Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 12/30/2025 has been entered into the prosecution for the application. Claims 12 and 13 have entered prosecution.
Claims 1, 4-13 are pending consideration.
Applicant’s amendment necessitate the new ground(s) of rejection presented in this Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 8, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Akai ( US 20100122839 A1) further in view of Nothdruft et. al. “Copper/Epoxy Joints in Printed Circuit Boards: Manufacturing and Interfacial Failure Mechanisms.” Materials, 2019, 12, 550.
Regarding Claim 1, Akai teaches a method for producing a multilayer printed wiring board comprising:
A copper clad laminate is formed by laminating copper foil (Element 18, Fig. 2a) onto an epoxy resin (Element 11, Fig. 2a), corresponding to a supporting substrate. [0053]
On the substrate is formed interlayer resin insulation layer (Element 12, Fig. 2G), corresponding to a first insulating layer. [0058]
Opening portions (Element 16, Fig. 3A) are formed on the insulation layer 12 using a CO2 gas laser. [0059]
An electroless copper plated film (Element 22, Fig. 3B) is formed on the insulation layer, including the inner-wall surfaces of the opening portions, corresponding to forming a seed layer on the first insulation layer. [0061]
A photosensitive dry film was laminated on electroless copper plated film, and a mask was placed thereon, exposed and developed. The plating resist (Element 13, Fig. 3D) was 25 microns thick, corresponding to a resist pattern for the writing part on a surface of the seed layer. [0061]
An electrolytic copper film was plated in areas where the plating resist was not formed, corresponding to forming a wiring part [0062] The plating resist was then removed by etching away the electroless copper-plated film, thereby forming conductive circuit (Element 14 Fig. 4A) [0063], corresponding to removing the resist pattern and the seed layer exposed by removal of the resist layer. These steps can be repeated multiple times to form multilayer circuit board, where in the outermost layer the conductive circuit includes via conductors (understood to be wiring) and solder pads (Element 34, Fig. 4B-5A), thus teaching that the outer conductive circuit includes a wiring part and a pad part. [0064]
Onto the surface of the solder pads are applied a solution of Y-amino propyltriethoxysilane [0068], in order to provide “notable adhesiveness” between the solder pad and the subsequent solder resist layer, corresponding to the first surface treatment and the second insulating layer.
A solder resist layer (element 24, Fig. 6a) is then formed on the surface of the surface of the solder pads, [0069] in which the photomask contains patterns for providing openings (element 28, Fig. 6A), corresponding to the formation of the second insulating layer and forming an opening in said second insulating layer.
Akai states that after phototreatment, solder-bump openings are formed [0070]. Subsequently, that is, while there are openings in the solder resist composition layer, the solder resist composition layer was cured through heat treatment, such as at 150 °C for 1 hour [0070], which corresponds to heating the second insulating material to the glass transition temperature or higher. Notably, applicant indicates that the required glass transition can be a temperature between 30 and 250 °C (Specification of the instant application, [0050]). The pad surface was exposed to an etching solution, containing nitric acid and hydrogen peroxide, to remove residue remaining in the opening (element 28), corresponding to a second surface treatment [0071].
The instant claim requires that the second surface treatment precede the heat treatment. The instant specification demonstrates that the second surface treatment is performed to remove organic components from the surface of the pad [0014]. The courts have held that a prima facie case of obviousness exists where the sequence of steps are reversed and no other distinction is found (see MPEP 2144.05 IV C). As the second surface treatment of Akai performs the same function as the second surface treatment of the instant application, barring a demonstration of critically regarding the arrangement of steps, it is understood that Akai teaches fully to the instant claim.
However, Akai does not teach that the first surface treatment is a surface-treated layer including an organic compound.
Nothdruft teaches a plurality of methods for promoting adhesion between a Cu surface and an epoxy layer in printed circuit boards [abstract].
Nothdruft teaches a method of promoting interfacial adhesion wherein azole based (that, an organic compound), specifically “GliCap” [see Sec. 2.2.2], which is the same as used by applicant [instant specification para. 0068], can be substituted for “silanol groups”, understood the be descriptive of the method which uses silanes [see Sec. 2.2.1], in order to create adhesion between a copper surface and an epoxy resin.
Prior to the filing of the present invention it would have been obvious to one of ordinary skill in the art that the use of a silanol based adhesion promoter, as per Akai, could be substituted for the use of GliCap azole based derivatives, as per Nothdruft, in order to arrive at a method of producing a printed circuit board using an organic compound as a first surface treatment with a reasonable expectation of success. Further, as the combined method for forming a printed circuit board as per Akai in view of Nothdruft features the same process steps as the instant application, it is understood that the process of forming a calcined layer and the amelioration of the conductivity decrease as taught as a matter of inherency (see MPEP 2112).
Regarding Claim 4, Akai teaches a “desmear treatment” [0041] is applied to “remove residue remaining in the opening portions formed in the solder resist layer” (corresponding to the second surface treatment) in which a “silane coupling agent” [0039] (corresponding to the first surface treatment) is being removed.
Regarding Claim 8, Akai teaches a photosensitive resin was used to create the solder resist layer and subsequent openings, after a photomask was applied and UV radiation was exposed to develop the layer. [0069-0070].
Regarding Claim 10, Akai teaches that the interlayer resin, corresponding to the first insulating layer, may be a thermosetting resin [0028] and that solder resist layer may be formed of a thermosetting resin [0097]. As applicant notes in their specification (Pg. 15), the first insulating material layer may be a “thermosetting resin” which is understood to be equivalent to the teaching of Akai.
However, Akai does not teach that the first and second insulating layers are the same material.
Prior to the filing of the present invention it would have been obvious to one of ordinary skill in the art that of the list of materials from which the first and second insulating materials may be selected choosing both the first and second insulating layers to both be a thermosetting resin would have been obvious to try, as it would result in the predictable formation of a multi-layered circuit board with multiple layers of insulating material (see MPEP 2143 E).
Regarding Claim 11, Akai teaches that after forming the openings in the second insulating layer, the solder resist composition layer was cured through heat treatment, such as at 150 °C for 1 hour [0070]. Notably, applicant indicates that the required glass transition can be a temperature between 30 and 250 °C (Specification of the instant application, [0050]). As the device taught by Akai is the same as the instant claim, it is understood that under the principle of inherency, as Akai teaches the same method of heating above a glass temperature after exposing a pad surface, Akai inherently discloses that a calcined layer will form at the interface between the wiring part and the second insulating layer material (see MPEP 2112.02 I).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Akai ( US 20100122839 A1) further in view of Nothdruft et. al. “Copper/Epoxy Joints in Printed Circuit Boards: Manufacturing and Interfacial Failure Mechanisms.” Materials, 2019, 12, 550, as applied to Claim 1, further in view of Ueki (US 20130326874 A1).
Regarding Claim 12, As demonstrated above, Akai teaches a multilayer printed circuit board that meets the limitations required by Claim 1.
However, Akai does not teach a peel strength of the wiring. Akai does not teach a step of removing residues between the steps of forming the first insulating layer and the step of depositing a metallic seed layer. Akai does not teach dimensions for the openings of the conductive circuit components, only a thickness of the resin layer.
Ueki teaches of producing a multilayer substrate, [0120], thus being in the same field of endeavor as Akai.
Ueki additionally teaches that the peel strength is at least 0.6 kN/m for producing a multilayer substrate with practical utility, [0266]. Akai teaches that the adhesiveness (the peel strength) is evaluated to determine whether the components of the printed circuit board that were fashioned together remain adhered to one another after reflow to ensure that the circuit board is functional. The range Ueki teaches falls within the claimed range (MPEP 2155.05 I). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Akai in view of Nothdruft, as per Ueki to meet a minimum standard of 0.6 kN/m in peel strength of the wiring component and the insulating layer to ensure that the method of producing a multilayer printed circuit taught by Akai in view of Nothdruft produces a functional device.
Regarding Claim 13, Ueki teaches that the interconnect pattern had a line width of 15 micron and a line-to-line spacing of 15 microns [0251]. Prior to the effective filing date it would have been obvious to one of ordinary skill to have incorporated the teachings of Ueki into Akai in view of Nothdruft to produce patterned features with 15-micron line widths as one of ordinary skill would have found it obvious to try (MPEP 2143 I E).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Akai ( US 20100122839 A1) further in view of Nothdruft et. al. “Copper/Epoxy Joints in Printed Circuit Boards: Manufacturing and Interfacial Failure Mechanisms.” Materials, 2019, 12, 550, as applied to Claim 1, further in view of Nishimura (US 20200344870 A1).
As demonstrated above, Akai in view of Nothdruft teaches a multilayer printed circuit board that meets the limitations required by Claim 1.
However, Akai does not teach an average surface roughness of a wiring part.
Nishimura teaches a method for producing a circuit board such that when the “arithmetic mean roughness” of the metal layer is 30 to 100 nm the adhesion between the resin layer and the metal layer can be further improved when producing the circuit board. [0088].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Akai with the teachings of Nishimura to select from within the range of arithmetic mean surface roughness taught by Nishimura, in order that the adhesiveness between the insulating layer and the metal wiring layer is improved. (MPEP 2144.05 I).
Claims 6, 7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Akai ( US 20100122839 A1) further in view of Nothdruft et. al. “Copper/Epoxy Joints in Printed Circuit Boards: Manufacturing and Interfacial Failure Mechanisms.” Materials, 2019, 12, 550, as applied to Claim 5, further in view of Ueki (US 20130326874 A1).
As demonstrated above, Akai in view of Nothdruft teaches a multilayer printed circuit board that meets the limitations required by Claim 1.
However, Akai in view of Nothdruft does not teach a peel strength of the wiring. Akai in view of Nothdruft does not teach a step of removing residues between the steps of forming the first insulating layer and the step of depositing a metallic seed layer. Akai in view of Nothdruft does not teach dimensions for the openings of the conductive circuit components, only a thickness of the resin layer.
Regarding Claim 6, Ueki teaches of producing a multilayer substrate, [0120], thus being in the same field of endeavor as Akai.
Ueki additionally teaches that the peel strength is at least 0.6 kN/m for producing a multilayer substrate with practical utility, [0266]. Akai teaches that the adhesiveness (the peel strength) is evaluated to determine whether the components of the printed circuit board that were fashioned together remain adhered to one another after reflow to ensure that the circuit board is functional. The range Ueki teaches falls within the claimed range (MPEP 2155.05 I). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Akai in view of Nothdruft as per Ueki to meet a minimum standard of 0.6 kN/m in peel strength of the wiring component and the insulating layer to ensure that the method of producing a multilayer printed circuit taught by Akai produces a functionally device.
Regarding Claim 7, Ueki teaches a method for producing a multilayer circuit board, featuring a desmear method. After boring holes on a supporting substrate, forming an insulating layer, and depositing a metal layer, a desmear treatment using plasma etching and an acidic solution can remove the metal or metal ion on the insulating layer and resin residues deposited on the bottom of the holes [0023 and 0243-0244]. Following the removal of the residues by the desmear method, an electroless plating step is employed [0246]. Doing a desmear method improves the adhesion of the metal film and the insulating layers. [0006-0007]. Prior to the effective filing date, it would have been obvious to one of ordinary skill to have incorporated the teachings of Ueki into Akai in view of Nothdruft in order that the base device of the printed circuit board would be improved in a predictable and obvious way by the addition of the desmearing method taught by Ueki to improve the reliability of the printed circuit board performance. (MPEP 2144 I C)
Regarding Claim 9, Ueki teaches that the interconnect pattern had a line width of 15 micron and a line-to-line spacing of 15 microns [0251]. Prior to the effective filing date it would have been obvious to one of ordinary skill to have incorporated the teachings of Ueki into Akai in view of Nothdruft to produce patterned features with 15-micron line widths as one of ordinary skill would have found it obvious to try (MPEP 2143 I E).
Response to Arguments
Applicant's arguments filed 8/26/2025 have been fully considered and are not persuasive.
Applicant argues the amended claims more clearly define the necessity of the arrangement of steps presented in order to achieve the remarkable results of high adhesion, insulation, and fine-pitch writing. While the amendment does necessitate the new grounds of rejection presented above, the arguments bearing to the obviousness rejection wherein the order of the steps (K) and (L) was not found to be critical, has not been addressed in a persuasive manner. As stated in the above rejection, it is evident that the second surface treatment of Akai, which teaches the total removal of organic residues found on the pad surface [0071], which is the same express purposes as in the present application [see instant specification 0077], such that the resulting change in the conductivity would occur only after this second surface treatment process. As the heating step relates to the calcination process and the surface treatment pertains to the removal of the conductivity reducing surface species, it does not matter the order in which these steps will occur, as the result will be the same in both cases, as each step produces a result unique to that step.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHANAEL J DOWNES whose telephone number is (571)272-1141. The examiner can normally be reached 8am to 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Lin can be reached at (571) 272-8902. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHANAEL JASON. DOWNES
Examiner
Art Unit 1794
/NATHANAEL JASON DOWNES/
Examiner, Art Unit 1794
/BRIAN W COHEN/Primary Examiner, Art Unit 1759