DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/13/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant' s arguments with respect to claim 1 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Based on the previously cited prior art Mishra425, Chen, Park, Nakajima, Lidow and new reference Mishra578 (US20130264578A1) the claims 1 - 13 and 21 - 22 are rejected.
Response to Amendment
Applicant’s amendment to claim 7 and 13 has been considered and resolve the claim objections. The claim objections has been withdrawn.
Applicant’s amendments to claims 4-7 has been fully considered and resolve the 35 U.S.C. 112(b) rejections. The 35 U.S.C. 112(b) rejection has been withdrawn. However, the amendments have introduced an objection as seen in Claim objections section.
Claim Objections
Claims 1-2 and 6-7 are objected to because of the following informalities:
Claim 1 recites “a depletion-mode-mode transistor”; this should be written as “a depletion-mode transistor”
Claim 2 recites “the III-N material structure”; this should be written as “the III-N layer structure”
Claim 6 recites “the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm”; this should be written as “the thickness of the second AlxGa1-xN layer is between 0.5 nm and 5 nm.”
Claim 7 recites “a doping density greater than the n-type GaN layer and the p-type III-N depleting layer”; this should be written as “a doping density greater than the first n-type GaN layer and the p-type III-N depleting layer.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 21 recites the limitation “device region" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 22 is rejected due to its dependency on claim 21.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. (US20130264578A1; hereinafter Mishra578).
PNG
media_image1.png
548
340
media_image1.png
Greyscale
Mishra: FIG. 2
Regarding Claim 1, (Currently Amended) Mishra578 discloses a III-N device (N-polar III-Nitride E-mode device, [0017]), comprising:
a III-N layer structure comprising a III-N channel layer (III-N channel layer 16) between a III-N barrier layer (back-barrier III-N layer 14) and a p-type III-N depleting layer (III-N layer 18), wherein the III-N channel layer includes a 2DEG channel formed therein (channel layer 16 includes a 2DEG channel 19), FIG. 2 reproduced above, [0020], [0021];
a source electrode (source contact 21) and a drain electrode (drain contact 22), each of which being electrically connected to the 2DEG channel (2DEG channel 19), FIG. 2, [0018];
a gate electrode (gate 23) between the source (21) and the drain (22), the gate (23) being over the III-N layer structure (layers 12, 14, 16, and 18), FIG. 2, [0018]; wherein
the p-type III-N depleting layer (18) includes a first portion that is between the gate electrode and the drain electrode (a portion of 18 extends between gate 23 and drain 22, [0028]) and a second portion that is below the gate electrode (a portion of 18 is below gate 23, [0027]); and
the p-type III-N depleting layer (18) is electrically connected to the gate electrode (18 is electrically connected to gate 23 in device without insulator 20, [0027]) and electrically isolated from the source and drain electrodes [0028].
Mishra578 [0028] discloses in some implementations at least a portion of layer 18 extends over the portion of 2DEG channel 19 in the access regions. Therefore the layer 18 may be electrically isolated from source 21 and drain 22 when the implementation includes only a portion of 18 over the 2DEG channel 19.
Mishra578 discloses all the claim limitations except for “III N device is a depletion-mode transistor”.
However, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F.2d 1647 (1987). Therefore, as Mishra578 teaches the claimed structure IIIN transistor, the limitation is met.
Regarding Claim 2, (Original) Mishra578 discloses the device of claim 1, wherein the III-N material structure (layers 12, 14, 16, and 18) is grown in an N-polar orientation (layers 12, 14, 16, and 18 are N-polar III-N layers, oriented as shown in the [0 0 0 −1] direction), [0018].
Regarding Claim 4, (Currently Amended) Mishra578 discloses the device of claim 1, further comprising a first AlxGa1-xN (additional AlN layer or AlzGa1-zN layer) between the p-type III-N depleting layer (18) and the III-N channel layer (16), wherein x is between 0.5 and 1 (additional AlN layer or AlzGa1-zN layer with z>0.5 or z>0.8, [0040]), and the thickness of the first AlxGa1-xN layer is between 0.5 nm and 5 nm [0024], [0030].
Mishra578 [0024], [0030] discloses the compositions and thicknesses of the layers in transistor are selectable variables that can minimize the resistance of the channel in the device access regions. It would be obvious to adjust the thicknesses of the first AlxGa1-xN layer to the range of 0.5 to 5 nm through routine optimization in order to reduce the access resistance of the device.
Regarding Claim 8, Mishra578 discloses the device of claim 1, wherein the p-type III-N depleting layer (18) includes a first end adjacent the drain electrode (22) and a separation from the first end to the drain electrode is between 0.5 μm and 5 μm, FIG. 1, [0028].
Mishra578 FIGS. 1 & 2, [0028] discloses in some implementations, layer 18 extends all the way from source 21 to drain 22, or at least a portion of layer 18 is over the portion of 2DEG channel 19 in the access regions, indicating the layer 18 may include a first end adjacent to 22 separated from the drain 22 and the separation distance can be varied. It would be obvious to select the separation distance of 0.5 μm and 5 μm through routine optimization to ensure access regions is not depleted of mobile charge.
Claims 3, 9, 10, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra578 in view of Mishra et al. (US20180102425A1; hereinafter Mishra425).
Regarding Claim 3, Mishra578 discloses the device of claim 1.
Mishra578 does not disclose “wherein a dopant concentration in the p-type III-N depleting layer is such that an areal p-type doping density in the p-type III-N layer is in the range of 10-150% of an areal sheet charge density of mobile charge in the 2DEG channel.”
In a similar art, Mishra425 discloses a III-N transistor device, FIG.1, [0017].
Mishra425 discloses: wherein a dopant concentration in the p-type III-N depleting layer (104) is such that an areal p-type doping density in the p-type III-N layer is in the range of 10-150% of an areal sheet charge density of mobile charge in the 2DEG channel (116), [0019].
Mishra425 [0019] discloses the areal mobile charge density or the p-type doping density in the p-type layer can be in the range of 50-75% of the areal sheet charge density of the electrons in the 2DEG channel 116, which falls within the range of 10-150% of an areal sheet charge density of mobile charge in the 2DEG channel 116.
Mishra425 discloses that a device as taught enables achieving an appropriate p-type doping density to 2DEG charge density ratio to obtain the desired operating characteristics of the device [0019]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578’s device in order to obtain the desired operating characteristics of the device as disclosed by Mishra425 [0019].
Regarding Claim 9, Mishra578 discloses the device of claim 8.
Mishra578 does not disclose “wherein the gate electrode includes a field plate, and the field plate at least partially extends over the first portion of the p-type III-N depleting layer.”
Mishra425 discloses: wherein the gate electrode (114) includes a field plate (field plate 122), and the field plate at least partially extends over the first portion (drain side access region of 104) of the p-type III-N depleting layer (104), FIG. 1, [0022].
Mishra [0022] discloses the field plate 122 directly contacts 104 and FIG.1 shows the field plate 122 extends over the gate 114 and at least a portion of the first portion (drain side access region of 104).
Mishra425 discloses that a device as taught enables more uniform field before breakdown occurs, and hence a larger breakdown voltage [0024]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578’s device in order to increase the breakdown voltage as disclosed by Mishra425 [0024].
Regarding Claim 10, Mishra578 discloses the device of claim 8.
Mishra578 does not disclose “wherein the drain electrode includes a field plate, and a portion of the field plate at least partially extends over the first portion of the p-type III-N depleting layer.”
Mishra425 discloses: wherein the drain electrode (112) includes a field plate (122), and a portion of the field plate at least partially extends over the first portion of the p-type III-N depleting layer (122 extends over the drain side access region of 104), FIG. 1, [0022].
Mishra [0022] discloses the field plate 122 directly contacts 104 and FIG.1 shows the field plate 122 extends towards the drain 112 and at least a portion of the first portion (drain side access region of 104).
Mishra425 discloses that a device as taught enables more uniform field before breakdown occurs, and hence a larger breakdown voltage [0024]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578’s device in order to increase the breakdown voltage as disclosed by Mishra425 [0024].
Regarding Claim 12, Mishra578 discloses the device of claim 1.
Mishra578 discloses: AlxGa1-xN layer wherein x is between 0.5 and 1, [0023], [0040]).
Mishra578 discloses implementations of the IIIN device including AlGaN layers with AlN layer or AlxGa1-xN layer, preferably with x>0.5 and AlzGa1-zN layer with z>0.5 or z>0.8, [0023], [0040].
the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm [0024], [0030].
Mishra578 [0024], [0030] discloses the compositions and thicknesses of the layers in transistor are selectable variables that can minimize the resistance of the channel in the device access regions. It would be obvious to adjust the thickness of the AlxGa1-xN layer to the range of 0.5 to 5 nm through routine optimization in order to reduce the access resistance of the device.
Mishra578 does not disclose “wherein the p-type III-N depleting layer includes a plurality of p-type layers over the III-N channel layer where each layer is separated by an AlxGa1-xN layer”
Mishra425 discloses: wherein the p-type III-N depleting layer (104) includes a plurality of p-type layers (superlattice 104) over the III-N channel layer (106) where each layer is separated by an AlGaN layer, [0017].
Mishra425 discloses the p-type III-N layer 104 is formed over the channel layer 106 and the p-type-III-N layer 104 can be a superlattice formed of alternating layers of GaN and AlGaN, [0017].
Mishra425 discloses that a device as taught improves the efficiency and output characteristics of the III-N transistor [0003]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578’s device in order to improve the efficiency and output characteristics as disclosed by Mishra425 [0003].
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Mishra578 in view of Park et al. (US20130082276A1; Park).
Regarding Claim 5, Mishra578 discloses the device of claim 4.
Mishra578 does not disclose “further comprising a first n-type GaN layer between the gate electrode and the p-type III-N depleting layer.”
In a similar art, Park discloses nitride semiconductor device [0004].
Park discloses: further comprising a first n-type GaN layer (140) between the gate electrode (70) and the p-type III-N depleting layer (40), FIG. 3, [0046].
Park discloses that a device as taught providing a nitride layer suppresses gate leakage current [0047]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578’s device in order to suppress gate leakage current as disclosed by Park [0047].
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Mishra578 in view of Lidow et al. (US20100258843A1; Lidow).
Regarding Claim 11, Mishra578 discloses the device of claim 8.
Mishra578 does not disclose “wherein a sidewall angle of the first end relative to a bottom surface of the p-type III-N depleting layer is between 10-80 degrees.”
In a similar art, Lidow discloses a transistor device 200 with sloped edges of the p-type GaN material 15, FIG. 8, [0041].
Lidow discloses: wherein a sidewall angle of the first end relative (end of 15 facing drain contact 19) to a bottom surface of the p-type III-N depleting layer (bottom surface of 15) is between 10-80 degrees, FIG. 8, [0041].
Lidow FIG. 8, [0041] discloses the p-type GaN material 15 has been etched such that the bottom of the material is more than 10% wider than the top of the material, leading to sloped edges, indicating the sidewall angle for the first end of 15 relative to its the bottom surface may be between 10-80 degrees.
Lidow discloses that the device as taught with sloped angles reduces the gate leakage current of the device [0042]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578’s device in order to reduce the gate leakage current as disclosed by Lidow [0042].
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Mishra578 in view of Nakajima et al. (US20130221409A1; hereinafter Nakajima).
Regarding Claim 21 (Currently Amended), Mishra578 discloses the device of claim 1.
In a similar art, Nakajima discloses III-Nitride semiconductor devices [0004].
Mishra578 does not disclose “wherein the III-N device is configured such that;
when the gate is biased relative to the source electrode at a negative voltage above a first minimum voltage, the 2DEG channel extends continuously from the source electrode to the drain electrode; and when the gate is biased relative to the source electrode at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrodes, and wherein the first minimum voltage is below -5V.”
In a similar art, Nakajima discloses III-Nitride semiconductor devices [0004].
Nakajima discloses: wherein the III-N device (transistor 500) is configured such that;
when the gate (530) is biased relative to the source electrode (535) at a negative voltage above a first minimum voltage, the 2DEG channel (2DEG 545) extends continuously from the source electrode (535) to the drain electrode (525), FIG. 5, [0104].
Nakajima [0104] discloses in the depletion mode n-channel transistor 500 has a negative threshold voltage and therefore is a ‘normally on’ type of transistor, i.e. when VGS=0, negative charge carriers (electrons) flow from drain electrode 525 to source electrode 535 until saturation is reached, indicating when the gate is biased relative to the source at a negative voltage above the first minimum voltage, the 2DEG channel 545 extends continuously from source to drain.
and when the gate (530) is biased relative to the source electrode (535) at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer (520) is depleted of holes in the device region between the gate (530) and drain (525) electrodes and wherein the first minimum voltage is below -5V, FIG. 5, [0104].
Nakajima [0104] discloses reducing VGS from zero to a negative voltage of magnitude greater than the threshold voltage causes a depletion region around the gate electrode to expand so as to ‘pinch off’ the channel, indicating that when the gate is biased below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes between the gate and drain.
Nakajima [0104] discloses reducing VGS from zero to a negative voltage of magnitude greater than the threshold voltage causes a depletion region around the gate electrode to expand so as to ‘pinch off’ the channel, indicating a negative first minimum voltage, which may be selected to be below -5V through routine optimization to improve breakdown voltage.
Nakajima discloses that a device as taught allows the voltage to reach high levels before breakdown occurs [0104]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578’s device in order to improve the breakdown voltage of the devices as disclosed by Nakajima [0104].
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Mishra578 in view of Nakajima, further in view of Mishra425.
Regarding Claim 22, The combination of Mishra578 and Nakajima discloses the device of claim 21.
The combination of Mishra578 and Nakajima does not disclose “wherein the device is configured such that, when the gate is biased above the first minimum voltage and the drain electrode is biased above a second minimum voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrode, wherein the second minimum voltage is above 5V.
Mishra425 discloses: wherein the device is configured such that, when the gate (114) is biased above the first minimum voltage and the drain electrode (112) is biased above a second minimum voltage, the p-type III-N layer (104) is depleted of holes in the device region between the gate (114) and drain electrode (112), wherein the second minimum voltage is above 5V (the minimum drain voltage can for example be between 20V and 100V), [0023], [0024].
Mishra425 [0023] discloses when the gate 114 is biased relative to the source 110 at a voltage that is greater than the threshold voltage of the device, there is a 2DEG charge below the gate 114 in the gate region, and therefore a continuous 2DEG from the source 110 to the drain 112; [0024] discloses electrons from the portion of the 2DEG in the drain-side access region deplete out, and the p-region in p-type layer 104 is also progressively depleted of holes at voltages greater than a minimum drain voltage between 20V and 100V.
Mishra425 discloses that a device as taught improves the efficiency and output characteristics of the III-N transistor [0003]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578 and Nakajima’s device in order to improve the efficiency and output characteristics as disclosed by Mishra425 [0003].
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra578 in view of Park, further in view of Chen et al. (CN111293173A; hereinafter Chen).
Regarding Claim 6 (Currently Amended), The combination of Mishra578 and Park discloses the device of claim 5.
The combination of Mishra 578 and Park does not disclose “further comprising a second AlxGa1-xN layer between the first n-type GaN layer and the p-type III-N depleting layer, wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm.”
In a similar art, Chen discloses a III-nitride device, FIG. 1, [0051].
Chen discloses a n-type GaN epitaxial layer 2, a GaN channel layer 3, an AlGaN barrier layer 5, a p-type GaN capping layer 7 are arranged sequentially from bottom to top, FIG. 1, [0039], [0041].
The combination of Mishra578, Park, and Chen discloses: further comprising a second AlxGa1-xN layer (Chen: aluminum nitride layer 5) between the first n-type GaN layer (Park: 140) and the p-type III-N depleting channel layer (Park: 40), wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm, Chen: [0015], [0016].
Chen [0015] discloses the layer 5 may be AlN or AlxGa(1-x)N where x > 0.3.
AlN corresponds to AlxGa(1-x)N with x value of 1, hence the first AlxGa1-xN layer may have a value of x between 0.3 and 1 which includes the claim range of x between 0.5 and 1.
Chen [0016] discloses the thickness of the layer 5 is greater than or equal to 0.5 nm and less than or equal to 3 nm, which is within the range of 0.5nm to 5nm.
Chen discloses that a device as taught prevents decrease in the concentration of two-dimensional electron gas and thereby preventing an increase in the on-resistance of the transistor [0006]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578 and Park’s device in order to prevent an increase in the on-resistance of the transistor as disclosed by Chen [0006].
Regarding Claim 7, The combination of Mishra578, Park, and Chen disclose the device of claim 6.
Chen discloses a n-type GaN epitaxial layer 2, a GaN channel layer 3, an AlGaN barrier layer 5, a p-type GaN capping layer 7 are arranged sequentially from bottom to top, FIG. 1, [0039], [0041].
Park [0046] discloses the n-type nitride layer 140 is formed on the p-type nitride layer 40.
The combination of Mishra578, Park, and Chen disclose: further comprising a second n-type GaN layer (Chen: 2) between the first n-type GaN layer (Park: 140) and the second AlxGa1-xN layer (Chen: 5), and a second p-type GaN layer (Chen: 7) between the p-type III-N depleting layer (Park:40) and the second AlxGa1-xN layer (Chen:5).
wherein the second n-type GaN layer and the second p-type GaN layer (Chen: layers 2 and 7) have a doping density greater than the first n-type GaN layer and the p-type III-N depleting layer (Park: 140 and 40).
Park [0046] discloses the doping level of the n-type nitride layer 140 is selected to reduce contact resistance, indicating the dopant density is a variable parameter affecting electrical performance. It would be obvious to adjust the doping density through routine optimization including the second n-type GaN layer and the second p-type GaN layer having a doping density greater than the first n-type GaN layer and the p-type III-N depleting layer in order to reduce contact resistance and improve performance.
Chen discloses that a device as taught prevents decrease in the concentration of two-dimensional electron gas and thereby preventing an increase in the on-resistance of the transistor [0006]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to prevent an increase in the on-resistance of the transistor as disclosed by Chen [0006].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mishra578 in view of Mishra425, further in view of Lidow.
Regarding Claim 13 (Amended), The combination of Mishra578 and Mishra425 discloses the device of claim 12.
The combination of Mishra578 and Mishra425 does not disclose “the separation of the first end to the drain electrode increases from the p-type layer proximal the III-N channel layer to the p-type layer distal the III-N channel layer.”
Mishra425 discloses: wherein each plurality of p-type layers (p-type layers in the superlattice in 104 which is formed over the channel layer 106) includes a first end adjacent to the drain electrode (end of 104 facing drain 112) and separated from the drain electrode 112, [0017].
Lidow FIG. 8, [0041] discloses the p-type GaN material 15 has been etched such that the bottom of the material is more than 10% wider than the top of the material, leading to sloped edges, indicating the separation of the first end to the drain electrode 19 increases from the p-type layer (15) proximal the III-N channel layer (13) to the p-type layer distal the III-N channel layer.
Lidow discloses that the device as taught with sloped angles reduces the gate leakage current of the device [0042]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra578 and Mishra425’s device in order to reduce the gate leakage current as disclosed by Lidow [0042].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to Krishna J Palaniswamy whose telephone number
is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM -
5PM EST.
Examiner interviews are available via telephone, in-person, and video
conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request
(AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number
for the organization where this application or proceeding is assigned is 571-483-7639.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is
available to registered users. To file and manage patent submissions in Patent Center,
visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-
center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For
additional questions, contact the Electronic Business Center (EBC) at 866-217-9197
(toll-free). If you would like assistance from a USPTO Customer Service
Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights