DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/06/2023 and 01/21/2026, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group I, and Claims 1-15 and 20-23 in the reply filed on 01/20/2026 is acknowledged. Claims 16-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/20/2026.
Claim Objections
Claim 7 and 14 are objected to because of the following informalities:
Claim 7 recites “the device of claim 6, further comprises a second n-type GaN layer”; this should be written as “the device of claim 6, further comprising a second n-type GaN layer”. Appropriate correction is required.
Claim 13 recites “ where each plurality of p-type layers”; this should be written as “wherein each plurality of p-type layers.”
Claim 14 recites “wherein the N-polar III-N layer structure is configure such that the 2DEG channel extends continuously”; this should be written as “wherein the N-polar III-N layer structure is configured such that the 2DEG channel extends continuously.”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation " the second AlyGa1-yN layer" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 recites the limitation " the first n-type GaN layer" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 7 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites “further comprises a second n-type GaN layer between the first n-type GaN layer and the second AlyGa1-yN layer” which is unclear because the claim or the base claims do not introduce a first AlyGa1-yN layer. For the purpose of examination, the Examiner interprets this limitation as “further comprises a second n-type GaN layer between the first n-type GaN layer and the second AlxGa1-xN layer.”
Claim 7 recites “a second p-type GaN layer between the p-type III-N depleting layer and the second AlyGa1-yN layer” which is unclear because the claim or the base claims do not introduce a first p-type GaN layer. For the purpose of examination, the Examiner interprets this limitation as “a p-type GaN layer between the p-type III-N depleting layer and the second AlxGa1-xN layer.”
Claim 7 recites “wherein the second n-type GaN layer and the second p-type GaN layer have a doping density greater than the n-type GaN layer and the p-type III-N depleting layer” which is unclear whether the second n-type GaN layer and the second p-type GaN layer have a doping density greater than the n-type GaN layer or the first n-type GaN layer. For the purpose of examination, the Examiner interprets this limitation as “wherein the second n-type GaN layer and the second p-type GaN layer have a doping density greater than the first n-type GaN layer and the p-type III-N depleting layer.”
Claim 10 is rejected due to its dependency on claim 7.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 3, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra et al. (US20180102425A1; hereinafter Mishra) in view of Jeon (US20140021480A1; hereinafter Jeon).
Regarding Claim 1, Mishra discloses a III-N device (III-N transistor device, FIG. 1 reproduced below, [0017]) comprising:
a III-N layer structure comprising a III-N channel layer (III-N channel layer 106) between a III-N barrier layer (III-N barrier layer 108) and a p-type III-N depleting layer (p-type III-N layer 104), wherein the III-N channel layer (106) includes a 2DEG channel (2DEG channel 116) formed therein, FIG. 1, [0018];
a source electrode (110) and a drain electrode (112), each of which being electrically connected to the 2DEG channel, (Source and drain contacts 110 and 112, respectively, are on opposite sides of the gate 114 and contact the device 2DEG channel 116 that is formed in layer 106, FIG. 1, [0018]);
a gate electrode (114) between the source (110) and the drain (112), the gate (114) being over the III-N layer structure, FIG. 1, [0018]; wherein
the p-type III-N depleting layer (104) includes a first portion (drain side access region of 104) that is between the gate electrode (114) and the drain electrode (112), FIG. 1, [0019]. Mishra [0019] discloses the p-type layer 104 has a portion located in the access region between gate and drain which is the drain side access region.
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Mishra: FIG. 1
Mishra does not disclose “the p-type III-N depleting layer is electrically connected to the gate electrode and electrically isolated from the source and drain electrodes.”
In a similar art, Jeon discloses semiconductor devices in particular high electron mobility transistors (HEMTs), [0003].
Jeon discloses: the p-type III-N depleting layer (DP10) is electrically connected to the gate electrode (G10) and electrically isolated from the source (S10) and drain (D10) electrodes, FIG. 1 reproduced below, [0088], [0089].
Jeon [0088] discloses the gate electrode G10 is disposed on the p-type depletion forming layer DP10 and may cover side and upper surfaces of DP10, indicating the DP10 is electrically connected to the gate electrode G10. Jeon [0088], [0089] discloses the insulating mask layer M10 electrically isolates the p-type depletion forming layer DP10 from source (S10) and drain (D10) electrodes.
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Jeon: FIG. 1
Jeon discloses that a device as taught improves operating characteristics of the devices [0008]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra’s device in order to improve the operating characteristics of the device as disclosed by Jeon [0008].
Regarding Claim 2, The combination of Mishra and Jeon discloses the device of claim 1.
Mishra discloses: wherein the III-N material structure is grown in an N-polar orientation (III- N layers 101, 108, 106, and 104 are N-polar III-N layers, oriented as shown in the [0 0 0−1] direction, FIG. 1, [0018]).
Regarding Claim 3, The combination of Mishra and Jeon discloses the device of claim 1.
Mishra discloses: wherein a dopant concentration in the p-type III-N depleting layer (104) is such that an areal p-type doping density in the p-type III-N layer is in the range of 10-150% of an areal sheet charge density of mobile charge in the 2DEG channel (116), [0019].
Mishra [0019] discloses the areal mobile charge density or the p-type doping density in the p-type layer can be in the range of 50-75% of the areal sheet charge density of the electrons in the 2DEG channel 116, which falls within the range of 10-150% of an areal sheet charge density of mobile charge in the 2DEG channel 116.
Regarding Claim 14, Mishra discloses a transistor (III-N transistor device, FIG. 1, [0017]), comprising:
an N-polar III-N layer structure comprising a III-N channel layer (106) between a III-N barrier layer (108) and a p-type III-N layer (104), FIG. 1, [0018]. Mishra [0018] discloses III- N layers 101, 108, 106, and 104 are N-polar III-N layers, oriented in the [0 0 0−1] direction.
a source electrode (110) and a drain electrode (112), FIG. 1, [0018];
a gate electrode (114) between the source (110) and the drain (112), the gate being over the III-N layer structure, FIG. 1, [0018];
a 2DEG channel (116) in the III-N channel layer (106), wherein the N-polar III-N layer structure is configured such that the 2DEG channel (116) extends continuously from the source electrode (110) to the drain electrode (112) when the gate is biased at 0V with respect to the source, [0021], [0023].
Mishra [0021] discloses if the depth of the recess below the gate is decreased, then the transistor can be a depletion-mode device, where the device is ON when 0V is applied to the gate relative to the source. Mishra [0023] discloses that in the ON state the 2DEG channel extends continuously from source 110 to drain 112, indicating the N-polar III-N layer structure is configured such that the 2DEG channel (116) extends continuously from the source electrode 110 to the drain electrode 112 when the gate is biased at 0V with respect to the source.
Mishra does not disclose “and the p-type III-N layer is electrically connected to the gate electrode”
In a similar art, Jeon discloses semiconductor devices in particular high electron mobility transistors, [0003].
Jeon discloses: the p-type III-N depleting layer (DP10) is electrically connected to the gate electrode (G10), FIG. 1, [0088].
Jeon [0088] discloses the gate electrode G10 is disposed on the p-type depletion forming layer DP10 and may cover side and upper surfaces of DP10, indicating the DP10 is electrically connected to the gate electrode G10.
Jeon discloses that a device as taught improves operating characteristics of the device [0007]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra’s device in order to improve the operating characteristics of the device as disclosed by Jeon [0007].
Regarding Claim 15, The combination of Mishra and Jeon disclose the transistor of claim 14.
Mishra discloses: wherein the p-type III-N layer (104) includes at least a first portion (drain side access region of 104) between the gate electrode (114) and the drain electrode (112), FIG. 1, [0019]. Mishra [0019] discloses the p-type layer 104 has a portion located in the drain side access region between gate and drain.
Claim 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of Jeon, further in view of Chen et al. (CN111293173A; hereinafter Chen).
Regarding Claim 4, The combination of Mishra and Jeon discloses the device of claim 1.
Mishra discloses the p-type III-N layer 104 is formed over the channel layer 106 and the p-type-III-N layer 104 can be a superlattice formed of alternating layers of GaN and AlGaN, [0017].
Mishra discloses: further comprising a first AlGaN layer (one of the alternating AlGaN layers within the superlattice 104) between the p-type III-N depleting layer (remaining alternating GaN and AlGaN layers of the superlattice 104) and the III-N channel layer (106), FIG. 1, [0017].
Mishra does not disclose “a first AlxGa1-xN layer; wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm.”
Jeon discloses: further comprising a first AlGaN layer (CS10) between the p-type III-N depleting layer (DP10) and the III-N channel layer (C10), wherein x is between 0.5 and 1 (CS10 is formed of AlN which corresponds to Al1Ga0N with x value of 1), and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm (thickness of about 5nm or greater), FIG. 1, [0082], [0083].
Jeon does not explicitly disclose the entire x and thickness ranges in “wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm.”
In a similar art, Chen discloses a III-nitride device, FIG. 1, [0051].
Chen discloses: further comprising a first AlxGa1-xN layer (layer 5) between the p-type III-N depleting layer (p-type GaN capping layer 7) and the III-N channel layer (channel layer 3), wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm, [0015], [0016].
Chen [0015] discloses the layer 5 may be AlN or AlxGa(1-x)N where x > 0.3.
AlN corresponds to AlxGa(1-x)N with x value of 1, hence the first AlxGa1-xN layer may have a value of x between 0.3 and 1 which includes the claim range of x between 0.5 and 1.
Chen [0016] discloses the thickness of the layer 5 is greater than or equal to 0.5 nm and less than or equal to 3 nm, which is within the range of 0.5nm to 5nm.
Chen discloses that a device as taught prevents decrease in the concentration of two-dimensional electron gas and thereby preventing an increase in the on-resistance of the transistor [0006]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra and Jeon’s device in order to prevent an increase in the on-resistance of the transistor as disclosed by Chen [0006].
Regarding Claim 12, The combination of Mishra and Jeon disclose the device of claim 1.
Mishra discloses: wherein the p-type III-N depleting layer (104) includes a plurality of p-type layers (superlattice 104) over the III-N channel layer (106) where each layer is separated by an AlGaN layer, [0017].
Mishra discloses the p-type III-N layer 104 is formed over the channel layer 106 and the p-type-III-N layer 104 can be a superlattice formed of alternating layers of GaN and AlGaN, [0017].
Mishra does not disclose “wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm.”
Jeon discloses: further comprising a first AlGaN layer (CS10) between the p-type III-N depleting layer (DP10) and the III-N channel layer (C10), where in x is between 0.5 and 1 (CS10 is formed of AlN which corresponds to Al1Ga0N with x value of 1), and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm (thickness of about 5nm or greater), FIG. 1, [0082], [0083].
Jeon does not explicitly disclose the entire x and thickness ranges in “wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm.”
In a similar art, Chen discloses a III-nitride device, FIG. 1, [0051].
Chen discloses: further comprising a first AlxGa1-xN layer (layer 5) between the p-type III-N depleting layer (p-type GaN capping layer 7) and the III-N channel layer (channel layer 3), wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm, [0015], [0016].
Chen [0015] discloses the layer 5 may be AlN or AlxGa(1-x)N where x > 0.3.
AlN corresponds to AlxGa(1-x)N with x value of 1, hence the first AlxGa1-xN layer may have a value of x between 0.3 and 1 which includes the claim range of x between 0.5 and 1.
Chen [0016] discloses the thickness of the layer 5 is greater than or equal to 0.5 nm and less than or equal to 3 nm, which is within the range of 0.5nm to 5nm.
Chen discloses that a device as taught prevents decrease in the concentration of two-dimensional electron gas and thereby preventing an increase in the on-resistance of the transistor [0006]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra and Jeon’s device in order to prevent an increase in the on-resistance of the transistor as disclosed by Chen [0006].
Claims 5 – 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of Jeon, further in view of Chen, still further in view of Park et al. (US20130082276A1; Park).
Regarding Claim 5, The combination of Mishra, Jeon, and Chen disclose the device of claim 4.
The combination of Mishra, Jeon, and Chen does not disclose “further comprising an n-type GaN layer between the gate electrode and the p-type III-N depleting layer.”
In a similar art, Park discloses nitride semiconductor device [0004].
Park discloses: further comprising an n-type GaN layer (140) between the gate electrode (70) and the p-type III-N depleting layer (40), FIG. 3, [0046].
Park discloses that a device as taught is capable of implementing normally-off characteristics and suppressing gate leakage current [0011]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra, Jeon, and Chen’s device in order to provide a nitride semiconductor device capable of implementing normally-off characteristics and suppressing gate leakage current as disclosed by Park [0011].
Regarding Claim 6, The combination of Mishra, Jeon, Chen, and Park disclose the device of claim 5.
The combination of Mishra and Jeon does not explicitly disclose “further comprising a second AlxGa1-xN layer between the n-type GaN layer and the p-type III-N depleting layer, wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm.”
Chen discloses: further comprising a first AlxGa1-xN layer (aluminum nitride layer 5) between the p-type III-N depleting layer (p-type GaN capping layer 7) and the III-N channel layer (gallium nitride channel layer 3), wherein x is between 0.5 and 1, and the thickness of the AlxGa1-xN layer is between 0.5 nm and 5 nm, [0015], [0016].
Chen [0015] discloses the layer 5 may be AlN or AlxGa(1-x)N where x > 0.3.
AlN corresponds to AlxGa(1-x)N with x value of 1, hence the first AlxGa1-xN layer may have a value of x between 0.3 and 1 which includes the claim range of x between 0.5 and 1.
Chen [0016] discloses the thickness of the layer 5 is greater than or equal to 0.5 nm and less than or equal to 3 nm, which is within the range of 0.5nm to 5nm.
Chen discloses that a device as taught prevents decrease in the concentration of two-dimensional electron gas and thereby preventing an increase in the on-resistance of the transistor [0006]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra, Jeon, and Park’s device in order to prevent an increase in the on-resistance of the transistor as disclosed by Chen [0006].
Regarding Claim 7, The combination of Mishra, Jeon, Chen, and Park disclose the device of claim 6.
Mishra discloses a p-type III-N layer 104 is formed over the n-type GaN channel layer 106, FIG. 1, [0017].
Chen discloses a GaN epitaxial layer 2, a GaN channel layer 3, an AlGaN barrier layer 5, a p-type GaN capping layer 7 are arranged sequentially from bottom to top, FIG. 1, [0039], [0041].
The combination of Mishra and Chen disclose: further comprises a second n-type GaN layer (Chen: 3) between the first n-type GaN layer (Mishra: 106) and the second AlxGa1-xN layer (Chen: 5), and a second p-type GaN layer (Chen: 7) between the p-type III-N depleting layer (Mishra: 104) and the second AlxGa1-xN layer (Chen:5), Mishra: FIG.1, [0017], Chen: FIG. 1, [0039], [0041].
wherein the second n-type GaN layer and the second p-type GaN layer (Chen: layers 3 and 7) have a doping density greater than the first n-type GaN layer and the p-type III-N depleting layer (Mishra: 106 and 104), Mishra: [0017], [0024], Chen: [0039].
Mishra [0017] discloses GaN layer 106 as unintentionally doped (UID) n-type GaN layer; and [0024] discloses the doping levels of p-type depleting layer 104 are chosen to achieve depletion, indicating the layers 104 and 106 may have a lower doping density. Chen [0039] discloses the layer 3 as a gallium nitride channel layer and layer 7 as a p-type GaN capping layer, indicating they are intentionally doped and may have a higher doping density than layers 106 and 104 (Mishra: FIG. 1).
Chen discloses that a device as taught prevents decrease in the concentration of two-dimensional electron gas and thereby preventing an increase in the on-resistance of the transistor [0006]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device in order to prevent an increase in the on-resistance of the transistor as disclosed by Chen [0006].
Regarding Claim 10, The combination of Mishra, Jeon, Chen, and Park disclose the device of claim 7.
Mishra discloses: wherein the drain electrode (112) includes a field plate (122), and a portion of the field plate at least partially extends over the first portion of the p-type III-N depleting layer (122 extends over the drain side access region of 104), FIG. 1, [0022].
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of Jeon, further in view Chowdhury et al. (US20140231823A1; Chowdhury).
Regarding Claim 8, The combination of Mishra and Jeon disclose the device of claim 1.
Mishra discloses: wherein the p-type III-N depleting layer (104) includes a first end adjacent the drain electrode (112), FIG. 1, [0017].
Mishra discloses the p-type III-N depletion layer 104 is at least between the gate 114 and the drain 112, FIG. 1, [0017], indicating the separation from the first end of the p type III-N depletion layer 104 adjacent to the drain electrode is lesser than the gate to drain spacing.
Mishra does not disclose “a separation from the first end to the drain electrode is between 0.5 μm and 5 μm.”
In a similar art, Chowdhury discloses a III-N transistor [0009].
Chowdhury discloses a gate-drain spacing LGD is less than 20 microns, FIG. 17, [0010], [0051].
The combination of Mishra and Chowdhury disclose: wherein the p-type III-N depleting layer includes a first end adjacent the drain electrode (Mishra: first end of 104 adjacent to drain 112) and a separation from the first end to the drain electrode is between 0.5 μm and 5 μm, (Chowdhury: FIG. 17, [0010], [0051]).
Chowdhury [0010], [0051] discloses a gate-drain spacing LGD is equal to or less than 20 microns, indicating the separation from the first end of the p type III-N depletion layer (Mishra: 104) adjacent to the drain electrode (Mishra: 112) is lesser than 20 microns, which may be in the range of 0.5 μm and 5 μm.
Chowdhury discloses that optimizing gate-drain spacing improves breakdown voltage of the device [0051]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra and Jeon’s device in order to improve breakdown voltage as disclosed by Chowdhury [0051].
Regarding Claim 9, The combination of Mishra, Jeon, and Chowdhury disclose the device of claim 8.
Mishra discloses: wherein the gate electrode (114) includes a field plate (field plate 122), and the field plate (122) at least partially extends over the first portion (drain side access region of 104) of the p-type III-N depleting layer (104), FIG. 1, [0022].
Mishra [0022] discloses the field plate 122 directly contacts 104 and FIG.1 shows the field plate 122 extends over the at least a portion of the first portion (drain side access region of 104).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of Jeon, further in view Chowdhury, still further in view of Lidow et al. (US20100258843A1; Lidow).
Regarding Claim 11, The combination of Mishra, Jeon, and Chowdhury disclose the device of claim 8.
The combination of Mishra, Jeon, and Chowdhury does not disclose “wherein a sidewall angle of the first end relative to a bottom surface of the p-type III-N depleting layer is between 10-80 degrees.”
In a similar art, Lidow discloses a transistor device 200 with sloped edges of the p-type GaN material 15, FIG. 8, [0041].
Lidow discloses: wherein a sidewall angle of the first end relative (end of 15 facing drain contact 19) to a bottom surface of the p-type III-N depleting layer (bottom surface of 15) is between 10-80 degrees, FIG. 8, [0041].
Lidow FIG. 8, [0041] discloses the p-type GaN material 15 has been etched such that the bottom of the material is more than 10% wider than the top of the material, leading to sloped edges, indicating the sidewall angle for the first end of 15 relative to its the bottom surface may be between 10-80 degrees.
Lidow discloses that the device as taught with sloped angles reduces the gate leakage current of the device [0042]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra, Jeon, and Chowdhury’s device in order to reduce the gate leakage current as disclosed by Lidow [0042].
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of Jeon, further in view of Chen, still further in view of Lidow.
Regarding Claim 13, The combination of Mishra, Jeon, and Chen disclose the device of claim 12.
Mishra discloses: where each plurality of p-type layers (p-type layers in the superlattice in 104 which is formed over the channel layer 106) includes a first end adjacent to the drain electrode (end of 104 facing drain 112) and separated from the drain electrode 112.
The combination of Mishra, Jeon, and Chen does not disclose “the separation of the first end to the drain electrode increases from the p-type layer proximal the III-N channel layer to the p-type layer distal the III-N channel layer.”
Lidow FIG. 8, [0041] discloses the p-type GaN material 15 has been etched such that the bottom of the material is more than 10% wider than the top of the material, leading to sloped edges, indicating the separation of the first end to the drain electrode 19 increases from the p-type layer 15 proximal the III-N channel layer 13 to the p-type layer 15 distal the III-N channel layer 13.
Lidow discloses that the device as taught with sloped angles reduces the gate leakage current of the device [0042]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra, Jeon, and Chen’s device in order to reduce the gate leakage current as disclosed by Lidow [0042].
Claims 20 – 23 are rejected under 35 U.S.C. 103 as being unpatentable over Mishra in view of Jeon, further in view of Nakajima et al. (US20130221409A1; hereinafter Nakajima).
Regarding Claim 20, Mishra discloses a III-N device (III-N transistor device, FIG. 1, [0017]) comprising:
a III-N layer structure comprising a III-N channel layer (106) and a 2DEG channel (116) therein, a III-N barrier layer (108) under the III-N channel layer (106), and a p-type III-N layer (104) over the III-N channel layer (106), FIG. 1, [0018];
a source electrode (110) and a drain electrode (112), FIG. 1, [0018]; and
a gate electrode (114) between the source electrode (110) and the drain electrode (112), the gate (114) being over the III-N layer, FIG. 1, [0018];
wherein the p-type III-N layer (104) includes a first portion (drain side access region of 104) that is between the gate (114) and the drain (112) electrodes, FIG. 1, [0019]. Mishra discloses the p-type layer 104 has a portion located in the drain side access region between gate and drain.
Mishra does not disclose “the gate electrically connected to the p-type III-N layer; wherein the III-N device has a negative threshold voltage; and wherein the III-N device is configured such that; when the gate is biased relative to the source electrode at a negative voltage above a first minimum voltage, the 2DEG channel extends continuously from the source electrode to the drain electrode; and when the gate is biased relative to the source electrode at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrodes.”
In a similar art, Jeon discloses semiconductor devices in particular high electron mobility transistors, [0003].
Jeon discloses: the p-type III-N depleting layer (DP10) is electrically connected to the gate electrode (G10), FIG. 1, [0088].
Jeon [0088] discloses the gate electrode G10 is disposed on the p-type depletion forming layer DP10 and may cover side and upper surfaces of DP10, indicating the DP10 is electrically connected to the gate electrode G10.
Jeon discloses that a device as taught improves operating characteristics of the device [0007]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra’s device in order to improve the operating characteristics of the device as disclosed by Jeon [0007].
The combination of Mishra and Jeon does not disclose “wherein the III-N device has a negative threshold voltage; and wherein the III-N device is configured such that;
when the gate is biased relative to the source electrode at a negative voltage above a first minimum voltage, the 2DEG channel extends continuously from the source electrode to the drain electrode; and when the gate is biased relative to the source electrode at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes in the device region between the gate and drain electrodes.”
In a similar art, Nakajima discloses III-Nitride semiconductor devices [0004].
Nakajima discloses: wherein the III-N device has a negative threshold voltage (reverse conducting transistor 500 operates as a depletion mode n-channel transistor with a negative threshold voltage, FIG. 5, [0104]); and
wherein the III-N device (transistor 500) is configured such that; when the gate (530) is biased relative to the source electrode (535) at a negative voltage above a first minimum voltage, the 2DEG channel (2DEG 545) extends continuously from the source electrode (535) to the drain electrode (525), FIG. 5, [0104].
Nakajima [0104] discloses in the depletion mode n-channel transistor 500 has a negative threshold voltage and therefore is a ‘normally on’ type of transistor, i.e. when VGS=0, negative charge carriers (electrons) flow from drain electrode 525 to source electrode 535 until saturation is reached, indicating when the gate is biased relative to the source at a negative voltage above the first minimum voltage, the 2DEG channel 545 extends continuously from source to drain.
and when the gate (530) is biased relative to the source electrode (535) at a voltage below the first minimum voltage and above the threshold voltage, the p-type III-N layer (520) is depleted of holes in the device region between the gate (530) and drain (525) electrodes, FIG. 5, [0104].
Nakajima [0104] discloses reducing VGS from zero to a negative voltage of magnitude greater than the threshold voltage causes a depletion region around the gate electrode to expand so as to ‘pinch off’ the channel, indicating that when the gate is biased below the first minimum voltage and above the threshold voltage, the p-type III-N layer is depleted of holes between the gate and drain.
Nakajima discloses that a device as taught allows the voltage to reach high levels before breakdown occurs [0104]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra and Jeon’s device in order to improve the breakdown voltage of the devices as disclosed by Nakajima [0104].
Regarding Claim 21, The combination of Mishra, Jeon, and Nakajima disclose the device of claim 20.
The combination of Mishra and Jeon does not disclose “wherein the first minimum voltage is below −5V.”
Nakajima discloses: wherein the first minimum voltage is below −5V, [0104].
Nakajima [0104] discloses reducing VGS from zero to a negative voltage of magnitude greater than the threshold voltage causes a depletion region around the gate electrode to expand so as to ‘pinch off’ the channel, indicating a negative first minimum voltage, which may be selected to be below -5V through routine optimization to improve breakdown voltage.
Nakajima discloses that a device as taught allows the voltage to reach high levels before breakdown occurs [0104]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Mishra and Jeon’s device in order to improve the breakdown voltage of the devices as disclosed by Nakajima [0104].
Regarding Claim 22, The combination of Mishra, Jeon, and Nakajima disclose the device of claim 20.
Mishra discloses: wherein the device is configured such that, when the gate (114) is biased above the first minimum voltage and the drain electrode (112) is biased above a second minimum voltage, the p-type III-N layer (104) is depleted of holes in the device region between the gate (114) and drain electrode (112), [0023], [0024].
Mishra [0023] discloses when the gate 114 is biased relative to the source 110 at a voltage that is greater than the threshold voltage of the device, there is a 2DEG charge below the gate 114 in the gate region, and therefore a continuous 2DEG from the source 110 to the drain 112; [0024] discloses electrons from the portion of the 2DEG in the drain-side access region deplete out, and the p-region in p-type layer 104 is also progressively depleted of holes at voltages greater than a minimum drain voltage between 20V and 100V.
Regarding Claim 23, The combination of Mishra, Jeon, and Nakajima disclose the device of claim 22.
Mishra discloses: wherein the second minimum voltage is above 5V (where the minimum drain voltage can for example be between 20V and 100V, [0024]).
Conclusion
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/Krishna J. Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899