DETAILED ACTION
1. This action is in response to the application filed on 2/13/23.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-5, 9, 11, 20, 22, 26-30, 32, 34-35, 37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 20190149032).
Regarding claim 1: Yang et al. disclose (i.e. figures 3-6 and 7A-7B) a method of operating a flyback converter (i.e. 5), the flyback converter comprising:
a transformer (i.e. 10) having a primary side winding (i.e. W1) and a secondary side winding (i.e. W2), a primary switch (i.e. QP) at the primary side (i.e. W1) of the transformer (i.e. 10) and a secondary switch (i.e. QSR) at the secondary side (i.e. W2) of the transformer (i.e. 10), and
a control unit (i.e. 503); the method comprising:
i) at the end of a switching cycle (i.e. cycle of VS), before turning on the primary side switch (i.e. QP): the control unit (i.e. 503) generating a Zero Voltage Switching (ZVS) pulse (i.e. pulse of ZVS/SR_ZVS) in the secondary side winding (i.e. W2) (i.e. ¶ 39-53), such that a parasitic capacitor (i.e. parasitic capacitor) of the primary side switch (i.e. QP) is discharged (i.e. ¶46); and
ii) consequently, turning on the primary side switch (i.e. QP) in ZVS or near ZVS conditions (i.e. ¶ 39-53),
wherein the converter includes a synchronizer unit (i.e. unit of 400),
wherein the method further includes a step of driving (i.e. by 400) the secondary side switch (i.e. QSR) combining a synchronous rectification signal (i.e. SR_sync), the ZVS pulse signal (i.e. pulse of ZVS/SR_ZVS) and a control pulse signal (i.e. signal VG),
wherein, when the synchronous rectification signal is high (i.e. figure 3: SR_sync high), the secondary switch (i.e. QSR) conducts current from its source terminal to its drain terminal (i.e. ¶ 38), transferring power from the transformer to an output capacitor (i.e. CO), and when the control pulse signal is high (i.e. figure 3: signal VG is high), the secondary switch (i.e. QSR) conducts current from a drain terminal to a source terminal, reflecting power from the output capacitor (i.e. Co) to the transformer (i.e. 10),
and wherein the method further includes the step of adjusting a power delivered (i.e. adjusting power at the output by the controller) to the output of the flyback converter (i.e. 5) by adjusting the duration (i.e. figure 3: on/off duration of signal VG) of the control pulse signal (i.e. signal VG) (i.e. ¶ 39-53).
Regarding claim 2: (i.e. figures 4-6 and 7A-7B) wherein the ZVS pulse (i.e. pulse of ZVS/SR_ZVS) in the secondary winding is generated when a local minimum voltage (i.e. VTR) at the drain terminal of the secondary side switch (i.e. QSR) is detected (i.e. ¶ 39-53).
Regarding claim 3: (i.e. figures 4-6 and 7A-7B) wherein the ZVS pulse (i.e. pulse of ZVS/SR_ZVS) is configured to turn on the secondary side switch (i.e. QSR) or the auxiliary side switch for a predefined time duration (i.e. ¶ 39-53).
Regarding claim 4: (i.e. figures 4-6 and 7A-7B) wherein the duration of the ZVS pulse (i.e. pulse of ZVS/SR_ZVS) is dependent on the parameters of the converter, such as input voltage or the output power (i.e. ¶ 39-53).
Regarding claim 5: (i.e. figures 4-6 and 7A-7B) wherein the duration of the ZVS pulse (i.e. pulse of ZVS/SR_ZVS) is less than a switching period (i.e. ¶ 39-53) or the cycle of the converter.
Regarding claim 9: (i.e. figures 4-6 and 7A-7B) wherein the control unit (i.e. unit of 400) implements a control scheme at a fixed frequency (i.e. ¶ 39-53).
Regarding claim 11: (i.e. figures 4-6 and 7A-7B) wherein a communication link exists between the primary side (i.e. W1) and the secondary side (i.e. W2), and wherein the communication link uses one or a combination of the following: a capacitive link, an inductive link, a proximity antenna or an integrated power and a signal transformer (i.e. 20).
Regarding claim 20: (i.e. figures 4-6 and 7A-7B) wherein the control pulse signal (i.e. signal VG) is configured to rise at a synchronous rectification signal falling edge (i.e. see signals of figure 3).
Regarding claim 22: (i.e. figures 4-6 and 7A-7B) the synchronizer unit (i.e. unit of 400) is configured to synchronize the ZVS pulse (i.e. pulse of ZVS) with a primary side drain voltage valley or a local peak (i.e. ¶ 39-53).
Regarding claim 26: (i.e. figures 4-6 and 7A-7B) which the control unit (i.e. unit of 400) is configured to send a ZVS request (i.e. ¶ 39-53).
Regarding claim 27: (i.e. figures 4-6 and 7A-7B) which the control unit (i.e. unit of 400) is configured to send a turn-on request to the primary side switch (i.e. QP) (i.e. ¶ 39-53).
Regarding claim 28: (i.e. figures 4-6 and 7A-7B) wherein the control unit (i.e. unit of 400) is configured to send ZVS pulses (i.e. pulse of ZVS/SR_ZVS) or turn-on requests to the primary side, and wherein parameters of pulses define a primary side switch duty cycle (i.e. ¶ 39-53).
Regarding claim 29: (i.e. figures 4-6 and 7A-7B) which the control unit (i.e. unit of 400) is configured to send ZVS pulses (i.e. pulse of ZVS/SR_ZVS) or turn on requests to the primary side, wherein the parameters of the ZVS pulses define a current threshold (i.e. current of the load) at which the primary side switch (i.e. QP) must turn off (i.e. ¶ 39-53).
Regarding claim 30: (i.e. figures 4-6 and 7A-7B) method uses an indirect pulse detection technique (i.e. by 20), and wherein the primary side switch (i.e. QP) is turned on after the ZVS pulse (i.e. pulse of ZVS/SR_ZVS) is detected (i.e. ¶ 39-53).
Regarding claim 32: (i.e. figures 4-6 and 7A-7B) which the indirect pulse detection technique (i.e. by 20) senses a primary switch drain voltage (i.e. voltage of QP) in order to detect a deep valley (i.e. ¶ 39-53).
Regarding claim 34: (i.e. figures 4-6 and 7A-7B) wherein the indirect pulse detection technique senses a dv/dt slope (i.e. figure 3: signals VM or VTR) of the primary switch (i.e. QP) drain voltage (i.e. ¶ 39-53).
Regarding claim 35: (i.e. figures 4-6 and 7A-7B) which the primary side switch (i.e. QP) on-time is calculated from the frequency of the ZVS pulse (i.e. pulse of ZVS/SR_ZVS) (i.e. ¶ 39-53).
Regarding claim 37: the method steps will be met during the normal operation of the apparatus described above. (Examiner notes: For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner wherein the invention was made.
6. Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20190149032) in view of Jitaru (US 20220140742).
Regarding claim 23: Yang et al. disclose (i.e. figures 4-6 and 7A-7B) a synchronizer unit (i.e. unit of 400) is configured to synchronize the ZVS pulse with an auxiliary side drain voltage valley or a local peak (i.e. peak signal of VM or VTR, see figure 3), but does not specifically disclose the transformer further includes an auxiliary side winding, and an auxiliary side switch is located at the auxiliary side.
Jitaru discloses a power converter (i.e. figure 7) comprising the transformer further includes an auxiliary side winding (i.e. N3), and an auxiliary side switch (i.e. 38) is located at an auxiliary side
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Yang et al.’s invention with the power converter as disclose by Jitaru, because it prevents the reduction of sizes and footprints of such adaptors from being significantly reduced.
7. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20190149032) in view of Hu et al. (US 20210006172).
Regarding claim 24: Yang et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose a secondary side rectifier is configured to generate the rectification signal that is configured to control the secondary side switch.
Hu et al. disclose a power supply (i.e. figure 2) comprising a secondary side rectifier (i.e. 12) is configured to generate the rectification signal (i.e. from 12) that is configured to control the secondary side switch (i.e. Q2).
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Yang et al.’s invention with the power supply as disclose by Hu et al. to provide power supplies that have a wide variety of applications in modern electronics.
8. Claims 38-39 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20190149032).
Regarding claim 38: Yang et al. discloses the claimed invention except for the flyback converter delivers up to 75 Watts of power at the output port. It would have been obvious to one having ordinary skill in the art at the time of the invention was made to the circuit of Yang et al.’s invention to have the flyback converter delivers up to 75 Watts of power at the output port for increasing the efficiency of the power converter. Since, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 39: Yang et al. discloses the claimed invention except for the flyback converter delivers between 100 Watts and 500 Watts of power at the output port. It would have been obvious to one having ordinary skill in the art at the time the invention was made to the circuit of Yang et al.’s invention to have the flyback converter delivers between 100 Watts and 500Watts of power at the output port for increasing the power converter efficiency. Since, it has been held that where the general conditions of a claim are discloses in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
9. Claims 33 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
10. Applicant's arguments filed 8/13/25 have been fully considered but they are not persuasive.
Applicant notes that both of claims 1 and 37 provide for "driving the secondary side switch combining a synchronous rectification signal, the ZVS pulse signal and a control pulse signal". The examiner appears to have identified these three signals as the synchronous rectification signal SR sync, the ZVS/SR-ZVS pulse and the VG signal of Yang.
However, applicant submits that the synchronous rectification signal SR_sync is not applied to the secondary switch to drive it. As explained above, the synchronous rectification signal SR sync is generated by the primary controller 100 and transmitted to the secondary controller 200 to trigger the PZV pulses and consequently the PSR pulses (after the predetermined delay Td).
However, the synchronous rectification signal SR sync does not reach the secondary switch. As a matter of fact, the secondary switch is solely driven by the VG voltage signal. This VG voltage signal can actually be seen as the combination of two contributions (see also figure 3), namely the PSR rectification pulses and the ZVS switching pulses PZV used to discharge the parasitic capacitance.
However, a contribution relating to the control of the power transmitted to the load, i.e. the claimed "control pulse signal", which produces the phase shifting effect, is completely missing in Yang.
Moreover, independent claims 1 and 37 specify that when the control pulse signal is high, the switch conducts current from its drain terminal to its source terminal, reflecting power from the output capacitor to the transformer, and the method includes the step of adjusting a power delivered to the output of the flyback converter by adjusting the duration of the control pulse signal.
Since Yang does not disclose any "control pulse signal", it cannot disclose any one of these two additional limitations either.”
The Examiner disagrees, because Yang’s paragraph [0035] stated that
“In this embodiment, the primary side controller circuit 100 is configured to further generate an SR synchronous signal SR_sync. The pulse transformer 20 couples the SR synchronous signal SR_sync from the primary side controller circuit 100 to the secondary side controller circuit 200 to generate the SR control signal VG. Also referring to FIG. 3, more specifically, the SR control signal VG is triggered to generate the SR-ZVS pulse PZV according to the SR synchronous signal SR_sync, and the synchronous rectifier transistor QSR is turned ON for a predetermined ZVS time period T_ZVS by the SR-ZVS pulse PZV (e.g. t1-t2 as shown in FIG. 3). When the synchronous rectifier transistor QSR is turned OFF at the end of the SR-ZVS pulse PZV (e.g. t2), the power transistor QP is turned ON (e.g. t3-t4). As mentioned earlier, during the predetermined ZVS time period T_ZVS (corresponding to the SR-ZVS pulse PZV), the parasitic capacitor Cp of the power transistor QP is discharged substantially to 0V, so the power transistor QP can achieve zero voltage switching when it is turned ON (e.g. t3-t4).”
According to the above paragraph [0035] of Yang’s reference, the SR_sync signal is transfer to controller circuit 200 via transformer 20 to generate the SR control signal VG. Together with the signals SR_sync, pulse of ZVS/SR_ZVS, and signal VG. The controller 200 driving the second side switch QSR. Therefore, Yang disclsoes “the method further includes a step of driving the secondary side switch (i.e. QSR) combining a synchronous rectification signal (i.e. SR_sync), the ZVS pulse signal (i.e. pulse of ZVS/SR_ZVS) and a control pulse signal (i.e. signal VG)”
Conclusion
11. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nguyen Tran/Primary Examiner, Art Unit 2838