Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-18) in the reply filed on 03/30/2026 is acknowledged.
Claims 19-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 03/30/2026.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/31/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is failing to particularly point out and distinctly define the metes and bounds of the subject matter because it is unclear what is the preamble of the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. (US 2020/0144309).
As for claim 1, Jeon et al. disclose in Fig. 1 and the related text an array substrate, comprising a display (right) area and a peripheral (left) area on a side of the display area (Fig. 1), wherein the array substrate comprises a base substrate 110, at least one low temperature polycrystalline silicon thin film transistor 120 [0047] on the base substrate 110 and in the peripheral area (Fig. 1), and at least one oxide thin film transistor 131 [0059] on the base substrate and in the display area (Fig. 1);
each of the at least one low temperature polycrystalline silicon thin film transistor 121 comprises a low temperature polycrystalline silicon semiconductor layer 121, a first gate 124, and a first source 122 and a first drain 123, which are sequentially arranged along a direction away from the base substrate 110 (Fig. 1);
each of the at least one oxide thin film transistor 130 comprises an oxide semiconductor layer 131, a second gate 134, and a second source 133 and a second drain 132, which are sequentially arranged along the direction away from the base substrate 110 (Fig. 1); and
the first source 124 and the first drain 123 are each in a different layer from the second gate 134 (Fig. 3).
As for claim 2, Jeon et al. disclose the array substrate according to claim 1, wherein (portions of) the first source 124 and the first drain 123 are each in a same layer as the second drain 132 (Fig. 1).
Claims 1, 3-10, 14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noh et al. (US 2021/0036197).
As for claim 1, Noh et al. disclose in Figs. 1-4 and the related text an array substrate, comprising a display (right) area and a peripheral (left) area on a side of the display area (Fig. 3), wherein the array substrate comprises a base substrate 100, at least one low temperature polycrystalline silicon thin film transistor 200 [0046] on the base substrate 100 and in the peripheral area (Fig. 3), and at least one oxide thin film transistor 300 [0057] on the base substrate and in the display area (Fig. 3);
each of the at least one low temperature polycrystalline silicon thin film transistor comprises a low temperature polycrystalline silicon semiconductor layer 210 [0046], a first gate 230, and a first source 250 and a first drain 260, which are sequentially arranged along a direction away from the base substrate (Fig. 3);
each of the at least one oxide thin film transistor 310 comprises an oxide semiconductor layer [0057], a second gate 330, and a second source 350 and a second drain 360, which are sequentially arranged along the direction away from the base substrate (Fig. 3); and
the first source 250 and the first drain 260 are each in a different layer from the second gate 330 (Fig. 3).
As for claim 3, Noh et al. disclose the array substrate according to claim 1, wherein the second source 350 and (a portion of) the second drain 360 are in different layers, respectively.
As for claim 4, Noh et al. disclose the array substrate according to claim 3, wherein the second source 350 is on a side of the second drain 360 away from the base substrate 100 (Fig. 3).
As for claim 5, Noh et al. disclose the array substrate according to claim 1, further comprising a pixel electrode, wherein the pixel electrode 510 is on a side of the second source 350 away from the base substrate 100, and is electrically connected to the second source 360 (Fig. 3).
As for claim 6, Noh et al. disclose the array substrate according to claim 5, further comprising a common electrode 530/(a portion of 530 surround the lower middle portion of 530) with a plurality of slits (Fig. 3-4), wherein the common electrode 250 is on a side of the pixel electrode 510 away from the base substrate 100 (Fig. 3).
As for claim 7, Noh et al. disclose the array substrate according to claim 6, wherein an orthographic projection of the common electrode 530 on the base substrate 100 at least partially overlaps with an orthographic projection of the pixel electrode 510 on the base substrate 100 (Fig. 3).
As for claim 8, Noh et al. disclose the array substrate according to claim 6, further comprising a metal layer (a lower middle portion of 530) on a side of the common electrode (a portion of 530 surround the lower middle portion of 530) close to the base substrate 100, wherein an orthographic projection of the metal layer on the base substrate falls on an edge of an orthographic projection of the pixel electrode 510 on the base substrate (Fig. 3).
As for claim 9, Noh et al. disclose the array substrate according to claim 8, wherein the metal layer (a lower middle portion of 530) is electrically connected to the common electrode (a portion of 530 surround the lower middle portion of 530) (Fig. 3).
As for claim 10, Noh et al. disclose the array substrate according to claim 9, wherein the metal layer (a lower middle portion of 530) is embedded in the common electrode (a portion of 530 surround the lower middle portion of 530) (Fig. 3).
As for claim 14, Noh et al. disclose the array substrate according to claim 1, wherein the oxide thin film transistor 300 further comprises a light shielding layer 450 on a side of the oxide semiconductor layer 310 close to the base substrate 100 (Fig. 3); and an orthographic projection of the light shielding layer 450 on the base substrate covers an orthographic projection of a channel of the oxide semiconductor layer 310 on the base substrate 100 (Fig. 3).
As for claim 16, Noh et al. disclose the display apparatus, comprising the array substrate according to claim 1 ([0007]-[0008]).
Claims 1, 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Watakabe et al. (US 2018/0122835).
As for claim 1, Watakabe et al. disclose in Figs. 1-6 and the related text an array substrate, comprising a display (right) area and a peripheral (left) area on a side of the display area (Fig. 6), wherein the array substrate comprises a base substrate 100, at least one low temperature polycrystalline silicon thin film transistor (left transistor, [0043]) on the base substrate 100 and in the peripheral area (Fig. 6), and at least one oxide thin film transistor (right transistor [0043]) on the base substrate and in the display area (Fig. 6);
each of the at least one low temperature polycrystalline silicon thin film transistor comprises a low temperature polycrystalline silicon semiconductor layer 102 [0045]-[0046], a first gate 104, and a first source 115 and a first drain 115, which are sequentially arranged along a direction away from the base substrate 100 (Fig. 6);
each of the at least one oxide thin film transistor comprises an oxide semiconductor layer 107 [0049], a second gate 111, and a second source 116 and a second drain 116, which are sequentially arranged along the direction away from the base substrate 100 (Fig. 6); and
the first source 115 and the first drain 115 are each in a different layer from the second gate 111 (Fig. 6).
As for claim 14, Watakabe et al. disclose the array substrate according to claim 1, wherein the oxide thin film transistor further comprises a light shielding layer 105 on a side of the oxide semiconductor layer 107 close to the base substrate 100 (Fig. 6); and an orthographic projection of the light shielding layer 105 on the base substrate covers an orthographic projection of a channel of the oxide semiconductor layer 107 on the base substrate 100 (Fig. 6).
As for claim 15, Watakabe et al. disclose the array substrate according to claim 14, wherein the light shielding layer 105 is in a same layer as the first gate 104 (Fig. 6, [0048]).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. in view of Jeon et al.
As for claim 11, Noh et al. disclose the array substrate according to claim 6, further comprising a groove (Fig. 3) at a connection position on the pixel electrode 510 and the second source 530 (Fig. 3).
Noh et al. do not disclose a connection position between the pixel electrode and the second source, and a spacer, wherein the spacer is embedded in the groove.
Jeon et al. disclose in Fig. 1 and the related text a connection position between the pixel electrode 170 and the second source 160, and a spacer 220a, wherein the spacer 220a is embedded in the groove (Fig. 1).
Noh et al. and Jeon are analogous art because they both are directed display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Noh et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Noh et al. to include the limitations as taught by Jeon et al., in order to suppress moisture permeation (Jeon et al., [0085]).
Claims 12-13 is rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. in view of Feng et al. (US 2023/0162686).
As for claim 12, Noh et al. disclose the array substrate according to claim 1, except a first/second gate contact electrode and a first/second gate transfer electrode electrically connected to each other, wherein the first/second gate contact electrode is in a same layer as the first/second gate; and the first/second gate transfer electrode is in a same layer as the first/second source and the first/second drain.
Feng et al. teach in Fig. 5 and the related text a first/second gate contact electrode (right 106) and a first/second gate transfer electrode 108 electrically connected to each other, wherein the first/second gate contact electrode (right 106) is in a same layer as the first/second gate (left 106); and the first/second gate transfer electrode 108 is in a same layer as the first/second source and the first/second drain 108.
Noh et al. and Feng et al. are analogous art because they both are directed display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Noh et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Noh et al. to include the limitations as taught by Feng et al., in order to provide high operation performance and reliability of the device.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Noh et al. in view of Ke (US 2020/0312829).
As for claims 17-18, Noh et al. disclose the display apparatus according to claim 16, except the display apparatus is a virtual reality display apparatus or an augmented reality display apparatus, wherein the virtual reality display apparatus or the augmented reality display apparatus has a pixel resolution greater than or equal to 1500 PPI.
Ke et al. teach in [0154] an apparatus is a virtual reality display apparatus or an augmented reality display apparatus, wherein the virtual reality display apparatus or the augmented reality display apparatus has a pixel resolution.
Noh et al. and Ke are analogous art because they both are directed display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Noh et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Noh et al. to include the limitations as taught by Ke, in order to provide applications for the display apparatus (Ke [0003]).
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the virtual reality display apparatus or the augmented reality display apparatus has a pixel resolution greater than or equal to 1500 PPI, in order to optimize the performance of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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