Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 failing to particularly point out and distinctly define the metes and bounds of the subject matter because it is unclear what is the preamble of the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ozeki (US 2022/0328532).
As for claim 1, Ozeki discloses in Figs. 1-7 and the related an array substrate, comprising a display (right side) area and a peripheral (left side) area on a side of the display area (FIG. 1), wherein the array substrate comprises a base substrate SUB, at least one low temperature polycrystalline silicon thin film transistor Tr2-1/Tr2-2 [0045] on the base substrate and in the peripheral area (FIG. 1, [0025]), and at least one oxide thin film transistor Tr1 on the base substrate and in the display area (FIG. 1, [0026]);
wherein the at least one low temperature polysilicon thin film transistor Tr2-1/Tr2-2 is in a gate driving circuit, and the at least one oxide thin film transistor Tr1 is in a pixel driving circuit (FIG. 1);
wherein each of the at least one low temperature polycrystalline silicon thin film transistor comprises a low temperature polycrystalline silicon semiconductor layer S, a first gate GL2, and a first source W1/W2 and a first drain W1/W2, which are sequentially arranged along a direction away from the base substrate (FIG. 1);
each of the at least one oxide thin film transistor Tr1 comprises an oxide semiconductor layer OS, a second gate GL1, and a second source ZCON and a second drain W1, which are sequentially arranged along the direction away from the base substrate (FIG. 1); and
the first source and the first drain are each in a different layer from the second gate GL1 (FIG. 1),
wherein the array substrate further comprises a pixel electrode PTCO, wherein the pixel electrode PTCO is on a side of the second source away from the base substrate (FIG. 1), and is electrically connected to the second source (FIG. 1),
wherein the array substrate further comprises a common electrode CTCO with a plurality of slits (FIG. 1), wherein the common electrode CTCO is on a side of the pixel electrode away from the base substrate (FIG. 1), wherein the array substrate further comprises a groove at a connection position between the pixel electrode PTCO and the second source ZTCO, and a spacer PCON; wherein the spacer is embedded in the groove (FIG. 1).
As for claim 2, Ozeki discloses the array substrate according to claim 1, wherein the first source and the first drain W1/W2 are each in a same layer as the second drain W1.
As for claim 3, Ozeki discloses the array substrate according to claim 1, wherein the second source ZTCO and the second drain W1 are in different layers, respectively (FIG. 1).
As for claim 4, Ozeki discloses the array substrate according to claim 3, wherein the second source ZTCO is on a side of the second drain W1 away from the base substrate (FIG. 1).
As for claim 5, Ozeki discloses the array substrate according to claim 6 claim 1, wherein an orthographic projection of the common electrode CTCO on the base substrate at least partially overlaps with an orthographic projection of the pixel electrode PTCO on the base substrate (FIG. 1).
As for claim 7, Ozeki discloses the array substrate according to claim 6, wherein an orthographic projection of the common electrode CTCO on the base substrate at least partially overlaps with an orthographic projection of the pixel electrode PTCO on the base substrate (Fig. 1).
As for claim 8, Ozeki discloses the array substrate according to claim 6 claim 1, further comprising a metal layer CMTL on a side of the common electrode close to the base substrate, wherein an orthographic projection of the metal layer on the base substrate falls on an edge of an orthographic projection of the pixel electrode on the base substrate (FIG 1).
As for claim 9, Ozeki discloses the array substrate according to claim 8, wherein the metal layer CMTL is electrically connected to the common electrode (FIG. 1).
As for claim 10, Ozeki discloses the array substrate according to claim 9, wherein the metal layer CMTL is embedded in the common electrode (FIG. 1).
As for claim 12, Ozeki discloses the array substrate according to claim 1, further comprising a first gate contact electrode GL2 and a first gate transfer electrode W1 electrically connected to each other, wherein the first gate contact electrode (right GL2) is in a same layer as the first gate (left GL2); and the first gate transfer electrode (right W1) is in a same layer as the first source and the first drain (left W1).
As for claim 13, Ozeki discloses the array substrate according to claim 1, further comprising a second gate contact electrode GL1 and a second gate transfer electrode W2 (above GL2) electrically connected to each other, wherein the second gate contact electrode is in a same layer as the second gate (FIG. 1); and the second gate transfer electrode GL1 is in a same layer as the second drain W1 (FIG. 1).
As for claim 14, Ozeki discloses the array substrate according to claim 1, wherein the oxide thin film transistor further comprises a light shielding layer LS on a (lower) side of the oxide semiconductor layer close to the base substrate (FIG. 1); and an orthographic projection of the light shielding layer LS on the base substrate covers an orthographic projection of a channel OS1 of the oxide semiconductor layer on the base substrate (Fig. 1).
As for claim 15, Ozeki discloses the array substrate according to claim 14, wherein the light shielding layer LS is in a same layer as the first gate GL2 (FIG. 1).
As for claim 16, Ozeki discloses a display apparatus, comprising the array substrate according to claim 1 (see Summary).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Ozeki in view of Ke (US 2020/0312829, as recited in previous office action).
As for claims 17-18, Ozeki disclosed the display apparatus according to claim 16, except the display apparatus is a virtual reality display apparatus or an augmented reality display apparatus, wherein the virtual reality display apparatus or the augmented reality display apparatus has a pixel resolution greater than or equal to 1500 PPI.
Ke et al. teach in [0154] an apparatus is a virtual reality display apparatus or an augmented reality display apparatus, wherein the virtual reality display apparatus or the augmented reality display apparatus has a pixel resolution.
Ozeki and Ke are analogous art because they both are directed display devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Ozeki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Ozeki to include the limitations as taught by Ke, in order to provide applications for the display apparatus (Ke [0003]).
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the virtual reality display apparatus or the augmented reality display apparatus has a pixel resolution greater than or equal to 1500 PPI, in order to optimize the performance of the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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