DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Otsuka (US 2013/0092948), Treu et al. (“Treu” US 2011/0227095), and Zhou et al. (“Zhou” US 2018/0040593).
Regarding claim 1, Otsuka discloses:
A power semiconductor module (Figure 11) comprising:
a semiconductor chip (10) configured to supply a power source, and including a voltage- driven switching element (para. [0047] discloses that semiconductor chip 10 is a power transistor, which is a well-known switching element in the art), and a gate electrode (gate pad electrode GP, Figure 11) provided on a main surface of the semiconductor chip (10, on the lower surface of the chip 10, see Figure 11);
a heat dissipation sheet (100a) disposed opposite the main surface of the semiconductor chip (10, the heat dissipation sheet 100a is disposed opposite the lower surface of the semiconductor chip 10 in relation to the “mounting substrate” 70), and configured to dissipate heat of the semiconductor chip (10, see para. [0087] which discloses the metallic materials used for the heat dissipation sheet 100a, which is bonded to the “heat spreader” 100, thus would also be configured to dissipate heat from the semiconductor chip to the external environment);
a[n insulating] substrate (100) disposed between the semiconductor chip (10) and the heat dissipation sheet (100a, see Figure 11), and including gate wiring (12) formed on a surface (upper surface of 8) facing the main surface of the semiconductor chip (10, see Figure 11, gate wiring 12 is formed on the top surface of 8 which faces the lower surface of the chip 10), to which a first external terminal (181) is connected (see Figure 11);
an interposer (70) formed from a sheet-like base material (insulating material, see para. [0072]) and disposed between the semiconductor chip (10) and the [insulating] substrate (100, see Figure 11).
Otsuka does not explicitly disclose a resin housing that seals the semiconductor chip, the insulating substrate, and the interposer, wherein the interposer includes a gate resistor interposed between the gate electrode of the semiconductor chip and the gate wiring of the insulating substrate, electrically connecting them to each other, and an end of the first external terminal protrudes from the resin housing.
However, Treu discloses in Figure 4 a gate resistor (445) in the interposer (wiring area above active area of the device, see para. [0029]) and interposed between the gate electrode (481a/b) of the semiconductor chip (410) and the gate wiring (gate terminal 431, see Figure 4, see also para. [0039] which discloses the gate electrode/contacts 481a/b are electrically coupled to the gate wiring/terminal 431 via the gate resistor 445, see also para. [0029] which discloses that the gate resistor may also be provided within a wiring area, i.e. a sheet like base material of the interposer, above an active area of the device), electrically connecting them to each other (see para. [0039]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Treu into the teachings of Otsuka in the manner above for the purpose of reducing generation of oscillations by providing a gate resistor (Treu, para. [0039]).
Zhou discloses a resin housing (240, see Figure 4g) that seals the semiconductor chip (104b), the insulating substrate (202), and the interposer (150, see Figure 4g), wherein an end of the first external terminal (220) protrudes from the resin housing (240, see Figure 4g).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Zhou into the teachings of Otsuka in the manner above for the purpose of protecting the semiconductor device from external elements (Zhou, para. [0035]) and to achieve electrical connection to components within the insulating resin via a protruding terminal (Zhou, para. [0033]).
Further, Otsuka does not explicitly disclose that the substrate 100 is an insulating substrate.
However, Zhou discloses an insulating substrate (202).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Zhou into the teachings of Otsuka to include an insulating substrate as taught by Zhou for the purpose of aiding in heat dissipation by using a thermally conductive but electrically insulating material for the substrate (see Zhou, para. [0030]). Further, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Regarding claim 2, Treu discloses:
The power semiconductor module according to claim 1, wherein
the gate resistor (445) is a resistance region (para. [0029]) of the sheet-like base material (wiring area above active area of device), and the resistance region is through the sheet-like base material in a thickness direction (because the gate resistor would be within the sheet like base material outside of the device, it would extend through a thickness thereof), and
on a first main surface of the sheet-like base material, the gate resistor (445) is connected to the gate electrode (481c), and on a second main surface of the sheet-like base material (wiring material above active area of device), the gate wiring is connected to the gate resistor (since the gate resistor is between the gate electrode and external gate wiring, the gate resistor would be between two surfaces of the sheet like base material, i.e. the wiring area above active surface of the device, see para. [0029]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Treu into the teachings of Otsuka in the manner above for the purpose of reducing generation of oscillations by providing a gate resistor (Treu, para. [0039]).
Regarding claim 3, Otsuka discloses, in the embodiment of Figure 19:
The power semiconductor module according to claim 2, wherein
the sheet-like base material (7) is a semiconductor substrate (silicon wafer, see para. [0124]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Otsuka’s embodiment of Figure 19 into the embodiment of Figure 11 to include a semiconductor substrate for the purpose of surface flatness for bonding (Otsuka, para. [0124]).
Treu disclose the gate resistor (445) is an impurity diffusion region in the semiconductor substrate (470, see Figure 4, para. [0037]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Treu into the teachings of Otsuka in the manner above for the purpose of tuning the resistance value of the gate resistor (Treu, para. [0037]).
Regarding claim 4, Otsuka discloses:
The power semiconductor module according to claim 1, wherein
on the main surface of the semiconductor chip (10, lower surface) is at least one controlled electrode (SP),
on the insulating substrate (100) is power supply wiring (6) connected to a second external terminal (19, see Figure 11),
the interposer (8) includes a wiring-coupling unit (16a) that connects the controlled electrode (SP) with the power supply wiring (6, see Figure 11), and
Otsuka and Treu do not explicitly disclose that the gate resistor has a resistance value higher than a resistance value of the wiring- coupling unit.
However, as evidenced by Treu (see para. [0037]), one having ordinary skill in the art would be motivated to optimize resistance values and tune resistance values in accordance with desired current flow and threshold voltage of the device.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Otsuka, Treu, and Zhou as applied to claims 1 and 4 above, and further in view of Chang et al. (“Chang” US 2020/0020635).
Regarding claim 5, Otsuka discloses, in the embodiment of Figure 19:
The power semiconductor module according to claim 4, wherein the sheet-like base material (7) is a semiconductor substrate (silicon wafer, see para. [0124]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Otsuka’s embodiment of Figure 19 into the embodiment of Figure 11 to include a semiconductor substrate for the purpose of surface flatness for bonding (Otsuka, para. [0124]). Further, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Otsuka does not explicitly disclose that the gate resistor and the wiring-coupling unit are each an impurity diffusion region in the semiconductor substrate and through the sheet-like base material in a thickness direction.
Treu discloses that the gate resistor (445) is an impurity diffusion region in the semiconductor substrate (470) and through the sheet-like base material (470, or external wiring in which the gate resistor is embedded, see para. [0029]) in a thickness direction.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Treu into the teachings of Otsuka in the manner above for the purpose of tuning the resistance value of the gate resistor (Treu, para. [0037]).
Chang discloses that a TSV (i.e. a wiring coupling unit) is an impurity diffusion region (doped polysilicon TSV, para. [0023]) in the semiconductor substrate and through the sheet-like base material (217).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Chang into the teachings of Otsuka to include a doped material, impurity diffusion region, for the wiring-coupling unit without any change in the function of the wiring coupling unit, resulting in the predictable result of providing electrical connection between parts of the device. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 6, Otsuka discloses:
The power semiconductor module according to claim 1, wherein the semiconductor chip (10) includes a silicon carbide substrate (para. [0107], [0109]), and
The sheet-like base material (7, embodiment of Figure 19) is a silicon substrate (para. [0124]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Otsuka’s embodiment of Figure 19 into the embodiment of Figure 11 to include a silicon substrate for the purpose of surface flatness for bonding (Otsuka, para. [0124]). Further, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Response to Arguments
Applicant’s arguments with respect to the wiring board (now amended to the insulating substrate) of claim 1 have been considered but are moot because the new ground of rejection does not rely on any interpretation of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s argument that Otsuka does not teach or suggest any member corresponding to the claimed interposer is not persuasive. Otsuka’s “mounting substrate” 70 is analogous to the claimed interposer and reads on the claim limitation “an interposer formed from a sheet-like base material and disposed between the semiconductor chip and the [insulating] substrate”, see above. The other limitations regarding the interposer have been incorporated by Treu, which is further discussed below.
Applicant’s argument that Treu fails to teach or suggest and member corresponding to “the interposer” is not persuasive. As stated above and in the Non-Final Office action, Treu discloses a wiring area above an active surface of the semiconductor device that includes the gate resistor (see para. [0029]), which clearly corresponds to some sort of interposer, which has the same structure of material including wiring or conductive traces therein, that corresponds to the claimed interposer. Treu also discloses in para. [0039] the gate electrode/contacts 481a/b are electrically coupled to the gate wiring/terminal 431 via the gate resistor 445, thus the gate resistor is interposed between the gate electrode and the gate wiring. The combination of Otsuka and Treu thus teach the limitation “a gate resistor interposed between the gate electrode of the semiconductor chip and the gate wiring of the insulating substrate, electrically connecting them to each other”, see above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899