DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 13-19 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation “not connected directly,” is unclear as to the proper interpretation and scope of the limitation. Specifically, the limitation attempts to preclude a connection which is “direct,” however the complete scope of what connections would be precluded is not defined, and therefore the scope of the claim is not defined.
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 13-14, and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Long et al. (CN104253159, using US 20160293771 as an English language equivalent; herein “Long”).
Regarding claim 1, Long discloses in Figs. 4-5H and related text a display substrate, comprising a base substrate and a driving circuit layer arranged on the base substrate, wherein:
the driving circuit layer comprises at least one pixel circuit, the pixel circuit comprises at least one first transistor (e.g. transistor of Fig. 5F);
the first transistor at least comprises: a first active layer (4, see [0123]) and a first source-drain electrode (10/12c, see [0123]) and a second source-drain electrode (12b, see [0123]) arranged on the base substrate, wherein the first source-drain electrode comprises a first sub-electrode (10) and a second sub-electrode (12c), and the second sub-electrode is located at a side of the first sub-electrode away from the base substrate; and
the driving circuit layer further comprises at least one first via hole (e.g. via hole in 11 filled by 12c), the first via hole is filled by the second sub-electrode, an orthographic projection of the first via hole is overlapped with an orthographic projection of the first sub-electrode and an orthographic projection of the first active layer on the base substrate respectively, the first via hole exposes at least a portion of the first sub-electrode (top portion of 10) and at least a portion of the first active layer respectively (top portion of 4), the second sub-electrode is electrically connected with the exposed first sub-electrode through the first via hole, and the second sub-electrode is electrically connected with the exposed first active layer through the first via hole; and
the first source-drain electrode (10/12c) is a drain electrode (see [0123]) of the first transistor, the second source-drain electrode is a source electrode of the first transistor (see [0123), the second sub-electrode (12c) the first source-drain electrode is arranged at a same layer as the second source-drain electrode (12b), and the first sub-electrode (10) of the first source-drain electrode is arranged at a different layer as the second source-drain electrode (12b);
the first sub-electrode comprises a first part of the first sub-electrode and a second part of the first sub-electrode which are separated from each other (note that one can arbitrarily choose portions of 10 which read on the claimed limitations; e.g. a part at the top side of 10 as oriented in Fig. 5H and a part at the bottom of 10 as oriented in Fig. 5H; separated from each other by a part at the middle), the first part of the first sub-electrode and the second part of the first sub-electrode are located respectively at two sides of the first via hole (e.g. top and bottom sides of via hole as oriented in Fig. 5H) and are not connected directly (e.g. not in direct contact, separated by the middle part of 10), an orthographic projection of at least a portion of the first via hole on the base substrate is overlapped with an orthographic projection of the first part of the first sub-electrode and an orthographic projection of the second part of the first sub-electrode on the base substrate respectively, the first via hole exposes at least a portion of the first part of the first sub-electrode and at least a portion of the second part of the first sub-electrode respectively, and the second sub-electrode is electrically connected with the exposed first part of the first sub-electrode and the exposed second part of the first sub-electrode through the first via hole respectively (see Fig. 5F and 5H).
Regarding claim 13, Long further discloses wherein the driving circuit layer further comprises a gate insulating layer (e.g. bottom layer of 6, see [0088]), a first interlayer dielectric layer (e.g. top layer of 6, see [0088]) and another interlayer dielectric layer (e.g. 11, see [0123])sequentially arranged on the base substrate, the gate insulating layer and the first interlayer dielectric layer are located between the first active layer (4) and the first sub-electrode (10), the other interlayer dielectric layer (11) is located on a side of the first sub-electrode away from the base substrate (i.e. top side of 10), and the first via hole passes through the other interlayer dielectric layer, the first interlayer dielectric layer and the gate insulating layer sequentially from a surface of the other interlayer dielectric layer away from the base substrate, and extending to a surface of the first active layer on a side away from the substrate (see Fig. 5C).
Regarding claim 14, Long further discloses wherein the second source-drain electrode (12b) is located on a side of the first active layer away from the base substrate (i.e. top side of 4), the driving circuit layer further comprises a second via hole (e.g. via hope through 11 filled by 12b), and the second source-drain electrode is electrically connected with the first active layer through the second via hole.
Regarding claim 18, Long further discloses wherein the pixel circuit comprises at least one second transistor (e.g. second transistor shown in Fig. 5H); the second transistor comprises a second active layer (4 of second transistor), a gate (7 of second transistor), a third source-drain electrode (12b of second transistor) and a fourth source-drain electrode (12c of second transistor) arranged on the base substrate, an orthographic projection of the second active layer is overlapped with an orthographic projection of the third gate on the base substrate, the third source-drain electrode and the fourth source-drain electrode are electrically connected with the second active layer respectively, and a material of the second active layer comprises low-temperature polysilicon (see [0144] at least).
Regarding claim 19, Long discloses in Figs. 4-5H and related text a display apparatus, comprising the display substrate according to claim 1 (see rejection of claim 1 above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Long as applied to claim 1 above and in view of Park et al. (US 20210328102; herein “Park).
Regarding claim 16, Long further discloses wherein the first transistor further comprises a second gate (7), the second gate is located on a side of the first active layer (4) away from the base substrate, and an orthographic projection of the second gate and the orthographic projection of the first active layer are overlapped on the base substrate.
Long does not explicitly disclose wherein the first transistor further comprises a first gate, the first gate is located on a side of the first active layer close to the base substrate, and an orthographic projection of the first gate, an orthographic projection of the second gate and the orthographic projection of the first active layer are overlapped on the base substrate.
In the same field of endeavor, Park teaches in Fig. 3 and related text a display device wherein the first transistor further comprises a first gate (112, see [0070]) and a second gate (172, see [0070]), the first gate is located on a side of the first active layer (162, see [0063]) close to the base substrate, the second gate is located on a side of the first active layer away from the base substrate, and an orthographic projection of the first gate, an orthographic projection of the second gate and the orthographic projection of the first active layer are overlapped on the base substrate (see Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Long by having the first transistor further comprises a first gate and a second gate, the first gate is located on a side of the first active layer close to the base substrate, the second gate is located on a side of the first active layer away from the base substrate, and an orthographic projection of the first gate, an orthographic projection of the second gate and the orthographic projection of the first active layer are overlapped on the base substrate, as taught by Park, in order to achieve a high electron mobility (see Park [0070]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Long as applied to claim 1 above and in view of Yuan (US 20210376029; herein “Yuan”).
Regarding claim 17, Long does not explicitly disclose wherein a material of the first active layer comprises one of an indium gallium zinc oxide material and an indium tin zinc oxide material.
In the same field of endeavor, Yuan teaches a display device wherein a material of the first active layer comprises one of an indium gallium zinc oxide material and an indium tin zinc oxide material (see [0075]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Long by having a material of the first active layer comprises one of an indium gallium zinc oxide material and an indium tin zinc oxide material in order to have a transistor with good transparency and uniformity (see Yuan [0075]).
Response to Arguments
Applicant's arguments filed 12/25/2026 have been fully considered but they are not persuasive.
Applicant argues (page 13-14) that Long does not teach or suggest the claimed invention because the drain electrode does not have “two separate portions” which are “at two side of a via hole” and are “not connected directly.”
In response, the examiner disagrees. Specifically, the Examiner notes that in accordance with MPEP 2111, USPTO personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997). Therefore the limitations “part” and “not connected directly” have been given its broadest reasonable interpretation. According to American Heritage® Dictionary, “part” is defined as “a portion, division, piece, or segment of a whole” and "directly" is defined as "without anyone or anything intervening." Therefore, there is a first “part” of 10 at the top side as oriented in Fig. 5H and a second a “part” of 10 at the bottom side as oriented in Fig. 5H. The two parts can be chosen such that they are separated by a middle part and they are connected with the middle part intervening, i.e. not directly connected. Accordingly, Long teaches the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
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/LAUREN R BELL/Primary Examiner, Art Unit 2896 2/5/2026