DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/15/2026 has been entered.
Response to Amendment
Acknowledgment is made of the amendment filed 05/15/2026, in which: claim 1 is amended; claim 8 is cancelled; and the rejection of the claims are traversed. Claims 1, 3, 5-7, 9-15, 17, and 19-22 are currently pending an Office action on the merits as follows.
Claim Objections
Claim 1 objected to because of the following informalities: the phrase "the second electrode of the polysilicon transistor" should read ". Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim s 6 and 20 recites the limitation "the active layer of the polysilicon transistor" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3, 6, 9-10, 12, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US Publication 20210005693) in view of Park et al. (US Publication 20200258970).
Regarding independent claim 1, Cho teaches a display base plate (fig. 1, 100), comprising a substrate (100) and a plurality of sub-pixels (paragraph 0180) arranged in an array at one side of the substrate;
each of the plurality of sub-pixels comprises a storage capacitor (140), a polysilicon transistor (320) and at least one oxide transistor (330);
wherein the storage capacitor comprises a first electrode (142) and a second electrode (141) oppositely arranged, and the first electrode is arranged at a side of the second electrode away from the substrate (fig. 1);
the second electrode being arranged in a same layer as a gate electrode (324) of the polysilicon transistor (fig. 1, 141 and 324 both in 112), the at least one oxide transistor being arranged on a side of the first electrode away from the substrate (fig. 1), and the first electrode at least partially overlapping with an active layer (331) of the at least one oxide transistor in a direction perpendicular to the substrate (fig. 1); and
[the first electrode] further serving as a bottom gate of an overlapping oxide transistor (fig. 1), wherein an oxide transistor at least partially overlapping with the first electrode in the direction perpendicular to the substrate is the overlapping oxide transistor (fig. 1);
wherein an orthographic projection of the active layer of the at least one of the oxide transistors on the substrate is located within an orthographic projection of the first electrode on the substrate (fig. 1);
wherein the display base plate further comprises a connection electrode (160), a first flat layer (117) and a second flat layer (118), the sub-pixel further comprises an anode (170), wherein the anode is electrically connected to the connection electrode via a through hole (see figure below) throughout the second flat layer, and the connection electrode is electrically connected to the second electrode (323) of the polysilicon
PNG
media_image1.png
450
724
media_image1.png
Greyscale
transistor via a through hole (see figure below) throughout the first flat layer; and
along at least one direction parallel to the substrate, and the length of the second electrode is larger than a length of the active layer (fig. 1, 141 is longer than 331).
Cho does not teach the first electrode being configured to access a power signal, wherein the display base plate further comprises a power line, and the first electrode is electrically connected to the power line via a third through hole; an orthographic projection of the third through hole on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the third through hole on the substrate is located outside the orthographic projection of the active layer of the at least one of the oxide transistors on the substrate; a length of the first electrode is larger than a length of the second electrode.
Park teaches the first electrode (fig. 5, CE2) being configured to access a power signal (paragraph 0094), wherein the display base plate further comprises a power line (PVL2), and the first electrode is electrically connected to the power line via a third through hole (VH2);
an orthographic projection of the third through hole on the substrate overlaps with the orthographic projection of the first electrode on the substrate (fig. 5), and the orthographic projection of the third through hole on the substrate is located outside the orthographic projection of the active layer of the at least one of the oxide transistors on the substrate (fig. 5, orthographic projection of VH2 does not overlap with orthographic projection of ACT(C1) which corresponds to active layer of at least one of the oxide transistors of Cho);
PNG
media_image2.png
417
784
media_image2.png
Greyscale
a length of the first electrode is larger than a length of the second electrode (see figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate of Cho and the third via hole of Park in order to connect the power voltage line to the storage electrode (Park paragraph 0093).
Regarding dependent claim 3, Cho further teaches the display base plate according to claim 1, wherein an orthographic projection of the second electrode on the substrate is located within the orthographic projection of the first electrode on the substrate (fig. 1, orthographic projection of 141 located within orthographic projection of 142).
Regarding dependent claim 9, Cho further teaches the display base plate according to claim 1, wherein the polysilicon transistor is a P-type transistor and the oxide transistor is an N-type transistor (paragraph 0181).
Regarding dependent claim 10, Cho further teaches the display base plate according to claim 1, wherein the sub-pixel further comprises a single-gate oxide transistor (fig. 1, 310), and an active layer (311) of the single-gate oxide transistor does not overlap with the first electrode in the direction perpendicular to the substrate (paragraph 0055, 311 can include polysilicon but can be easily switched to include an oxide semiconductor per MPEP 2144.07).
Regarding dependent claim 12, Cho further teaches a display panel comprising the display base plate according to claim 1 (paragraph 0040).
Regarding dependent claim 17, Cho further teaches the display panel according to claim 12, wherein an orthographic projection of the second electrode on the substrate is located within the orthographic projection of the first electrode on the substrate (fig. 1, orthographic projection of 141 located within orthographic projection of 142).
Regarding dependent claims 6 and 20, Cho further teaches the display base plate according to claim 1/the display panel according to claim 12, wherein the polysilicon transistor is a top-gate polysilicon transistor (fig. 1), and the active layer (321) of the polysilicon transistor is arranged between the substrate and the gate electrode (324) of the polysilicon transistor.
Claims 5, 7-8, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Park as applied to claim 1 above, and further in view of Cha et al. (US Publication 20200083311).
Regarding dependent claims 5 and 19, Cho in view of Park teaches the display base plate according to claim 1/the display panel according to claim 12.
Cho in view of Park does not teach wherein the power line is arranged in the same layer as a first electrode and a second electrode of the overlapping oxide transistor.
Cha teaches wherein the power line (fig. 3, 301b) is arranged in the same layer as a first electrode (123) and a second electrode (124) of the overlapping oxide transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate of Cho in view of Park and the power line positioning of Cha in order to reduce the non-display area (Cha paragraph 0092).
Regarding dependent claim 7, Cho in view of Park teaches the display base plate according to claim 6.
Cho in view of Park does not teach wherein a first electrode and a second electrode of the polysilicon transistor are arranged in the same layer as a first electrode and a second electrode of the overlapping oxide transistor.
Cha teaches wherein a first electrode (fig. 3 203) and a second electrode (204) of the polysilicon transistor (TFTn) are arranged in the same layer as a first electrode (123) and a second electrode (124) of the overlapping oxide transistor (TFTd).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate of Cho and the arrangement of the first and second electrodes of the transistors of Cha in order that “the source electrode 123 and the drain electrode 124 contacting the semiconductor layer 121 of the transistor TFTd through the contact holes CH1, the source electrode 203 and the drain electrode 204 contacting the semiconductor layer 201 of the transistor TFTn through the contact holes CH3, and the second power line 301b may be formed on the third insulating layer 113” (Cha paragraph 0106).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Park as applied to claim 1 above, and further in view of Cai et al. (CN Publication 110824797/Machine Translation Document of 02/20/2026)
Regarding dependent claim 11, Cho in view of Park teaches the display base plate according to claim 1.
Cho in view of Park does not teach wherein the sub-pixel further comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; and the first transistor and the second transistor are the oxide transistors and the third transistor is the polysilicon transistor; the display base plate further comprises a power line, a light-emitting control signal line, a data signal line, a reset control signal line and an initial signal line; and the sub-pixel further comprises a light-emitting diode; a gate electrode of the first transistor is electrically connected to the reset control signal line, a second electrode of the first transistor is electrically connected to the initial signal line, a first electrode of the first transistor and a first electrode of the second transistor are electrically connected to a first node, a gate electrode of the third transistor and a second electrode of the storage capacitor are electrically connected to the first node; a gate electrode of the second transistor is electrically connected to the reset control signal line, and a second electrode of the second transistor is electrically connected to a third node, a first electrode of the third transistor is electrically connected to a second node, and a second electrode of the third transistor is electrically connected to the third node, a first electrode of the fourth transistor is electrically connected to the second node, the second electrode of the fourth transistor is electrically connected to the data signal line, a gate electrode of the fourth transistor is electrically connected to the reset control signal line, a second electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the power line, and a gate electrode of the fifth transistor is electrically connected to the light-emitting control signal line; and a gate electrode of the sixth transistor is electrically connected to the light-emitting control signal line, a first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to a fourth node, a gate electrode of the seventh transistor is electrically connected to the reset control signal line, a first electrode of the seventh transistor is electrically connected to the fourth node, and a second electrode of the seventh transistor is electrically connected to the initial signal line, an anode of the light-emitting diode is electrically connected to the fourth node, and a cathode of the light-emitting diode is connected to ground; wherein orthographic projections of active layers of the first transistor and the second transistor on the substrate are both located within an orthographic projection of the first electrode on the substrate, and orthographic projections of active layers of other transistors on the substrate do not overlap with the orthographic projection of the first electrode on the substrate.
Cai teaches wherein the sub-pixel further comprises a first transistor (fig. 9, M5), a second transistor (M1), a third transistor (M7), a fourth transistor (M2), a fifth transistor (M3), a sixth transistor (M6) and a seventh transistor (M4); and
the first transistor and the second transistor are the oxide transistors (machine translation, page 9 paragraph 5) and the third transistor is the polysilicon transistor (machine translation, page 9 paragraph 6);
the display base plate further comprises a power line (VDD), a light-emitting control signal line (EM), a data signal line (VData), a reset control signal line (Sn and Sn-1) and an initial signal line (Vinit); and
the sub-pixel further comprises a light-emitting diode (50);
a gate electrode of the first transistor is electrically connected to the reset control signal line (fig. 9, gate electrode of M5 connected to Sn-1), a second electrode of the first transistor is electrically connected to the initial signal line (“second pole of the fifth sub-transistor M5 is connected to the initial voltage signal line Vinit” as stated in Cai), a first electrode of the first transistor and a first electrode of the second transistor are electrically connected to a first node (see figure below, first electrode of M5 and first electrode of M1 connected to first node), a gate electrode of the third transistor and a second electrode of the storage capacitor are electrically connected to the first node (fig. 9, gate of M7 and second electrode of C’ connected to first node;
a gate electrode of the second transistor is electrically connected to the reset control signal line (fig. 9, gate electrode of M1 connected to Sn), and a second electrode of the second transistor is electrically connected to a third node (see figure below, second electrode of M1 connected to third node), a first electrode of the third transistor is electrically connected to a second node (see figure below, first electrode of M7 connected to second node), and a second electrode of the third transistor is electrically connected to the third node (see figure below, second electrode of M7 connected to third node), a first electrode of the fourth transistor is electrically connected to the second node (see figure below, first electrode of M2 connected to second node), the second electrode of the fourth transistor is electrically connected to the data signal line (fig. 9, second electrode of M2 connected to VData), a gate electrode of the fourth transistor is electrically connected to the reset control signal line (fig. 9, gate of M2 connected to reset control signal line Sn), a second electrode of the fifth transistor is electrically connected to the second node (see figure below, second electrode of M3 connected to second node), a first electrode of the fifth transistor is electrically connected to the power line (see figure below, first electrode of M3 connected to VDD), and a gate electrode of the fifth transistor is electrically connected to the light-emitting control signal line (fig. 9, gate of M3 connected to EM); and
PNG
media_image3.png
340
490
media_image3.png
Greyscale
a gate electrode of the sixth transistor is electrically connected to the light-emitting control signal line (fig. 9, gate of M6 connected to EM), a first electrode of the sixth transistor is electrically connected to the third node (see figure below, first electrode of M6 connected to third node), and the second electrode of the sixth transistor is electrically connected to a fourth node (see figure below, second electrode of M6 connected to fourth node), a gate electrode of the seventh transistor is electrically connected to the reset control signal line (fig. 9, gate electrode of M4 connected to reset control signal line Sn-1), a first electrode of the seventh transistor is electrically connected to the fourth node (see figure below, first electrode of M4 connected to fourth node), and a second electrode of the seventh transistor is electrically connected to the initial signal line (fig. 9, second electrode of M4 connected to Vinit), an anode of the light-emitting diode is electrically connected to the fourth node (fig. 9, anode of 50 connected to fourth node), and a cathode of the light-emitting diode is connected to ground (fig. 9, cathode of 50 connected to ground).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate of Cho in view of park and the circuit configuration of Cai to compensate the threshold voltage of the sub-pixel during the light emitting process in order to have uniformity (machine translation, page 10 paragraph 2).
Cai does not explicitly teach wherein orthographic projections of active layers of the first transistor and the second transistor on the substrate are both located within an orthographic projection of the first electrode on the substrate, and orthographic projections of active layers of other transistors on the substrate do not overlap with the orthographic projection of the first electrode on the substrate, however, Cai discloses “the second storage capacitor C′ and the orthographic projection of the low temperature polycrystalline oxide transistor on the substrate 10 at least partially overlap. In some embodiments, the second storage capacitor C′ may also at least partially overlap with the orthographic projection of the low temperature polysilicon transistor on the substrate 10. In still other embodiments, the second storage capacitor C′ and the orthographic projection of the low temperature polycrystalline oxide transistor on the substrate 10 do not overlap, or the orthographic projection of the second storage capacitor C′ and the low temperature polycrystalline silicon transistor on the substrate 10 do not overlap” (machine translation, page 10 paragraph 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the active layers of the transistors such that only the active layers of the first two transistors overlap with the first electrode of the capacitor, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Park as applied to claim 1 above, and further in view of Liu (US Publication 20180114864).
Regarding dependent claims 21 and 22, Cho further teaches the display base plate according to claim 1/the display panel according to claim 12, wherein the display base plate further comprises a second buffer layer (fig. 1, 111).
Cho does not teach and a thickness of the second buffer layer is 3000 A.
Liu teaches and a thickness of the second buffer layer is 3000 A (paragraph 0075, “the thickness of the gate insulating layer 12 may be controlled to be between about 300Å to about 3000Å”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate/panel of Cho in view of Park and the thickness of the second buffer layer of Liu in order to cover the gate electrode (Liu paragraph 0021).
Response to Arguments
Applicant’s arguments with respect to claims 1, 3, 5-7, 9-15, 17, and 19-22 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Applicant’s arguments filed 05/15/2026 have been fully considered but are not persuasive.
Applicant argues on page 10 of the instant Remarks: “It can be clearly seen from FIG. 2 of Cai that 41 of Cai is directly connected to 14b of Cai, however, referring to FIG. 14 and paragraph [0077] of the present application, "the anode 35 may also be electrically connected to a connection electrode 41 via a through hole throughout through the second flat layer 40, and the connection electrode 41 is electrically connected to the second electrode 30 of the polysilicon transistor via a through hole throughout the first flat layer", that is, Cai fails to disclose a connection electrode disposed between 41 of Cai and 14b of Cai. In other words, Cai fails to disclose the above distinguishing features.”
However, Cho discloses the anode (170) is electrically connected to the connection electrode (160) via a through hole throughout the second flat layer (118), and the connection electrode is electrically connected to the second electrode (323) of the polysilicon transistor via a through hole throughout the first flat layer (117).
Applicant also argues on pages 10-11 of the instant Remarks: “According to FIG. 2 of Cai, it can be clearly seen that along at least one direction parallel to the substrate, a length of the active layer 31 is larger than a length of the upper electrode plate 23, and the length of the upper electrode plate 23 is approximately equal to a length of the lower electrode plate 21, however, in claim 1 of the present application, along at least one direction parallel to the substrate, a length of the first electrode 18 is larger than a length of the second electrode 16, and the length of the second electrode 16 is larger than a length of the active layer 20, which is not taught by Cai.”
However, as stated above, Park discloses a length of the first electrode is larger than a length of the second electrode (see second marked figure corresponding to claim 1) while Cho discloses the length of the second electrode is larger than a length of the active layer (fig. 1, 141 is longer than 331). Therefore, claim 1, along with dependent claims 3, 5-12, 17, and 19-22 are not patentable over the cited references.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights