DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 12/26/2025, in which: claims 1, 3, 11, and 17 are amended; claims 2 and 16 are cancelled; claims 13-15 stand withdrawn; and the rejection of the claims are traversed. Claims 1, 3, 5-12, 17 and 19-22 are currently pending an Office action on the merits as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 3, 6, 9-12, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cai et al. (CN Publication 110824797/Machine Translation Document of 02/18/2026) in view of Park et al. (US Publication 20200258970).
Regarding independent claim 1, Cai teaches a display base plate (fig. 8), comprising a substrate (10) and a plurality of sub-pixels (40) arranged in an array at one side of the substrate;
each of the plurality of sub-pixels comprises a storage capacitor (C, C”), a polysilicon transistor (LTPS TFT) and at least one oxide transistor (LTPO TFT);
wherein the storage capacitor comprises a first electrode (23) and a second electrode (21) oppositely arranged, and the first electrode is arranged at a side of the second electrode away from the substrate (fig. 8);
the second electrode being arranged in a same layer as a gate electrode of the polysilicon transistor (fig. 8, 21 and gate electrode 13 of LTPS TFT on same layer), the at least one oxide transistor being arranged on a side of the first electrode away from the substrate (fig. 8, LTPO TFT on top of 23), and the first electrode at least partially overlapping with an active layer (31) of the at least one oxide transistor in a direction perpendicular to the substrate (fig. 8); and
the first electrode being configured to access a power signal (machine translation, page 9 paragraph 2) and further serving as a bottom gate of an overlapping oxide transistor (fig. 2, machine translation, page 7 paragraph 8), wherein an oxide transistor at least partially overlapping with the first electrode in the direction perpendicular to the substrate is the overlapping oxide transistor (machine translation, page 10 paragraph 4);
wherein the display base plate further comprises a power line (fig. 6, VDD);
wherein an orthographic projection of the active layer of the at least one of the oxide transistors on the substrate is located within an orthographic projection of the first electrode on the substrate (fig. 2, orthographic projection of 31 located within orthographic projection of 23);
Cai does not teach and the first electrode is electrically connected to the power line via a third through hole; an orthographic projection of the third through hole on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the third through hole on the substrate is located outside the orthographic projection of the active layer of the at least one of the oxide transistors on the substrate.
Park teaches and the first electrode (fig. 5, CE2) is electrically connected to the power line (PVL2) via a third through hole;
an orthographic projection of the third through hole on the substrate overlaps with the orthographic projection of the first electrode on the substrate (fig. 5), and the orthographic projection of the third through hole on the substrate is located outside the orthographic projection of the active layer of the at least one of the oxide transistors on the substrate (fig. 5, orthographic projection of VH2 does not overlap with orthographic projection of ACT(C1) which corresponds to active layer of at least one of the oxide transistors of Cai).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate of Cai and the third via hole of Park in order to connect the power voltage line to the storage electrode (Park paragraph 0093).
Regarding dependent claim 3, Cai further teaches the display base plate according to claim 1, wherein an orthographic projection of the second electrode on the substrate is located within the orthographic projection of the first electrode on the substrate (fig. 2, orthographic projection of 21 located within orthographic projection of 23).
Regarding dependent claim 9, Cai further teaches the display base plate according to claim 1, wherein the polysilicon transistor is a P-type transistor and the oxide transistor is an N-type transistor (machine translation, page 5 paragraph 7).
Regarding dependent claim 10, Cai further teaches the display base plate according to claim 1, wherein the sub-pixel further comprises a single-gate oxide transistor (fig. 6, X3, see also machine translation, page 7 paragraph 10).
Cai does not explicitly teach and an active layer of the single-gate oxide transistor does not overlap with the first electrode in the direction perpendicular to the substrate, however, Cai discloses the “orthographic projection of the light emitting transistor X3 and the first storage capacitor C on the transparent display panel 1 (substrate 10) may also at least partially overlap” (machine translation, page 7 paragraph 10).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the active layer of the single-gate oxide transistor and the first electrode of the capacitor such that they don’t overlap in the direction perpendicular to the substrate, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claim 11, Cai further teaches the display base plate according to claim 1, wherein the sub-pixel further comprises a first transistor (fig. 9, M5), a second transistor (M1), a third transistor (M7), a fourth transistor (M2), a fifth transistor (M3), a sixth transistor (M6) and a seventh transistor (M4); and
the first transistor and the second transistor are the oxide transistors (machine translation, page 9 paragraph 5) and the third transistor is the polysilicon transistor (machine translation, page 9 paragraph 6);
the display base plate further comprises a power line (VDD), a light-emitting control signal line (EM), a data signal line (VData), a reset control signal line (Sn and Sn-1) and an initial signal line (Vinit); and
the sub-pixel further comprises a light-emitting diode (50);
a gate electrode of the first transistor is electrically connected to the reset control signal line (fig. 9, gate electrode of M5 connected to Sn-1), a second electrode of the first transistor is electrically connected to the initial signal line (“second pole of the fifth sub-transistor M5 is connected to the initial voltage signal line Vinit” as stated in Cai), a first electrode of the first transistor and a first electrode of the second transistor are electrically connected to a first node (see figure below, first electrode of M5 and first electrode of M1 connected to first node), a gate electrode of the third transistor and a second electrode of the storage capacitor are electrically connected to the first node (fig. 9, gate of M7 and second electrode of C’ connected to first node)
a gate electrode of the second transistor is electrically connected to the reset control signal line (fig. 9, gate electrode of M1 connected to Sn), and a second electrode of the second transistor is electrically connected to a third node (see figure below, second electrode of M1 connected to third node), a first electrode of the third transistor is electrically connected to a second node (see figure below, first electrode of M7 connected to second node), and a second electrode of the third transistor is electrically connected to the third node (see figure below, second electrode of M7 connected to third node), a first electrode of the fourth transistor is electrically connected to the second node (see figure below, first electrode of M2 connected to second node), the second electrode of the fourth transistor is electrically connected to the data signal line (fig. 9, second electrode of M2 connected to VData), a gate electrode of the fourth transistor is electrically connected to the reset control signal line (fig. 9, gate of M2 connected to reset control signal line Sn), a second electrode of the fifth transistor is electrically connected to the second node (see figure below, second electrode of M3 connected to second node), a first electrode of the fifth transistor is electrically connected to the power line (see figure below, first electrode of M3 connected to VDD), and a gate electrode of the fifth transistor is electrically connected to the light-emitting control signal line (fig. 9, gate of M3 connected to EM); and
a gate electrode of the sixth transistor is electrically connected to the light-emitting control signal line (fig. 9, gate of M6 connected to EM), a first electrode of the sixth transistor is electrically connected to the third node (see figure below, first electrode of M6 connected to third node), and the second electrode of the sixth transistor is electrically connected to a fourth node (see figure below, second electrode of M6 connected to fourth node), a gate electrode of the seventh transistor is electrically connected to the reset control signal line (fig. 9, gate electrode of M4 connected to reset control signal line Sn-1), a first electrode of the seventh transistor is electrically connected to the fourth node (see figure below, first electrode of M4 connected to fourth node), and a second electrode of the seventh transistor is electrically connected to the initial signal line (fig. 9, second electrode of M4 connected to Vinit), an anode of the light-emitting diode is electrically connected to the fourth node (fig. 9, anode of 50 connected to fourth node), and a cathode of the light-emitting diode is connected to
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ground (fig. 9, cathode of 50 connected to ground).
Cai does not explicitly teach wherein orthographic projections of active layers of the first transistor and the second transistor on the substrate are both located within an orthographic projection of the first electrode on the substrate, and orthographic projections of active layers of other transistors on the substrate do not overlap with the orthographic projection of the first electrode on the substrate, however, Cai discloses “the second storage capacitor C′ and the orthographic projection of the low temperature polycrystalline oxide transistor on the substrate 10 at least partially overlap. In some embodiments, the second storage capacitor C′ may also at least partially overlap with the orthographic projection of the low temperature polysilicon transistor on the substrate 10 . In still other embodiments, the second storage capacitor C′ and the orthographic projection of the low temperature polycrystalline oxide transistor on the substrate 10 do not overlap, or the orthographic projection of the second storage capacitor C′ and the low temperature polycrystalline silicon transistor on the substrate 10 do not overlap” (machine translation, page 10 paragraph 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the active layers of the transistors such that only the active layers of the first two transistors overlap with the first electrode of the capacitor, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claim 12, Cai further teaches a display panel (fig. 7, 4) comprising the display base plate according to claim 1.
Regarding dependent claim 17, Cai further teaches the display panel according to claim 12, wherein an orthographic projection of the second electrode on the substrate is located within the orthographic projection of the first electrode on the substrate (fig. 2, orthographic projection of 21 located within orthographic projection of 23).
Regarding dependent claims 6 and 20, Cai further teaches the display base plate according to claim 1/ the display panel according to claim 12, wherein the polysilicon transistor is a top-gate polysilicon transistor (machine translation, page 6 paragraph 6), and the active layer of the polysilicon transistor is arranged between the substrate and the gate electrode of the polysilicon transistor (fig. 2).
Claims 5, 7-8, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Park as applied to claim 1 above, and further in view of Cha et al. (US Publication 20200083311).
Regarding dependent claims 5 and 19, Cai in view of Park teaches the display base plate according to claim 1/the display panel according to claim 12.
Cai in view of Park does not teach wherein the power line is arranged in the same layer as a first electrode and a second electrode of the overlapping oxide transistor.
Cha teaches wherein the power line (fig. 3, 301b) is arranged in the same layer as a first electrode (123) and a second electrode (124) of the overlapping oxide transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate of Cai in view of Park and the power line positioning of Cha in order to reduce the non-display area (Cha paragraph 0092).
Regarding dependent claim 7, Cai in view of Park teaches the display base plate according to claim 6.
Cai in view of Park does not teach wherein a first electrode and a second electrode of the polysilicon transistor are arranged in the same layer as a first electrode and a second electrode of the overlapping oxide transistor.
Cha teaches wherein a first electrode (fig. 3 203) and a second electrode (204) of the polysilicon transistor (TFTn) are arranged in the same layer as a first electrode (123) and a second electrode (124) of the overlapping oxide transistor (TFTd).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate of Cai and the arrangement of the first and second electrodes of the transistors of Cha in order that “the source electrode 123 and the drain electrode 124 contacting the semiconductor layer 121 of the transistor TFTd through the contact holes CH1, the source electrode 203 and the drain electrode 204 contacting the semiconductor layer 201 of the transistor TFTn through the contact holes CH3, and the second power line 301b may be formed on the third insulating layer 113” (Cha paragraph 0106).
Regarding dependent claim 8, Cai further teaches the display base plate according to claim 7, wherein the sub-pixel further comprises an anode (fig. 2, 41), and either the first electrode or the second electrode of the polysilicon transistor is electrically connected to the anode (fig. 2, 14b of LTPS TFT connected to 41).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Cai in view of Park as applied to claim 1 above, and further in view of Liu (US Publication 20180114864).
Regarding dependent claims 21 and 22, Cai teaches the display base plate according to claim 1/the display panel according to claim 12, wherein the display base plate further comprises a second buffer layer (fig. 3, 22).
Cai does not teach and a thickness of the second buffer layer is 3000 A.
Liu teaches and a thickness of the second buffer layer is 3000 A (paragraph 0075, “the thickness of the gate insulating layer 12 may be controlled to be between about 300Å to about 3000Å”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display base plate/panel of Cai in view of Park and the thickness of the second buffer layer of Liu in order to cover the gate electrode (Liu paragraph 0021).
Response to Arguments
Applicant’s arguments, see page 9, filed 12/26/2025, with respect to the specification have been fully considered and are persuasive. The objection of 12/26/2025 has been withdrawn.
Applicant’s arguments with respect to claims 1, 3, 5-12, 17, and 19-22 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Applicant’s arguments filed 12/26/2025 have been fully considered but are not persuasive.
Applicant argues on pages 11 of the instant Remarks: “It can be clearly seen from FIG. 2 of Cai that an orthographic projection of 31 is located outside an area of an orthographic projection of 23 on the substrate 10. However, in claim 1 of the present application, an orthographic projection of the active layer 20 of the at least one of the oxide transistors on the substrate 10 is located within an orthographic projection of the first electrode 18 on the substrate 10 as shown in FIG. 14 of the present application, which is different from Cai. In other words, Cai fails to disclose the above distinguishing features.”
However, as stated above, it can be clearly seen from fig. 2 of Cai that an orthographic projection of 31 and an orthographic projection of 23 on the substrate 10 fully overlap each other, therefore an orthographic projection of the active layer 31 is located within an orthographic projection of the first electrode 23 on the substrate 10.
Applicant also argues on pages 11-12 of the instant Remarks: “It can be seen from FIG. 6 of Cai that a plate of the second storage capacitor C' is connected to the power signal line VDD", however, Cai fails to disclose the detailed features showing the specific connection method between the plate of the second storage capacitor C' and the power signal line VDD. In fact, in claim 1 of the present application, the display base plate further comprises a power line, and the first electrode is electrically connected to the power line via a third through hole, which is not disclosed by Cai, rather than the detailed features about the third through hole.”
However, as stated above, Park teaches and the first electrode (fig. 5, CE2) is electrically connected to the power line (PVL2) via a third through hole; an orthographic projection of the third through hole on the substrate overlaps with the orthographic projection of the first electrode on the substrate (fig. 5), and the orthographic projection of the third through hole on the substrate is located outside the orthographic projection of the active layer of the at least one of the oxide transistors on the substrate (fig. 5, orthographic projection of VH2 does not overlap with orthographic projection of ACT(C1) which corresponds to active layer of at least one of the oxide transistors of Cai).
Therefore, claim 1, along with dependent claims 3, 5-12, 17, and 19-22 are not patentable over the cited references.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897