DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 11/10/25, in which: claims 1, 6, 9, and 23 are amended; and the rejection of the claims are traversed. Claims 1-13, 15-20, and 23 are currently pending an Office action on the merits as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-8 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US Publication 20210020704) in view of Kubota et al. (JP Publication 2007148219/Machine Translation Document 08/07/2025).
Regarding independent claims 1 and 23, Kim teaches a display device (fig. 3), comprising a display substrate (10), the display substrate comprising:
a base substrate (100), comprising a first display region (DA3) and a second display region (DA2), wherein the first display region at least partially surrounds the second display region (fig. 3), and a light transmittance of the second display region is greater than a light transmittance of the first display region (paragraph 0072);
a plurality of pixel driving circuits (fig. 6), provided on the base substrate and in the first display region (fig. 3, pixel driving circuits ox PXm located in DA3);
a first planarization layer (fig. 8, 115), provided on a side of the plurality of pixel driving circuits facing away from the base substrate (fig. 8, 115 above Cst, A1, G1, and T6 of pixel driving circuits);
a plurality of light-emitting elements (OLED), provided on a side of the first planarization layer facing away from the base substrate (fig. 8);
a first power supply signal wire (PL), provided on the side of the first planarization layer facing away from the base substrate and in the first display region (fig. 8); and
a data signal wire (DL), provided on the side of the first planarization layer facing away from the base substrate and in the first display region (fig. 8); wherein:
the first planarization layer comprises an element connection via hole (1153 and 1163) electrically connecting at least one of the plurality of pixel driving circuits with at least one of the plurality of light-emitting elements (fig. 8, T6 connected to 210 of OLED via 1153), a power supply via hole (CNT) electrically connecting at least one of the plurality of pixel driving circuits with the first power supply signal wire (fig. 8, HL of pixel driving circuit connected to PL via CNT), and a data via hole (fig. 7, 1154) electrically connecting at least one of the plurality of pixel driving circuits with the data signal wire (paragraph 0150).
Kim does not teach the element connection via hole, the power supply via hole and the data via hole are arranged in a same straight line, and the same straight line extends along a first direction.
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Kubota teaches the element connection via hole (fig. 7, Ha1), the power supply via hole (Ha3) and the data via hole (Ha5) are arranged in a same straight line, and the same straight line extends along a first direction (see figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Kim and the arrangement of holes along a first direction of Kubota in order for “the gate electrode and the drain electrode of the drive transistor Tdr [to be] electrically connected (diode connection)” (machine translation document, page 6 paragraph 3).
Regarding dependent claim 2, Kubota further teaches the display substrate according to claim 1, further comprising:
a first initialization signal wire (fig. 7, 12), configured to provide a first initialization signal to at least one of the plurality of pixel driving circuits (machine translation document, page 6 paragraph 2, “initialization signal Sb is supplied to the initialization line 12 from a drive circuit”);
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wherein a shortest distance between the element connection via hole (Ha1 occupies space for element connection via hole of Kim) and the first initialization signal wire, a shortest distance between the power supply via hole (Ha3 occupies space for power supply via hole of Kim) and the first initialization signal wire, and a shortest distance between the data via hole (Ha5 occupies space for data via hole of Kim) and the first initialization signal wire are substantially equal to each other (see figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Kim and the first initialization signal wire of Kubota per the reason(s) stated above in claim 1.
Regarding dependent claim 3, Kim further teaches the display substrate according to claim 2, wherein the plurality of pixel driving circuits comprise a first pixel driving circuit (fig. 3, PXm) and a second pixel driving circuit (PXc), and the plurality of light-emitting elements comprise a first light-emitting element (fig. 6, OLED of PXm) provided in the first display region and a second light-emitting element (OLED of PXc) provided in the second display region;
the element connection via hole comprises a first via hole (fig. 8, 1163) and a second via hole (1153), the first light-emitting element is electrically connected with the first pixel driving circuit through the first via hole (fig. 8), the second light-emitting element is electrically connected with the second pixel driving circuit through a first connection wire (1175) provided in the first display region and the second display region (paragraph 0127), and in the first display region, the first connection wire is electrically connected with the second pixel driving circuit through the second via hole (fig. 8, 1175 of PXm can be configured to connect to T6 of PXc per MPEP 2144.04).
Regarding dependent claim 4, Kubota further teaches the display substrate according to claim 3, wherein:
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the plurality of pixel driving circuits comprise a plurality of pixel circuit groups (see figure below) extending in the first direction and arranged in a second direction, and at least one of the plurality of pixel circuit groups comprises a plurality of first pixel driving circuits and a plurality of second pixel driving circuits (fig. 1, pixel driving circuits P contain first and second pixel driving circuits of Kim);
a plurality of first via holes, a plurality of second via holes, a plurality of power supply via holes and a plurality of data via holes adopted by the plurality of first pixel driving circuits and the plurality of second pixel driving circuits are arranged along the first direction (fig. 7, Ha1 contains first and second via holes of Kim and holes are arranged in X direction), and the first direction and the second direction intersect with each other (fig. 7).
Regarding dependent claim 5, Kubota further teaches the display substrate according to claim 4, wherein the plurality of first via holes, the plurality of second via holes, the plurality of power supply via holes and the plurality of data via holes adopted by the plurality of first pixel driving circuits and the plurality of second pixel driving circuits in the at least one of the plurality of pixel circuit groups are provided to have shortest distances substantially equal to each other from the first initialization signal wire (refer to marked figure of claim 2).
Regarding dependent claim 6, Kubota further teaches the display substrate according to claim 4, wherein the plurality of first via holes, the plurality of second via holes, the plurality of power supply via holes and the plurality of data via holes adopted by the plurality of first pixel driving circuits and the plurality of second pixel driving circuits in the at least one of the plurality of pixel circuit groups are provided in
Regarding dependent claim 7, Kubota further teaches the display substrate according to claim 6, wherein in a direction parallel to the base substrate, the first connection wire is provided on at least one side of the same straight line (refer to marked figure corresponding to claim 1, Ha1 occupies element connection hole of Kim which has first connection wire of Kim, thus first connection wire is provided on at least one side of straight line).
Regarding dependent claim 8, Kim further teaches the display substrate according to claim 7, wherein an extension direction of the first connection wire from the first display region to the second display region is parallel to the first direction (fig. 8, 1175 extends horizontally).
Claims 9-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kubota as applied to claim 2 above, and further in view of Wei et al. (WO Publication 2021102791/Machine Translation Document 08/07/2025).
Regarding dependent claim 9, Kim further teaches the display substrate according to claim 3, wherein:
the first pixel driving circuit and the second pixel driving circuit respectively comprise a second transistor (fig. 6, T3) serving as a compensation transistor and a third transistor (T1) serving as a driving transistor;
a gate electrode (G3) of the second transistor is connected with a scanning signal wire (SL), and a second electrode (S3) of the second transistor is connected with a second electrode (D1) of the third transistor.
Kubota further teaches the first initialization signal wire is provided in a second conductive layer (fig. 4, conductive elements on top of L0 is second conductive layer), and the second conductive layer is provided on a side of the first conductive layer facing away from the base substrate (fig. 4).
Kim in view of Kubota does not teach a first transistor serving as a reset transistor, a gate electrode of the first transistor is connected with a reset signal wire, a first electrode of the first transistor is connected with the first initialization signal wire, a second electrode of the first transistor is respectively connected with a first electrode of the second transistor and a gate electrode of the third transistor; the gate electrode of the first transistor, the gate electrode of the second transistor, the gate electrode of the third transistor, the scanning signal wire and the reset signal wire are provided in a first conductive layer provided on the base substrate.
Wei teaches a first transistor (fig. 1, T6) serving as a reset transistor, a gate electrode (T60) of the first transistor is connected with a reset signal wire (111 and 112, T60 connected to 111), a first electrode (T61) of the first transistor is connected with the first initialization signal wire (211), a second electrode (T62) of the first transistor is respectively connected with a first electrode (T32) of the second transistor and a gate electrode (T10) of the third transistor;
the gate electrode of the first transistor, the gate electrode of the second transistor, the gate electrode of the third transistor, the scanning signal wire (113) and the reset signal wire are provided in a first conductive layer provided on the base substrate (fig. 4C).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Kim in view of Kubota and the reset transistor of Wei in order to “provide a reset control signal RESET to the pixel circuit structure” (machine translation, page 8 paragraph 3).
Regarding dependent claim 10, Kim further teaches the display substrate according to claim 9, wherein:
the first pixel driving circuit and the second pixel driving circuit further respectively comprise a storage capacitor (fig. 6, Cst), a fourth transistor (T2) serving as a data writing transistor and a fifth transistor (T5) serving as a light emission control transistor;
a gate electrode (G2) of the fourth transistor is connected with the scanning signal wire (SL), a first electrode (S2) of the fourth transistor is connected with the data signal wire (DL), a second electrode (D2) of the fourth transistor is connected with a first electrode (S1) of the third transistor, a gate electrode (G5) of the fifth transistor is connected with a light emission control wire (EL), a first electrode (S5) of the fifth transistor is connected with a second electrode plate of the storage capacitor (connected to Cst2 via PL), and a second electrode (D5) of the fifth transistor is connected with the first electrode of the third transistor.
Wei further teaches the light emission control wire (fig. 4B, 110) is provided in the first conductive layer (L1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Kim in view of Kubota and the light emission control wire of Wei per the reason(s) stated above in claim 9.
Regarding dependent claim 11, Wei further teaches the display substrate according to claim 10, wherein:
the first pixel driving circuit and the second pixel driving circuit further respectively comprise a sixth transistor (fig. 1, T5) serving as a light emission control transistor and a seventh transistor (T7) serving as a reset transistor;
a gate electrode (T50) of the sixth transistor is connected with the light emission control wire (110), a first electrode (T51) of the sixth transistor is connected with the second electrode (T12 corresponds to fig. 6 D1 of Kim) of the third transistor, the first light-emitting element or the second light-emitting element (20) is connected with a second electrode (T52) of the sixth transistor, a gate electrode (T70) of the seventh transistor is connected with the reset signal wire (T70 connected to 112), a first electrode (T71) of the seventh transistor is connected with a second initialization signal wire (212), and a second electrode (T72) of the seventh transistor is connected with the second electrode of the sixth transistor (fig. 1);
the second initialization signal wire is provided in the second conductive layer (fig. 4D, L2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Kim in view of Kubota and the sixth and seventh transistors of Wei per the reason(s) stated above in claim 9.
Regarding dependent claim 12, Wei further teaches the display substrate according to claim 11, wherein in the first direction parallel to the base substrate, the second initialization signal wire, the reset signal wire, the first initialization signal wire and the scanning signal wire for a same first pixel driving circuit or a same second pixel driving circuit are sequentially arranged (fig. 4E).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Kim in view of Kubota and the arrangement of wires of Wei per the reason(s) stated above in claim 9.
Regarding dependent claim 13, Kim further teaches the display substrate according to claim 10, wherein:
the second transistor comprises an active layer (paragraph 0134) and two gate electrodes (paragraph 0126), the active layer is provided in a semiconductor material layer (fig. 7, 1130) provided between the first conductive layer and the base substrate (paragraph 0129);
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the active layer comprises a first portion (see figure below), and an orthographic projection of the first portion on the base substrate does not overlap with orthographic projections of the two gate electrodes on the base substrate (see figure below);
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Wei further teaches the second conductive layer comprises a shielding pattern (see figure below), and the orthographic projection of the first portion on the base substrate overlaps with an orthographic projection of the shielding pattern on the base substrate (see figure below).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Kim in view of Kubota and the shield pattern of Wei per the reason(s) stated above in claim 9.
Regarding dependent claim 15, Wei further teaches the display substrate according to claim 13, wherein:
the semiconductor material layer comprises a semiconductor pattern (fig. 4A, SCP) for connecting the active layer of the second transistor with an active layer of the first transistor (fig. 4C);
an orthographic projection of the semiconductor pattern on the base substrate overlaps with the orthographic projection of the shielding pattern on the base substrate (fig. 4C).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Kubota and further in view of Wei as applied to claim 9 above, and further in view of Peng (CN Publication 20080121886/Machine Translation Document 08/07/2025).
Regarding dependent claim 16, Kim in view of Kubota and further in view of Wei teaches the display substrate according to claim 9.
Kim in view of Kubota and further in view of Wei does not teach wherein the first electrode and the second electrode of the first transistor, the first electrode and the second electrode of the second transistor, and the first electrode and the second electrode of the third transistor are provided in a third conductive layer, and the third conductive layer is provided on a side of the second conductive layer facing away from the base substrate.
Peng teaches wherein the first electrode and the second electrode of the first transistor, the first electrode and the second electrode of the second transistor, and the first electrode and the second electrode of the third transistor are provided in a third conductive layer (fig. 2, 6011, 6012, and 6013 corresponds to first and second electrodes of first through seventh transistors), and the third conductive layer is provided on a side of the second conductive layer facing away from the base substrate (fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Kim in view of Kubota and further in view of Wei and the third conductive layer of Peng in order to provide a “connection of the anode and the thin film transistor” (machine translation, page 8 paragraph 1).
Regarding dependent claim 17, Kim further teaches the display substrate according to claim 16, wherein the first power supply signal wire is provided in a fourth conductive layer (fig. 8, elements on top of 115 correspond to fourth conductive layer upon which first power supply signal wire PL is part of), and the fourth conductive layer is provided on a side of the third conductive layer facing away from the base substrate (fig. 8).
Regarding dependent claim 18, Kim further teaches the display substrate according to claim 17, wherein the data signal wire is provided in the fourth conductive layer (fig. 8, elements on top of 115 correspond to fourth conductive layer upon which data signal wire DL is part of).
Regarding dependent claim 19, Wei further teaches the display substrate according to claim 16, wherein:
the third conductive layer further comprises a connection portion (fig. 3A, 31b) provided between the second electrode of the first transistor and the gate electrode of the third transistor (machine translation, page 10 paragraph 3, “second electrode T62 of T6 is electrically connected to the gate T10 of the driving transistor T1 through the second connecting electrode 31b”).
Kubota further teaches the first power supply signal wire further comprises a protrusion (fig. 15, 152 bottom);
an orthographic projection of the connection portion on the base substrate overlaps with an orthographic projection of the protrusion on the base substrate (fig. 15, orthographic projection of connection portion of Wei can be configured to overlap orthographic projection of protrusion of first power supply signal of Kubota per MPEP 2144.04).
Regarding dependent claim 20, Kubota further teaches the display substrate according to claim 19, wherein the orthographic projection of the connection portion on the base substrate is within the orthographic projection of the protrusion on the base substrate (fig. 15, orthographic projection of connection portion of Wei can be configured to be within the orthographic projection of protrusion of first power supply signal of Kubota per MPEP 2144.04).
Response to Arguments
Applicant’s arguments with respect to claims 1-13, 15-20, and 23 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Applicant’s arguments filed 11/10/2025 have been fully considered but are not persuasive.
Applicant argues on pages 13-15 of the instant Remarks: “Figure 6 of the present disclosure is reproduced below in aid of discussion. Figure 6 depicts that (paragraph [0067]), in the embodiments of the present disclosure, the element connection via hole V1/V2, the power supply via hole V3 and the data via hole V4 are arranged along a same line L1 extending along the first direction (e.g., a horizontal direction in Fig. 6). Figure 7 of Kim is reproduced below. Figure 7 depicts that the contacts holes CNT, 1153, 1163 and 1154 are not located in a same straight line along a first direction. Accordingly, Kim fails to disclose the above-quoted feature of amended claim 1. Kubota does not remedy the deficiencies of Kim. Kim is silent about the element connection via hole, the power supply via hole and the data via hole V4, as well as their arrangement. Accordingly, it is respectfully submitted that Kubota does not disclose, teach or suggest the above-quoted features of amended claim 1. Other references Wei and Peng also silent about the above-quoted features of amended claim 1.”
However, as stated above in claim 1, Kubota does disclose, teach or suggest the element connection via hole (fig. 7, Ha1), the power supply via hole (Ha3) and the data via hole (Ha5) are arranged in a same straight line, and the same straight line extends along a first direction (see marked figure corresponding to claim 1).
Examiner also notes applicant does not address the specification objection and the 112(b) claim rejections in the argument, however, the amendments made to the title and claim 9 overcomes the previous objection/112(b) rejection of 08/07/2025.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897