Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of Claims
Examiner notes that in the instant application:
-Claims 1-14, and 16 are pending.
-Claim 15 is cancelled.
-Claims 1, 2, 7, and 8 are Amended.
Priority
Examiner noted in the previous Office Action, dated June 12, 2025, hereinafter the “Non-Final”, that in order to effectively benefit from the foreign priority date based on the application filed in Japan on August 24, 2020, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented. The Applicant has not included these documents in the instant application. Therefore, the right to foreign priority under 35 U.S.C. 119 (a)-(d) is not considered perfected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 24, 2025 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title
Acknowledgement is made of Applicant’s replacement of the title of the invention to a new title which is more clearly indicative of the invention to which the claims are directed. The objection to the title is hereby withdrawn.
Claim Objections
Acknowledgement is made of Applicant’s amendment to Claim 2 as it relates to the claim objection over informalities in the Non-Final. However, Applicant needs to include the article --an-- before “Fe concentration” in the claim limitation. The Claim Objection of the Non-Final is maintained.
Upon review, the additional claim objections are found.
Claims 1, 6, and 7 are objected to because of the following informalities:
Regarding Claim 1, The limitation
“the low concentration region has Si concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, O concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, and Mg concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less,
at least one of C concentration and Fe concentration in the low concentration region is higher than any of Si concentration, O concentration, and Mg concentration in the low concentration region, and 5*1019 atoms/cm3 or less.”
has unclear syntax, is missing articles, and contains typographical errors.
For the purposes of this Office Action, the limitation of Claim 1 above shall be read by the Examiner as follows:
-- the low concentration region has a Si concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less,
a C concentration and/or a Fe concentration in the low concentration region are/is higher than any of the Si concentration, the O concentration, and the Mg concentration in the low concentration region, and are/is 5*1019 atoms/cm3 or less.--
Regarding Claim 6, The limitation
“wherein Si concentration, O concentration, Mg concentration, C concentration and Fe concentration of the electronic traveling layer are all greater than 0 and less than or equal to 1*1017 atoms/cm3.”
is missing articles.
For the purposes of this Office Action, the limitation of Claim 6 above shall be read by the Examiner as follows:
--wherein a Si concentration, an O concentration, a Mg concentration, a C concentration and an Fe concentration of the electronic traveling layer are all greater than 0 and less than or equal to 1*1017 atoms/cm3.--
Regarding Claim 7, The limitation
“the high concentration region has Si concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less, O concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less, and Mg concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less,
the main layer has Si concentration of 0 atoms/cm3 or more and 2* 1016 atoms/cm3 or less, O concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, and Mg concentration of 0 atoms/cm3 or more and 2* 1016 atoms/cm3 or less,
at least one of C concentration and the Fe concentration in the second nitride semiconductor layer is higher than any of Si concentration, O concentration, and Mg concentration in the second nitride semiconductor layer and is 5*1019 atoms/cm3 or less,
the main layer includes a region where concentration of activated donor ions is 0 atoms/cm3 or more and 2* 1014 atoms/cm3 or less, and
the electronic traveling layer has Si concentration of 0 atoms/cm3 or more and 1 * 1016 atoms/cm3 or less, O concentration of 0 atoms/cm3 or more and 1 * 1016 atoms/cm3 or less, and Mg concentration of 0 atoms/cm3 or more and 1 * 1016 atoms/cm3 or less, C concentration of 0 atoms/cm3 or more and 1*1017 atoms/cm3 or less, and Fe concentration of 0 atoms/cm3 or more and 1*1017 atoms/cm3 or less.”
has unclear syntax and is missing articles.
For the purposes of this Office Action, the limitation of Claim 2 above shall be read by the Examiner as follows:
--the high concentration region has a Si concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less,
the main layer has a Si concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less,
a C concentration and/or an Fe concentration in the second nitride semiconductor layer are/is higher than any of the Si concentration, the O concentration, and the Mg concentration in the second nitride semiconductor layer and are/is 5*1019 atoms/cm3 or less,
the main layer includes a region where a concentration of activated donor ions is 0 atoms/cm3 or more and 2*1014 atoms/cm3 or less, and
the electronic traveling layer has a Si concentration of 0 atoms/cm3 or more and 1*1016 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 1*1016 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 1*1016 atoms/cm3 or less, a C concentration of 0 atoms/cm3 or more and 1*1017 atoms/cm3 or less, and an Fe concentration of 0 atoms/cm3 or more and 1*1017 atoms/cm3 or less.--
Appropriate correction is required.
Response to Arguments
Applicant's arguments and amendments filed September 11, 2025, hereinafter the “Response”, have been fully considered but they are not persuasive.
On Page 9 and 10 of the Response, Applicant states that the newly added limitations of Claim 1, 7, and 8 are supported by Paragraph [0058] and proceeds to quote from the instant application’s Specification. Examiner firstly must point out that the text quoted of the paragraph referenced do not match what is found in the Specification in the file wrapper of the application, nor the publication of the instant application (U.S. Pub. 2023/0343865). Examiner is unsure of what document is being referenced by the Applicant in the Response, but the quoted text seems to be from Paragraphs [0080] and [0083] of the Specification.
Referring back to the Response, Applicant argues that the Specification “emphasizes that by intentionally doping the first nitride semiconductor layer with carbon and/or iron, the concentration of carbon and/or iron in the low concentration region becomes greater than that of silicon, oxygen, and magnesium, while remaining at or below 5 x 1019 atoms/cm3.” (emphasis added) The Examiner finds no support for this position.
Examiner brings Applicant’s attention to Paragraph [0083] of the Specification:
“When first nitride semiconductor layer 4 is a uid layer, the first region of first nitride semiconductor layer 4 has a Si concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less. The second region of first nitride semiconductor layer 4 has a Si concentration of 0 atoms/cm3 to 2*1016 atoms/cm3, an O concentration of 0 atoms/cm3 to 2*1016 atoms/cm3, and a Mg concentration of 0 atoms/cm3 to
2*1016 atoms/cm3. Further, at least one of C concentration and Fe concentration in the second region of first nitride semiconductor layer 4 is higher than all the Si concentration, the O concentration and the Mg concentration in the second region of first nitride semiconductor layer 4, and is 5*1019 atoms/cm3 or less.” (emphasis added)
Notably, the concentrations provided for the second region of first nitride semiconductor layer of Paragraph [0083] matches those recited for the low concentration region of the first nitride semiconductor layer in the newly amended Claim 1. Thus, the concentrations incorporated by the amendment limitations are necessarily those of an unintentionally doped (uid) first nitride layer.
Furthermore, in the Response, Applicant argues that Suzuki et al. (WO 2020/149184), hereinafter Suzuki, “describes a nitride semiconductor layer 4 (see Fig. 5) that merely functions as a buffer layer” and “Suzuki's nitride semiconductor layer is not insulating”. This is an argument for a negative, which cannot be sustained as a lack of a statement about an intention to use a material in a particular way does not preclude one from utilizing its characteristics. Moreso, the intended use of a material does not change the material’s characteristics, i.e. if an insulator is used as a buffer layer, it’s still insulating. Furthermore, Suzuki directly states that by incorporating the nitride semiconductor layer (4) into the compound semiconductor substrate (CS1), the “insulation breakdown voltage [is] higher than GaN insulation breakdown voltage. As a result, the vertical withstand voltage of the compound semiconductor substrate can be improved” (Paragraph [0057]). Thus, Suzuki identifies it as insulating.
As was previously presented in the Non-Final, because Suzuki has a shared formation process as the first nitride semiconductor layer of the instant application, wherein no intentional doping is further incorporated, Suzuki necessarily teaches the same structure. See MPEP § 2112 II-III.
The rejections have been updated to address the newly amended limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. (WO Pub. 2020149184), hereinafter Suzuki, in view of Umeda et al. (U.S. Pub. 2015/0171173), hereinafter Umeda. In the remainder of this Office Action, the US version of Suzuki (U.S. Pub. 2022/0069090) is used for references and quotations. This is solely for translational purposes.
Regarding Claim 1, Suzuki teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) comprising:
-a Si substrate ((1); Fig. 5, Paragraph [0035]),
-a SiC layer ((2); Fig. 5, Paragraph [0036]) formed on the Si substrate (1),
-a first nitride semiconductor layer made of AlxGa1-xN (0.1
≤
x
≤
1) ((4); Fig. 5, Paragraph [0039]), formed on the SiC layer (2) and including an insulating or semi-insulating layer (e.g. layer (43); Fig. 5, Paragraph [0053]),
-a second nitride semiconductor layer (‘compound layer’ (5); Fig. 5, Paragraph [0040]) formed on the first nitride semiconductor layer (4) and including a main layer comprising of insulating or semi-insulating AlyGa1-yN (0
≤
y<0.1) (e.g. ‘C-GaN’ layer (51b); Fig. 5, Paragraph [0041]),
-an electronic traveling layer (‘GaN layer’ (7); Fig. 5, Paragraph [0050]) formed on the second nitride semiconductor layer (5) and made of AlzGa1-zN (0
≤
z<0.1) (GaN), and
-a barrier layer (‘Al nitride semiconductor layer’ (10); Fig. 5, Paragraph [0051]) formed on the electronic traveling layer (7) and having a wider band gap than a band gap of the electronic traveling layer (AlGaN intrinsically has a higher band gap than GaN), wherein
-a sum total thickness of the first ((4), 500nm
≤
thickness
≤
2
μ
m
; Paragraph [0039]) and second nitride semiconductor layers ((5), 550nm
≤
thickness of each C-GaN layer (51)
≤
3
μ
m
; Paragraph [0043]) and the electronic traveling layer ((7), 100nm
≤
thickness
≤
1
μ
m
; Paragraph [0050]) is 6 micrometers or more and 10 micrometers or less (As given by thickness values above).
-the first nitride semiconductor layer (4) includes a low concentration region made of AlxGa1-xN (0.1≤x≤0.4) (e.g. layer (43); Fig. 5, Paragraph [0053]) having a thickness of 0.5 micrometer or more (Suzuki Figs. 2 and 4 show (43) makes up the larger portion of (4), being at least greater than (41) and (42) individually. Therefore, if (4) is 2 micrometers (Paragraph [0039]) (43) is necessarily 0.5 micrometer or more).
-the low concentration region has a Si concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less,
-a C concentration and/or a Fe concentration in the low concentration region are/is higher than any of the Si concentration, the O concentration, and the Mg concentration in the low concentration region, and are/is 5*1019 atoms/cm3 or less.
(Suzuki teaches the formation of the low concentration region (43), using MOCVD, on top of a AlN buffer layer (3), the same method and placement by which the first nitride layer is formed in the instant application (Paragraph [0079], in the instant application, the AlN buffer layer is grouped in the first nitride layer as element (40)). This is further matched by the figures of the Al composition ratio, note the only difference is the incorporation of the AlN layer into the graphs: see Suzuki Fig. 2 and instant application Fig. 2; Suzuki Fig. 6 and instant application Fig. 6; Suzuki Fig. 7 and application Fig. 7. The instant application further discloses that impurities are not intentionally introduced when forming the layer (Paragraph [0080]-[0083]). The limitations above therefore refer to impurities that are resultant of a standard MOCVD process when forming a AlGaN layer above a AlN layer and are inherent. Thus, due to the shared formation process, the prior art necessarily teaches the same structure. See MPEP § 2112 II-III)
Suzuki does not teach:
-a Si substrate with O concentration of 3*1017/cm3 or more and 3*1018/cm3 or less.
Umeda teaches a nitride semiconductor structure, wherein:
- a Si substrate ((101); Fig. 1; Paragraph [0029]) with O concentration of 3*1017/cm3 or more and 3*1018/cm3 or less (Paragraph [0045]).
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the teachings of Umeda into the device of Suzuki such that it is made with a Si substrate with O concentration of 3*1017/cm3 or more and 3*1018/cm3 or less. This would be due to the fact that doing so would increase the strength of the silicon substrate and mitigate cracks and warping of subsequently formed layers (Umeda, Paragraphs [0025] and [0050]).
Regarding Claim 2, Suzuki as modified by Umeda teaches the compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
-the second nitride semiconductor layer (Suzuki, (5)) further includes at least one intermediate layer (Suzuki, e.g. layer (52b); Fig. 5, Paragraph [0075]) formed within of the main layer and/or on the main layer ((Suzuki, (51b)), the intermediate layer (Suzuki, (52b)) comprising of AlyGa1-yN (0.5
≤
y
≤
1) (Suzuki, ‘AlN’; Paragraph [0075]), and
-the main layer (Suzuki, (51b)) has a C concentration higher than that of the electronic traveling layer and/or an Fe concentration higher than that of the electronic traveling layer (Suzuki, In this case C-GaN of (51b) has a C concentration higher than the undoped GaN of (7); Paragraph [0048]).
Regarding Claim 3, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 2, wherein:
the intermediate layer is two or more layers (Suzuki, e.g. (52a) and (52b); Fig. 5), and each of the two or more intermediate layers has a thickness of 10 nanometers or more and 30 nanometers or less (Suzuki, Paragraph [0044]), and is formed at intervals of 0.5 micrometers or more and 10 micrometers or less (Suzuki, as given by thickness of C-GaN layer (51b) between them; Cited in Claim 1, see Paragraph [0043]).
Regarding Claim 4, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
-the Si substrate (1) has p type conductivity (Suzuki, ‘consists of, for example p+ type Si’; Paragraph [0035]).
Umeda further teaches:
-the Si substrate contains B, and has p type conductivity (The p-type silicon shown in FIG. 2 is a silicon containing boron as the p-type impurity.) and a resistivity of 0.1 mΩcm or more and 100 mΩcm or less (corresponding to an impurity concentration of 2*1017cm-3 to 1021cm-3; Fig. 2)
It would have been obvious to one of ordinary skill in the art at the time the claims were effectively filed to incorporate the further teachings of Umeda into the device of Suzuki as initially modified by Umeda such that the Si substrate contains B, and has p type conductivity and a resistivity of 0.1 mΩcm or more and 100 mΩcm or less. This would be due the fact doing so would increase device performance by reaching a desired maximum width of the depletion layer obtained from the impurity concentration (Umeda, Paragraph [0038]).
Regarding Claim 5, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
-the SiC layer (Suzuki, (2)) has a thickness of 0.5 micrometers or more and 2 micrometers or less (Suzuki, ‘0.1 micrometers or more and 3.5 micrometers or less’; Paragraph [0037]).
Regarding Claim 6, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
- wherein a Si concentration, a O concentration, a Mg concentration, a C concentration and a Fe concentration of the electronic traveling layer are all greater than 0 and less than or equal to 1*1017 atoms/cm3. (Suzuki teaches the formation of (7), using MOCVD, on top of a C-GaN layer, the same method and placement by which the electronic traveling layer is formed in the instant application (Paragraph [0097]). The instant application further discloses that impurities are not intentionally introduced when forming the layer (Paragraph [0097]). The limitation above therefore refers to impurities that are resultant of a standard MOCVD process when forming a GaN layer above a C-GaN layer and are inherent. Thus, due to the shared formation process, the prior art necessarily teaches the same structure. See MPEP § 2112 II-III)
Regarding Claim 7, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 6, wherein:
-the first nitride semiconductor layer (Suzuki, (4)) further includes a high concentration region made of AlxGa1-xN (0.4<x≤1) (e.g. layer (41); Fig. 5, Paragraph [0053]).
-the high concentration region has a Si concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 5*1017 atoms/cm3 or less,
(Suzuki teaches the formation of the high concentration region (41) using MOCVD, on top of a AlN buffer layer (3), the same method and placement by which the first nitride layer is formed in the instant application (Paragraph [0079], in the instant application, the AlN buffer layer is grouped in the first nitride layer as element (40)). This is further matched by the figures of the Al composition ratio, note the only difference is the incorporation of the AlN layer into the graphs: see Suzuki Fig. 2 and instant application Fig. 2; Suzuki Fig. 6 and instant application Fig. 6; Suzuki Fig. 7 and application Fig. 7. The instant application further discloses that impurities are not intentionally introduced when forming the layer (Paragraph [0080]-[0083]). The limitations above therefore refer to impurities that are resultant of a standard MOCVD process when forming a AlGaN layer above a AlN layer and are inherent. Thus, due to the shared formation process, the prior art necessarily teaches the same structure. See MPEP § 2112 II-III)
the main layer has a Si concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 2*1016 atoms/cm3 or less,
a C concentration and/or an Fe concentration in the second nitride semiconductor layer are/is higher than any of the Si concentration, the O concentration, and the Mg concentration in the second nitride semiconductor layer and are/is 5*1019 atoms/cm3 or less,
the main layer includes a region where a concentration of activated donor ions is 0 atoms/cm3 or more and 2*1014 atoms/cm3 or less, and
(Suzuki teaches the formation of the second nitride layer (5) and main layer (51b), using MOCVD, on top of a second region (43), and using a lower growth temperature so that C contained in the Ga source gas is taken into the GaN layer (Paragraphs [0045] and [0046]), the same method and placement by which the electronic traveling layer is formed in the instant application (Paragraph [0092])). The instant application further discloses that impurities are not intentionally introduced when forming the layer (Paragraph [0086]). The limitations above therefore refer to impurities that are resultant of a standard MOCVD process when forming a C-GaN layer above a AlGaN layer and are inherent. Thus, due to the shared formation process, the prior art necessarily teaches the same structure. See MPEP § 2112 II-III)
-the electronic traveling layer has a Si concentration of 0 atoms/cm3 or more and 1*1016 atoms/cm3 or less, an O concentration of 0 atoms/cm3 or more and 1*1016 atoms/cm3 or less, and a Mg concentration of 0 atoms/cm3 or more and 1*1016 atoms/cm3 or less, a C concentration of 0 atoms/cm3 or more and 1*1017 atoms/cm3 or less, and an Fe concentration of 0 atoms/cm3 or more and 1*1017 atoms/cm3 or less. (As detailed in Claim 6 above, Suzuki necessarily teaches (7) to be the same structure as the electronic traveling layer of the instant application).
Regarding Claim 8, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 7, wherein:
-a distance between the high concentration region (Suzuki, (41)) and the SiC layer (Suzuki, (2)) is less than a distance between the low concentration region (Suzuki, (43)) and the SiC layer ((41) is formed directly on AlN layer (3) which itself is directly on (2), while (43) is above (41) and is necessarily a greater distance from (2)).
Regarding Claim 9, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
- the first nitride semiconductor layer (Suzuki, (4)) has a thickness less than or equal to a thickness of the second nitride semiconductor layer (Suzuki, (5)) (Suzuki, as given by range of thicknesses of (4) and constituting portions of (5); Cited in Claims 1 and 3, see Paragraphs [0039], [0043], and [0044]).
Regarding Claim 10, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
-the electronic traveling layer (Suzuki, (7)) has a thickness of 0.3 micrometers or more (Suzuki, ‘100 nanometers or more and 1000 nanometers or less’; Paragraph [0050]).
- Regarding Claim 11, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
- stipulating a least squares plane of a top surface of the compound semiconductor substrate, when a sum total value of distance from the least squares plane to a highest point of the top surface of the compound semiconductor substrate and distance from the least squares plane to a lowest point of the top surface of the compound semiconductor substrate is defined as a warpage amount (Suzuki, warpage is further defined as either being ‘convex’ or ‘concave’ relating to the least square plane of a top surface being either the higher point or the lower point, respectively [Paragraph [0097]), the warpage amount is 0 or more and 50 or less micrometers (Suzuki, e.g. for (CS2), ‘27 micrometers’; Paragraph [0098]).
Regarding Claim 12, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
- regions other than an area where a distance from an outer edge of a top surface of the compound semiconductor substrate is 5 millimeters or less (Suzuki, corresponding to the area between the center (PT1) and outer mark (PT2); top view on Fig. 4 and as applied to cross-sectional Fig. 10, Paragraph [0069]) do not contain cracks (Suzuki, Paragraphs [0016], [0054]).
Regarding Claim 13, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 1, wherein:
- the compound semiconductor substrate (Suzuki, (CS2) being a embodiment of (CS1) and thus is still formed on a wafer) has a disk shape and a diameter of 100 millimeters or more and 200 millimeters or less (Suzuki, Fig. 4, Paragraph [0035]).
Regarding Claim 14, Suzuki as modified by Umeda teaches a compound semiconductor substrate ((CS2); Fig. 5, Paragraph [0074]) of Claim 2, wherein:
- a top surface of the compound semiconductor substrate does not contain traces of meltback etching (Suzuki, Paragraphs [0017] and [0109])
Regarding Claim 16, Suzuki as modified by Umeda a compound semiconductor device ((CS2); Fig. 5, Paragraph [0074], specifically as a form of an HEMT, Paragraph [0034]) comprising:
- the compound semiconductor substrate according to claim 1 (detailed above),
-first and second electrodes (corresponding to source and drain contacts) formed on the barrier layer (Suzuki, (10), ‘Al nitride semiconductor layer (10) becomes a barrier layer of the HEMT’; Paragraph [0051]), and
-a third electrode (corresponding to a gate contact) which is formed on the barrier layer (Suzuki, (10)) and controls current flowing between the first and second electrode according to applied voltage (Suzuki, via (7) which ‘becomes an electronic traveling layer of the HEMT’; Paragraph [0050]).
(Suzuki discloses the inclusion of a HEMT in the compound semiconductor substrate (Paragraph [0034]), while Suzuki does not directly discuss the formation of contacts, it would have been obvious to one of ordinary skill in the art to incorporate into the device of Suzuki as modified by Umeda three contacts (corresponding to a source, a drain, and a gate) in order to have a functional HEMT).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/D.M./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812