DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed June 11, 2026 has been entered. Claims 1 and 4-20 remain pending in the application.
Claim Objections
The lineout in the last line of claim 1 does not include everything from the previously presented claim 1 filed December 22, 2025. For purposes of Examination, Examiner will interpret the missing section as also deleted since there is a period amended at the end of the last non-deleted limitation. Applicant is asked to expressly show the deletion in a subsequent filing.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et. al. (US 20230329050 A1), hereinafter Choi.
Regarding claim 1, Choi teaches a display substrate (Fig 3 not labeled display device, [0071]), comprising: a base substrate (Figs 3 and 6 substrate SUB, [0079]); a drive circuit layer (Fig 6 layer containing transistors, such as TFT2) on a side of the base substrate (Fig 6 substrate SUB, [0079]), wherein the drive circuit layer (Fig 6 layer containing transistors, such as TFT2) comprises a plurality of first pixel circuits (Fig 3 Examiner considers transistors of pixel driving units PDU1 to be the pixel circuits, [0085]) on one side (Fig 6 upper side) of the base substrate (Figs 3 and 6 substrate SUB, [0079]); a first flat layer (Fig 6 dielectric layer 142, [0130]) on a side of the drive circuit layer (Fig 6 layer containing transistors, such as TFT2) away from the base substrate (Fig 6 substrate SUB, [0079]), wherein the first flat layer (Fig 6 dielectric layer 142, [0130]) is provided with a first via hole (See annotated figure) penetrating through the first flat layer (Fig 6 dielectric layer 142, [0130]); a first conductive layer (Fig 6 portion of electrode D1 on layer 142) on a side of the first flat layer (Fig 6 dielectric layer 142, [0130]) away from the base substrate (Fig 6 substrate SUB, [0079]); a second flat layer (Fig 6 planarization layer 151, [0133]) on a side of the first conductive layer (Fig 6 portion of electrode D1 on layer 142) away from the base substrate (Fig 6 substrate SUB, [0079]), wherein the second flat layer (Fig 6 planarization layer 151, [0133]) is provided with a second via hole (See annotated figure) penetrating through the second flat layer (Fig 6 planarization layer 151, [0133]); a second conductive layer (Fig 6 portion of electrode BE1 on layer 151) on a side of the second flat layer (Fig 6 planarization layer 151, [0133]) away from the base substrate (Fig 6 substrate SUB, [0079]); a third flat layer (Fig 6 planarization layer 152, [0134]) on a side of the second conductive layer (Fig 6 portion of electrode BE1 on layer 151) away from the base substrate (Fig 6 substrate SUB, [0079]), wherein the third flat layer (Fig 6 planarization layer 152, [0134]) is provided with a third via hole (See annotated figure) penetrating through the third flat layer (Fig 6 planarization layer 152, [0134]), and an orthogonal projection of the first via hole (See annotated figure) on the base substrate (Fig 6 substrate SUB, [0079]) and an orthogonal projection of the third via hole (See annotated figure) on the base substrate (Fig 6 substrate SUB, [0079]) have an overlapping region (Fig 6; The wider portions of the via have an overlapping region), and the first via hole (See annotated figure) and the third via hole (See annotated figure) form a first group of holes; a third conductive layer (Fig 6 portion of electrode BE2 on layer 152) on a side of the third flat layer (Fig 6 planarization layer 152, [0134]) away from the base substrate (Fig 6 substrate SUB, [0079]); a fourth flat layer (Fig 6 planarization layer 153, [0139]) on a side of the third conductive layer (Fig 6 portion of electrode BE2 on layer 152) away from the base substrate (Fig 6 substrate SUB, [0079]), wherein the fourth flat layer (Fig 6 planarization layer 153, [0139]) is provided with a fourth via hole (See annotated figure) penetrating through the fourth flat layer (Fig 6 planarization layer 153, [0139]), and the second via hole (See annotated figure) and the fourth via hole (See annotated figure) for a second group of holes; a plurality of first light-emitting devices (Fig 3 light-emitting elements LE, [0079]) comprising first electrodes (Fig 6 pixel electrode 171, [0140]), wherein the first electrodes (Fig 6 pixel electrode 171, [0140]) are located on one side (Fig 6 upper side) of the fourth flat layer (Fig 6 planarization layer 153, [0139]) away from the base substrate (Fig 3 substrate SUB, [0079]), and the first electrodes (Fig 6 pixel electrode 171, [0140]) each passes through (a portion pf the electrode passes through the via hole) the fourth via hole (See annotated figure), wherein the first pixel circuit (Fig 6 Examiner considers transistors of pixel driving units PDU1 to be the pixel circuits, [0085]) is electrically connected (Fig 6 the bridge electrodes electrically connect the light-emitting elements LE to the Examiner considers transistors of pixel driving units PDU1 to be the pixel circuits) with the first electrode (Fig 6 pixel electrode 171, [0140]) via the first conductive layer (Fig 6 portion of electrode D1 on layer 142) passing through the first via hole (See annotated figure), the second conductive layer (Fig 6 portion of electrode BE1 on layer 151) passing through the second via hole (See annotated figure), and the third conductive layer (Fig 6 portion of electrode BE2 on layer 152) passing through the third via hole (See annotated figure) in sequence (Fig 6); and a pixel defining layer (Fig 6 pixel-defining film 160, [0140]) on one side (Fig 6 upper side) of the first electrodes (Fig 6 pixel electrode 171, [0140]) away from (Fig 6 upper side) the base substrate (Fig 6 substrate SUB, [0122]) and comprising an opening (Fig 6 not labeled opening in pixel-defining film 160 for light-emitting elements LE) exposing the first electrode (Fig 6 pixel electrode 171, [0140]), wherein an orthographic projection of the opening (Fig 6 not labeled opening in pixel-defining film 160 for light-emitting elements LE) on the base substrate (Fig 6 substrate SUB, [0122]) does not overlap (Fig 6 the orthographic projections do not overlap) an orthographic projection (Fig 6) of the second group of holes on the base substrate (Fig 6 substrate SUB, [0122]).
Choi fails to teach an orthographic projection of the second via hole on the base substrate and an orthographic projection of the fourth via hole on the base substrate have an overlapping region, and an orthographic projection of the first group of holes on the base substrate does not overlap with an orthographic projection of the second group of holes on the base substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have rearranged the locations of the via holes such that an orthographic projection of the second via hole on the base substrate and an orthographic projection of the fourth via hole on the base substrate have an overlapping region, and an orthographic projection of the first group of holes on the base substrate does not overlap with an orthographic projection of the second group of holes on the base substrate, with no change in the device’s function, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. MPEP 2144.04 (VI)(C)
Further, Choi shows the locations of the via holes of the different layers at different locations in Fig 6 and Fig 7. Also, Examiner notes that since the via holes have two different widths, one having ordinary skill in the art before the effective filing date of the claimed invention would be able to move the via holes such that the required overlapping and non-overlapping regions limitations would be met.
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Regarding claim 5, Choi as modified in claim 1 fails to teach an orthographic projection of the second group of holes on the base substrate does not overlap an orthographic projection of the first group of holes on the base substrate.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have rearranged the location of the via holes such that an orthographic projection of the second group of holes on the base substrate does not overlap an orthographic projection of the first group of holes on the base substrate, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. MPEP 2144.04 (VI)(C).
Additionally, the rearrangement of the via holes would not change the operation of the device
as the via holes would still provide the necessary interconnection.
Regarding claim 19, Choi teaches a display panel (Fig 1 display panel 10, [0061]), comprising the display substrate according to claim 1.
Regarding claim 20, Choi teaches a display apparatus (Fig 1 display device 1, [0060]), comprising the display panel (Fig 1 display panel 10, [0061]) according to claim 19.
Claims 6-10, 12, and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et. al. (US 20230329050 A1), hereinafter Choi, in view of Park et. al. (US 20220115480 A1), hereinafter Park.
Regarding claim 6, Choi as modified in claim 1 teaches the plurality of first light-emitting devices (Fig 6 light-emitting elements LE, [0079]) comprise device row groups (Fig 2 row groups of light-emitting elements LE) arranged in sequence in a first direction (Fig 2 downward DR2 direction), and each of the device row groups (Fig 2 row groups of light-emitting elements LE) comprises a first device row (Fig 9B top row containing L2c and L2a), a second device row (Fig 9B second row below first row containing L2b), a third device row (Fig 9B third row below second row containing L2a and L2c) and a fourth device row (Fig 9B fourth row below third row containing L2d) arranged in sequence in the first direction (Fig 9B downward DR2 direction); the first device row (Fig 9B top row containing L2c and L2a) and the third device row (Fig 9B third row below second row containing L2a and L2c) each comprise first sub-light-emitting devices (Fig 9B color light-emitting element L2a, [0161]) and second sub-light-emitting devices (Fig 9B color light-emitting element L2c, [0161]) arranged alternately (Examiner notes Fig9B shows two instances of L2a in the top row but [0161] teaches L2a and L2c are adjacent to each other in the DR2 direction; Examiner reads this to mean the right most instance of L2a should be L2c) in sequence in a second direction (Fig 9B DR1), a color of light emitted ([0157] teaches Fig9B is an arrangement of the light-emitting elements of Fig9A; Examiner confers the colors from Fig9A to that of Fig 9B; that is L1a=L2a; thus the color of L2a is red,[0160]) from the first sub-light-emitting devices (Fig 9B color light-emitting element L2a, [0161]) is different from a color of light emitted (blue, [0160]) from the second sub-light-emitting devices (Fig 9B color light-emitting element L2c, [0161]); and the second device row (Fig 9B second row below first row containing L2b) and the fourth device row (Fig 9B fourth row below third row containing L2d) each comprise third sub-light-emitting devices (Fig 9B color light-emitting element L2b, [0161]) and fourth sub-light-emitting devices (Fig 9B color light-emitting element L2d, [0161]) arranged in the second direction (Fig 9B DR1), and a color of light emitted from the third sub- light-emitting devices (Fig 9B color light-emitting element L2b, [0161]) is the same as a color (L1b and L1d emit the green, [0160]) of light emitted from the fourth sub-light-emitting devices (Fig 9B color light-emitting element L2d, [0161]); in the same device row group (Fig 2 row groups of light-emitting elements LE same as row groups in Fig 9B), a first row gap (See annotated figure) is between the first device row (Fig 9B top row containing L2c and L2a) and the second device row (Fig 9B second row below first row containing L2b), and a second row gap (See annotated figure) is between the third device row (Fig 9B third row below second row containing L2a and L2c) and the fourth device row (Fig 9B fourth row below third row containing L2d);
Choi as modified in claim 1 additionally teach the second device row and the fourth device row each comprise third sub-light-emitting devices and fourth sub-light-emitting devices arranged alternately in sequence in the second direction.
Choi as modified in claim 1 fails to teach the first groups of holes and second groups of holes configured to connect all the first light-emitting devices in the first device row as well as first groups of holes and second groups of holes configured to connect all the first light-emitting devices in the second device row are all in the first row gap and are arranged in a direction parallel to the second direction; and first groups of holes and second groups of holes configured to connect all the first light-emitting devices in the third device row as well as first groups of holes and second groups of holes configured to connect all the first light-emitting devices in the fourth device row are all located in the second row gap and are arranged in a direction parallel to the second direction.
Regarding the groups of holes. Park teaches first groups of holes (Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132] corresponds Choi: Fig 6 group consisting of hole for pixel electrode 171 and hole for bridge electrode BE1) and second groups of holes (Fig 11 contact hole 117, [0109] corresponds Choi: Fig 6 group consisting of hole for bridge electrode BE2 and hole for drain electrode D1) configured to connect all the first light-emitting devices (Fig 10 area with emission layer 121a and not labeled emission layer for PE3 corresponds to Choi: Fig 6 light-emitting elements LE, [0079]) in the first device row (Fig 10 row with big emission areas corresponds to Choi: Fig 9B top row containing L2c and L2a) as well as first groups of holes (Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132] corresponds Choi: Fig 6 group consisting of hole for pixel electrode 171 and hole for bridge electrode BE1) and second groups of holes (Fig 11 contact hole 117, [0109] corresponds Choi: Fig 6 group consisting of hole for bridge electrode BE2 and hole for drain electrode D1) configured to connect all the first light-emitting devices (Fig 10 area with emission layer 121a and not labeled emission layer for PE3 corresponds to Choi: Fig 6 light-emitting elements LE, [0079]) in the second device row (Fig 10 row with small emission areas corresponds to Choi: Fig 9B top row containing L2c and L2a) are all in the first row gap (Fig 10 row with IL4 corresponds to Choi: See annotated figure) and are arranged in a direction parallel to the second direction (Fig 10 X- direction corresponds to Choi: Fig 9B DR1); and first groups of holes (Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132] corresponds Choi: Fig 6 group consisting of hole for pixel electrode 171 and hole for bridge electrode BE1) and second groups of holes (Fig 11 contact hole 117, [0109] corresponds Choi: Fig 6 group consisting of hole for bridge electrode BE2 and hole for drain electrode D1) configured to connect all the first light-emitting devices (Fig 10 area with emission layer 121a and not labeled emission layer for PE3 corresponds to Choi: Fig 6 light-emitting elements LE, [0079]) in the third device row (Fig 10 row with big emission areas corresponds to Choi: Fig 9B third row below second row containing L2a and L2c) as well as first groups of holes (Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132] corresponds Choi: Fig 6 group consisting of hole for pixel electrode 171 and hole for bridge electrode BE1) and second groups of holes (Fig 11 contact hole 117, [0109] corresponds Choi: Fig 6 group consisting of hole for bridge electrode BE2 and hole for drain electrode D1) configured to connect all the first light-emitting devices (Fig 10 area with emission layer 121a and not labeled emission layer for PE3 corresponds to Choi: Fig 6 light-emitting elements LE, [0079]) in the fourth device row (Fig 10 row with big emission areas corresponds to Choi: Fig 9B fourth row below third row containing L2d) are all located in the second row gap (Fig 10 a different row with IL4 corresponds to Choi: See annotated figure) and are arranged in a direction parallel to the second direction (Fig 10 X- direction corresponds to Choi: Fig 9B DR1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified Choi to incorporate the teachings of Park by having groups of holes in a particular arrangement. This would aid in providing a high quality image by having an optimal pixel arrangement ([0028]).
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Regarding claim 7, the closest art is Choi et. al. (US 20230329050 A1), hereinafter Choi, in view of Park et. al. (US 20220115480 A1), hereinafter Park.
Choi and Park fail to teach the first row gap, spacing between centers of at least two adjacent second groups of holes in all the second groups of holes configured to connect the first electrodes is different; and in the second row gap, spacing between centers of at least two adjacent second groups of holes in all the second groups of holes configured to connect the first electrodes is different.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that due to manufacturing differences the spacing between the between centers of at least two adjacent groups of holes would be different.
Regarding claim 8, the closest art is Choi et. al. (US 20230329050 A1), hereinafter Choi, in view of Park et. al. (US 20220115480 A1), hereinafter Park.
Choi and Park fail to teach the first row gap, a ratio of spacing between centers of at least two adjacent first groups of holes in all the first groups of holes configured to connect the first electrodes is in a range of 0.8-1.2; and in the second row gap, a ratio of spacing between centers of at least two adjacent first groups of holes in all the first groups of holes configured to connect the first electrodes is in a range of 0.8-1.2.
However, one having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to try to get the ideal spacing between centers of at least two adjacent groups of holes, ideally a ratio of 1. Differences in manufacturing would prevent every ratio of spacing between centers of at least two adjacent second groups of holes from being 1, but would be within an achievable range of tolerance close to 1, such as 0.8-1.2.
Regarding claim 9, the closest art is Choi et. al. (US 20230329050 A1), hereinafter Choi, in view of Park et. al. (US 20220115480 A1), hereinafter Park.
Choi and Park fail to teach spacing between centers of at least two adjacent second groups of holes in the first row gap is different from spacing between centers of at least two adjacent second groups of holes in the second row gap.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that due to manufacturing differences the spacing between the between centers of at least two adjacent groups of holes would be different.
Regarding claim 10, Choi as modified in claim 6 teaches in the first row gap (Park: Fig 10 gap with IL4), second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the third sub-light- emitting devices (Park: Fig 10 left pixel with VIA2), second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the first sub-light-emitting devices (Park: Fig 10 pixel with VIA3), second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the fourth sub-light-emitting devices (Park: Fig 10 right pixel with VIA2) and second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the second sub-light-emitting devices (Park: Fig 10 pixel with VIA1) are arranged in cycles in sequence (Park: Fig 10) in the second direction (Park: Fig 10 X direction).
Regarding claim 12, Choi as modified in claim 6 teaches in the second row gap (Fig 10 a different row with IL4 corresponds to Choi: See annotated figure), second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the third sub-light- emitting devices (Park: Fig 10 left pixel with VIA2), second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the first sub-light-emitting devices (Park: Fig 10 pixel with VIA3), second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the fourth sub-light-emitting devices (Park: Fig 10 right pixel with VIA2) and second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the second sub-light-emitting devices (Park: Fig 10 pixel with VIA1) are arranged in cycles in sequence (Park: Fig 10) in the second direction (Park: Fig 10 X direction).
Regarding claim 14, Choi as modified in claim 6 teaches a plurality of first electrodes (Park: Fig 10 pixel electrodes PE1, PE2, PE3, [0142] corresponds to Choi: Fig 6 pixel electrode 171, [0140]) of the plurality of first light-emitting devices (Park: Fig 10 not labeled light emitting elements corresponding to PE1, PE2, and PE3 corresponds to Choi: Fig 6 light-emitting elements LE, [0079]) comprise first electrode cell rows (Park: See annotated figure) and second electrode cell rows (Park: See annotated figure) arranged in sequence in the first direction (Park: Fig 10 y direction); the first electrode cell rows (Park: See annotated figure) comprise a plurality of first electrode cells (Park: See annotated figure) arranged in sequence in the second direction (Park: Fig 10 x direction), and the second electrode cell rows (Park: See annotated figure) comprises a plurality of second electrode cells (Park: See annotated figure) arranged in sequence in the second direction (Park: Fig 10 x direction); and the first electrode cell (Park: See annotated figure) and the second electrode cell (Park: See annotated figure) each comprise a first sub-electrode (Park: See annotated figure; PE3) and a second sub-electrode (Park: See annotated figure; PE1) arranged in the first direction (Park: Fig 10 y direction), and a third sub-electrode (Park: See annotated figure; left PE2) and a fourth sub- electrode (Park: See annotated figure; right PE2) arranged in the second direction (Park: Fig 10 x direction).
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Regarding claim 15, Choi as modified in claim 14 teaches the first electrode cell (Park: See annotated figure; Examiner will be using the second electrode cell for the limitations of the claim, as the components are more clearly illustrated) comprises a first edge parallel (Park: See annotated figure) to a long edge of the third sub-electrode (Park: See annotated figure; left PE2) and comprises a second edge parallel (Park: See annotated figure) to a long edge of the fourth sub-electrode (Park: See annotated figure; right PE2); in the first electrode cell, the third sub-electrode (Park: See annotated figure; left PE2) comprises: a third sub-electrode body (Park: Fig 10 first region 123b for left PE2, [0134]) and a third sub-electrode switch-over portion (Park: Fig 10 second region 125b for left PE2, [0134]) extending from the third sub-electrode body (Park: Fig 10 first region 123b for left PE2, [0134]) towards one side away from the second sub-electrode (Park: See annotated figure; PE1); and an orthographic projection of second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the third sub-light-emitting devices (Park: left PE2 pixel corresponds to Choi: Fig 9B color light-emitting element L2b, [0161]) on the base substrate (Park: Fig 12 substrate 100, [0060] corresponds to Choi: Fig 6 substrate SUB, [0079]) and an orthographic projection of the third sub-electrode switch- over portion (Park: Fig 10 second region 125b for left PE2, [0134]) on the base substrate (Park: Fig 12 substrate 100, [0060] corresponds to Choi: Fig 6 substrate SUB, [0079]) have an overlapping region (Park: Fig 10 the VIA overlaps the second region 125b).
Choi as modified in claim 14 fails to teach a third sub-electrode switch-over portion extending from the third sub-electrode body towards one side away from the second sub-electrode in a direction perpendicular to the first edge.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have rearranged the location of the third sub-electrode switch-over portion extension such that a third sub-electrode switch-over portion extends from the third sub-electrode body towards one side away from the second sub-electrode in a direction perpendicular to the first edge, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. MPEP 2144.04 (VI)(C)
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Regarding claim 16, Choi as modified in claim 15 teaches in the first electrode cell (Park: See annotated figure of claim 15; Examiner will be using the second electrode cell for the limitations of the claim, as the components are more clearly illustrated), the fourth sub-electrode (Park: See annotated figure of claim 15; right PE2) comprises: a fourth sub-electrode body (Park: Fig 10 first region 123b for right PE2, [0134]) and a fourth sub-electrode switch- over portion (Park: Fig 10 second region 125b for right PE2, [0134]) extending from the fourth sub-electrode body (Park: Fig 10 first region 123b for right PE2, [0134]) towards one side away from the second sub-electrode (Park: See annotated figure of claim 15; PE1); and an orthographic projection of second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the fourth sub-light- emitting devices (Park: right PE2 pixel corresponds to Choi: Fig 9B color light-emitting element L2b, [0161]) on the base substrate (Park: Fig 12 substrate 100, [0060] corresponds to Choi: Fig 6 substrate SUB, [0079]); and an orthographic projection of the fourth sub-electrode switch-over portion (Park: Fig 10 second region 125b for right PE2, [0134]) on the base substrate (Park: Fig 12 substrate 100, [0060] corresponds to Choi: Fig 6 substrate SUB, [0079]) have an overlapping region (Park: Fig 10 the VIA overlaps the second region 125b).
Choi as modified in claim 14 fails to teach a fourth sub-electrode switch- over portion extending from the fourth sub-electrode body towards one side away from the second sub-electrode in a direction perpendicular to the second edge.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have rearranged the location of the fourth sub-electrode switch-over portion extension such that a fourth sub-electrode switch-over portion extends from the fourth sub-electrode body towards one side away from the second sub-electrode in a direction perpendicular to the second edge, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. MPEP 2144.04 (VI)(C)
Regarding claim 17, Choi as modified in claim 14 teaches the second electrode cell (Park: See annotated figure) comprises a third edge parallel (Park: See annotated figure) to a long edge of the third sub- electrode (Park: See annotated figure; left PE2) and comprises a fourth edge parallel (Park: See annotated figure)to a long edge of the fourth sub-electrode (Park: See annotated figure; right PE2); in the second electrode cell (Park: See annotated figure), the third sub-electrode (Park: See annotated figure; left PE2) comprises: a third sub-electrode body (Park: Fig 10 first region 123b for left PE2, [0134]) and a third sub-electrode body (Park: Fig 10 first region 123b for left PE2, [0134]) and a third sub-electrode switch-over portion (Park: Fig 10 second region 125b for left PE2, [0134]) extending from the third sub-electrode body (Park: Fig 10 first region 123b for left PE2, [0134]) towards one side away from the second sub-electrode (Park: See annotated figure; PE1); and an orthographic projection of second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the third sub-light-emitting devices (Park: left PE2 pixel corresponds to Choi: Fig 9B color light-emitting element L2b, [0161]) on the base substrate (Park: Fig 12 substrate 100, [0060] corresponds to Choi: Fig 6 substrate SUB, [0079]) and an orthographic projection of the third sub-electrode switch- over portion (Park: Fig 10 second region 125b for left PE2, [0134]) on the base substrate (Park: Fig 12 substrate 100, [0060] corresponds to Choi: Fig 6 substrate SUB, [0079]) have an overlapping region (Park: Fig 10 the VIA overlaps the second region 125b).
Choi as modified in claim 14 fails to teach a third sub-electrode switch-over portion extending from the third sub-electrode body towards one side away from the second sub-electrode in a direction perpendicular to the third edge.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have rearranged the location of the third sub-electrode switch-over portion extension such that a third sub-electrode switch-over portion extends from the third sub-electrode body towards one side away from the second sub-electrode in a direction perpendicular to the third edge, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. MPEP 2144.04 (VI)(C)
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Regarding claim 18, Choi as modified in claim 17 teaches in each second electrode cell (Park: See annotated figure of claim 17), the fourth sub-electrode (Park: See annotated figure of claim 17; right PE2) comprises: a fourth sub-electrode body (Park: Fig 10 first region 123b for right PE2, [0134]) and a fourth sub-electrode switch- over portion (Park: Fig 10 second region 125b for right PE2, [0134]) extending from the fourth sub-electrode body (Park: Fig 10 first region 123b for right PE2, [0134]) towards the first sub-electrode (Park: See annotated figure of claim 17; PE3); and an orthographic projection of second groups of holes (Park: Fig 10 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) configured to connect the fourth sub-light- emitting devices (Park: right PE2 pixel corresponds to Choi: Fig 9B color light-emitting element L2b, [0161]) on the base substrate (Park: Fig 12 substrate 100, [0060] corresponds to Choi: Fig 6 substrate SUB, [0079]) and an orthographic projection of the fourth sub-electrode switch-over portion (Park: Fig 10 second region 125b for right PE2, [0134]) on the base substrate (Park: Fig 12 substrate 100, [0060] corresponds to Choi: Fig 6 substrate SUB, [0079]) have an overlapping region (Park: Fig 10 the VIA overlaps the second region 125b).
Choi as modified in claim 17 fails to teach a fourth sub-electrode switch- over portion extending from the fourth sub-electrode body towards one side close to the first sub-electrode in a direction parallel to the fourth edge.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have rearranged the location of the fourth sub-electrode switch-over portion extension such that a fourth sub-electrode switch- over portion extends from the fourth sub-electrode body towards one side close to the first sub-electrode in a direction parallel to the fourth edge, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. MPEP 2144.04 (VI)(C)
Allowable Subject Matter
Claims 4, 11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, Choi as modified in claim 1 teaches a fourth conductive layer (Fig 6 portion of D1 on layer 141) on one side of (Examiner interprets this limitation to mean the fourth conductive layer is on the bottom side of layer 142 but not necessarily between the layers 141 and 142; an example being a multilayer cake wherein the icing on the outside is on one side of the top most cake layer facing the table) the first flat layer (Fig 6 dielectric layer 142, [0130]) facing the base substrate (Fig 6 substrate SUB, [0079]); a fifth flat layer (Fig 6 interlayer dielectric layer 141, [0130]) on one side of the fourth conductive layer (Fig 6 portion of D1 on layer 141) facing the base substrate (Fig 6 substrate SUB, [0079]) away from (Fig 6 lower side of 151) the second flat layer (Fig 6 planarization layer 151, [0132]) wherein the fifth flat layer comprises: a fifth via hole (See annotated figure) penetrating through the fifth flat layer (Fig 6 Examiner considers interlayer dielectric layer , [0130]); the first pixel circuit (Fig 6 layer containing transistors, such as TFT2) is electrically connected with the first electrode (Fig 6 pixel electrode 171, [0140]) via the fourth conductive layer (Fig 6 portion of D1 on layer 141) passing through the fifth via hole (See annotated figure), the first conductive layer (Fig 6 portion of electrode D1 on layer 142) passing through the first via hole (See annotated figure), the second conductive layer (Fig 6 portion of electrode BE1 on layer 151) passing through the second via hole (See annotated figure), and the third conductive layer (Fig 6 portion of electrode BE2 on layer 152) passing through the third via hole (See annotated figure) in sequence;
Choi fails to teach an orthographic projection of the fifth via hole on the base substrate and the orthographic projection of the second group of holes on the base substrate have an overlapping region.
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Regarding claim 11, the closest art is Choi et. al. (US 20230329050 A1), hereinafter Choi, in view of Park et. al. (US 20220115480 A1), hereinafter Park.
Choi as modified by Park teaches in an arrangement cycle of the first row gap (Park: Fig 10 gap with IL4), first groups of holes (Park: Fig 11 contact hole 117, [0109]) of the third sub-light-emitting devices (Park: Fig 11 with VIA2) are on one side (Park: Fig 11 contact hole 117 is below VIA2) of the second groups of holes (Park: Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) of the third sub-light-emitting devices (Park: Fig 11 pixel with VIA2) away from (Park: Fig 11) the second groups of holes (Park: Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) of the first sub-light-emitting devices (Park: Fig 11 pixel with VIA3); and first groups of holes (Park: Fig 11 contact hole 117, [0109]) of the second sub-light-emitting devices (Park: Fig 11 pixel with VIA1) are on one side of the first groups of holes (Park: Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) of the second sub-light-emitting devices (Park: Fig 11 pixel with VIA1) away from the second groups of holes (Park: Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) of the fourth sub-light-emitting devices (Park: Fig 11 not shown would correspond with Fig 10 other pixel with VIA2).
Choi and Park fail to teach first groups of holes of the first sub-light-emitting devices are between the second groups of holes of the first sub-light-emitting devices and the second groups of holes of the third sub-light- emitting devices; first groups of holes of the fourth sub-light-emitting devices are between the second groups of holes of the first sub-light-emitting devices and the second groups of holes of the fourth sub-light- emitting devices.
Regarding claim 13, the closest art is Choi et. al. (US 20230329050 A1), hereinafter Choi, in view of Park et. al. (US 20220115480 A1), hereinafter Park.
Choi as modified by Park teaches in an arrangement cycle of the second row gap (Park: Fig 10 gap with IL4), first groups of holes (Park: Fig 11 contact hole 117, [0109]) of the third sub-light-emitting devices (Park: Fig 11 with VIA2) are located on one side (Park: Fig 11 contact hole 117 is below VIA2) of the second groups of holes (Park: Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) of the third sub-light-emitting devices (Park: Fig 11 pixel with VIA2) away from (Park: Fig 11) the second groups of holes (Park: Fig 11 via hole for pixel electrodes VIA1-VIA3, [0130]-[0132]) of the first sub-light-emitting devices (Park: Fig 11 pixel with VIA3);
Choi and Park fail to teach first groups of holes of the first sub-light-emitting devices are between the second groups of holes of the third sub-light-emitting devices and the second groups of holes of the first sub-light-emitting devices; first groups of holes of the fourth sub-light-emitting devices are between the second groups of holes of the first sub-light-emitting devices and the second groups of holes of the fourth sub-light-emitting devices; and first groups of holes of the second sub-light-emitting devices are between the second groups of holes of the fourth sub-light-emitting devices and the second groups of holes of the second sub-light-emitting devices.
Response to Arguments
Applicant's arguments, see 35 USC §103 section beginning with “In Choi…” on page 12, filed June 11, 2026, with respect to the art not teaching overlaps of orthographic projections, have been fully considered but they are not persuasive.
Examiner has addressed the amended limitations pertaining to overlap and the orthographic projections of the via holes in the rejection for claim 1 above.
Regarding the Allowable Subject Matter, Examiner reminds Applicant that only claims 11 and 13 were objected to as being allowable if rewritten in independent form in the Office Action filed March 09, 2026. Claims 7-9 were objected to as being allowable if rewritten in independent form in a prior Office Action filed September 24, 2025. However, those claims were addressed and rejected in the second Non-Final Office Action filed March 09, 2026.
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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