DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/13/26 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-14, 16, 17, and 19 - 22 are rejected under 35 U.S.C. 102 as being anticipated by Wang (US 2024/0046861 A1)
Regarding claim 1, Wang teaches a display substrate ( [0006] the display panel includes a substrate ), comprising first voltage lines ( [0016] a constant high-level voltage metal line ) in a plurality of columns, and a plurality of rows ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) and a plurality of columns of pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) arranged on a base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ); wherein the pixel driving circuit includes a driving transistor ( [0014] the pixel driving circuit layer further includes a second thin film transistor electrically connected with the light-emitting function layer ) and a compensation transistor ( [0006] each of the pixel driving circuits at least includes a compensation transistor ); an orthographic projection of the first voltage line ( [ 0041] a constant high-level voltage metal line disposed on the same layer with the first gate layer ) on the base substrate ( Fig. 6 #10 ) at least partially overlaps an orthographic projection of a gate electrode of the driving transistor ( as discussed above ) on the base substrate ( Fig. 6 #10 ); the gate electrode ( Fig. 6 #32 ) of the driving transistor ( Fig. 6 #30; Fig. 7: driving transistor T1 ) is coupled to a first electrode ( [0096] a first terminal of the compensation transistor 20 is connected to the third node B ) of the compensation transistor ( Fig. 6 #20 ) through a first conductive connection portion ( Fig. 7 node B ) ; a second electrode ( Fig. 7 node E ) of the compensation transistor ( Fig. 6 #20 ) is coupled to a first electrode of the driving transistor ( [0014] the pixel driving circuit layer further includes a second thin film transistor electrically connected with the light-emitting function layer ); an orthographic projection ( [0011] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate) of the first voltage line ( [ 0041] a constant high-level voltage metal line disposed on the same layer with the first gate layer) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate) at least partially overlaps an orthographic projection ( [0011] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate ) of the first conductive connection portion on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) wherein a first gate metal layer ( Fig. 6: first gate layer 32 ) where the gate electrode ( Fig. 6 #32 ) of the driving transistor ( Fig. 6: driving transistor 30 ) is located is on a side of an active layer ( Fig. 6: first semiconductor layer 31 ) where the first electrode of the compensation transistor ( Fig. 6: compensation transistor 20 ) is located, away from the base substrate ( Fig. 6 #10 ); a first source-drain metal layer ( Fig. 6: source/drain layer 34 ) where the first conductive connection portion ( [0017] the first shielding layer is electrically connected with at least one of the first gate and the second gate ) is located is on a side of the first gate metal layer ( Fig. 6 #32 ) where the gate electrode of the driving transistor ( Fig. 6 #30 ) is located, away from the base substrate ( Fig. 6 #10 ); and a second source-drain metal layer ( Fig. 6: source/drain layer #23 ) where the first voltage line ( [0086] a reset metal line VI located between the second gate layer #32 and the second source/drain layer #34 ) is located is on a side of the first source-drain metal layer ( Fig. 1 #34 ) where the first conductive connection portion is located ( [0054] The second thin film transistor 30 is electrically connected with the light-emitting function layer 40 ), away from the base substrate ( Fig. 6 #10 ); the compensation transistor ( Fig. 6 #20 ) comprises a first channel ( Fig. 6 left side #23 ), a second channel ( Fig. 6 right side #23 ), and a first active pattern ( Fig. 6 #21 ) between the first channel ( Fig. 6 left side #23 ) and the second channel ( Fig. 6 right side #23 ), and the orthographic projection of the first conductive connection portion ( Fig. 7 connection between T1 and #23 ) on the base substrate ( Fig. 6 #10 ) at least partially overlaps an orthographic projection ( top of #23 overlaps the orthographic projection of #21 ) of the first active pattern ( Fig. 6 #21 ) on the base substrate ( Fig. 6 #10 ).
Regarding claim 2, Wang teaches the display substrate according to claim 1 (as discussed above), wherein the orthographic projection of the first voltage line lines ( [0016] a constant high-level voltage metal line ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) covers the orthographic projection ( [0011] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate) of the first conductive connection portion ( [0085] the material of the shielding component #50 is an electrical conductive material ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate).
Regarding claim 3, Wang teaches the display substrate according to claim 1 (as discussed above), wherein the orthographic projection of the first voltage line ( [0016] a constant high-level voltage metal line) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) covers an orthographic projection of at least one gate electrode of the compensation transistor ( [0017] an orthogonal projection of the first shielding layer projected on the first semiconductor layer, and the first shielding layer is electrically connected with at least one of the first gate and the second gate ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate).
Regarding claim 4, Wang teaches the display substrate according to claim 1 (as discussed above), wherein the display substrate further comprises first initial voltage lines ( [0097] the first initialization signal VI ) in a plurality of rows ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) arranged on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) ; the pixel driving circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) further includes a first initialization transistor ( [0020] one of the pixel driving circuits includes a first initialization transistor ); a first electrode of the first initialization transistor is coupled to the first initial voltage line ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ) ; the first electrode of the compensation transistor ( [0023] a second terminal of the compensation transistor is connected with the first node ) is coupled to a second electrode of the first initialization transistor ( [ 0024] a second terminal of the first initialization transistor is connected with the first node ); the orthographic projection of the first voltage line ( [0016] a constant high-level voltage metal line ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) at least partially overlaps the orthographic projection ( [0007] an orthogonal projection of the shielding component projected on the substrate at least partially overlays an orthogonal projection of the compensation transistor projected on the substrate ) of the first electrode of the compensation transistor ( [0023] a second terminal of the compensation transistor is connected with the first node ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) ; the orthographic projection ( [0007] an orthogonal projection of the shielding component projected on the substrate at least partially overlays an orthogonal projection of the compensation transistor projected on the substrate) of the first voltage line ( [0016] a constant high-level voltage metal line ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) at least partially overlaps an orthographic projection ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits, and each of the pixel driving circuits at least includes a compensation transistor) of the second electrode of the first initialization transistor ( [0020] one of the pixel driving circuits includes a first initialization transistor ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ).
Regarding claim 5, Wang teaches the display substrate according to claim 4 (as discussed above), wherein the orthographic projection ( [0007] an orthogonal projection of the shielding component projected on the substrate at least partially overlays an orthogonal projection of the compensation transistor projected on the substrate) of the first voltage line ( [0016] a constant high-level voltage metal line ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) covers the orthographic projection ( [0055] The pixel driving circuit further includes a light-emitting unit D1, a first initialization transistor T4) of the first electrode of the compensation transistor ( [0055] a compensation transistor #20 ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ), and the orthographic projection ( [0007] an orthogonal projection of the shielding component projected on the substrate at least partially overlays an orthogonal projection of the compensation transistor projected on the substrate ) of the second electrode of the first initialization transistor ( [ 0024] a second terminal of the first initialization transistor is connected with the first node ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ).
Regarding claim 6, Wang teaches the display substrate according to claim 1 (as discussed above), wherein the pixel driving circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) further comprises a storage capacitor ( [0020] pixel driving circuits drive a first capacitor ) ; the gate electrode ( Fig. 6 #32 ) of the driving transistor ( Fig. 6 #30 ) is multiplexed as a first electrode plate ( [0094] A gate of the driving transistor T1 is connected to the first node Q(E)) of the storage capacitor ( Fig. 7 the first capacitor C1 ); the orthographic projection ( [0036] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate) of the first voltage line ( [0016] a constant high-level voltage metal line) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate) and the orthographic projection ( [0037] an orthogonal projection of the second shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate ) of a second electrode plate of the storage capacitor ( Fig. 7: C1) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) jointly cover the orthographic projection of the gate electrode ( Fig. 6 #32 ) of the driving transistor (Fig. 6 #30 ) on the base substrate ( Fig. 6 #10 ).
Regarding claim 7, Wang teaches the display substrate according to claim 3 (as discussed above), further comprising scan lines ( [0024] a gate of the first initialization transistor is connected to receive a first scan signal ) in a plurality of rows ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) arranged on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) ; wherein the compensation transistor is a double-gate transistor ( [0017] the compensation transistor is a dual-gate structure ), and the compensation transistor includes a first gate electrode ( [0017] the first gate layer includes a first gate ) and a second gate electrode ( [0017] a second gate disposed on a same layer ); the scan line ( [0022] a second scan signal ) includes a first protrusion portion ( Fig. 7: Scan 2 connected to first gate of #20) and a first main portion extending along a first direction ( Fig. 7: Scan 2 connected to second gate of #20) ; the first gate electrode ( [0023] a gate of the compensation transistor is connected to receive the second scan signal ) of the compensation transistor ( Fig. 7 #20 ) and the first main portion form an integral structure ( Fig. 7 Scan 2 connected to the first gate #20 ), and the second gate electrode ( Fig. 7 Scan 2 connected to the second gate of #20) of the compensation transistor ( Fig. 7 #20 ) and the first protrusion portion form an integral structure ( Fig. 7 Scan 2 and the second gate of #20 are connected ); the orthographic projection ( [0017] orthogonal projections of the first gate and the second gate projected on the first semiconductor layer are both located in an orthogonal projection of the first shielding layer projected on the first semiconductor layer ) of the first voltage line ( [0016] a constant high-level voltage metal line ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) covers an orthographic projection ( [0007] an orthogonal projection of the shielding component projected on the substrate at least partially overlays an orthogonal projection of the compensation transistor projected on the substrate) of the first gate electrode of the compensation transistor ( Fig. 7 #20 ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ); the orthographic projection of the first voltage line ( [0016] a constant high-level voltage metal line ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) does not overlap an orthographic projection ( see the reference for the OR part of this claim since only one part needs to be satisfied ) of the second gate electrode ( Fig. 7 #20 second gate electrode ) of the compensation transistor ( Fig. 7 #20 ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ); or, the orthographic projection ( [0036] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate) of the first voltage line ( [0016] a constant high-level voltage metal line) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate) at least partially overlaps the orthographic projection ( [0031] an orthogonal projection of the shielding component projected on the substrate at least partially overlaps an orthogonal projection of the compensation transistor projected on the substrate) of the second gate electrode ( Fig. 7 #20 second gate electrode ) of the compensation transistor ( Fig. 7 #20 ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ).
Regarding claim 8, Wang teaches the display substrate according to claim 7 (as discussed above), wherein the pixel driving circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) further comprises a storage capacitor ( [0020] pixel driving circuits drive a first capacitor ); a second electrode plate of the storage capacitor ( [0028] a second capacitor electrode of the first capacitor is connected with the first node ) has a second protrusion portion ( Fig. 7: Q ), and an orthographic projection ( [ 0067] The pixel driving circuit layer includes a first metal layer #610, a second metal layer #620. The second metal layer #620 includes a second capacitor electrode #33 ) of the second protrusion portion ( Fig. 7: Q ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate) at least partially overlaps an orthographic projection ( [0017] orthogonal projections of the first gate and the second gate projected on the first semiconductor layer are both located in an orthogonal projection of the first shielding layer projected on the first semiconductor layer ) of a first active pattern ( Fig. 7 #20 area between node E and node B ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ).
Regarding claim 9, Wang teaches the display substrate according to claim 1 ( as discussed above), wherein an orthographic projection ( [0007] an orthogonal projection of the shielding component projected on the substrate at least partially overlays an orthogonal projection of the compensation transistor projected on the substrate ) of at least one channel of the compensation transistor ( Fig. 7 #20) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) at least partially overlaps an orthographic projection ( [0011] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate) of the first conductive connection portion ( [0085] the material of the shielding component #50 is an electrical conductive material ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ).
Regarding claim 10, Wang teaches the display substrate according to claim 1 ( as discussed above), wherein the orthographic projection ( [0036] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate) of the first voltage line ( [0016] a constant high-level voltage metal line) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) covers an orthographic projection ( [0007] an orthogonal projection of the shielding component projected on the substrate at least partially overlays an orthogonal projection of the compensation transistor projected on the substrate ) of at least one channel of the compensation transistor ( Fig. 7 #20) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) ; a part of the first voltage line ( [0016] a constant high-level voltage metal line ) covering the first conductive connection portion ( [0085] the material of the shielding component #50 is an electrical conductive material ) and a part of the first voltage line ( 0016] a constant high-level voltage metal line ) covering at least one channel of the compensation transistor ( Fig. 7 #20 ) form an integral structure ( [0032] a shielding component disposed between the substrate and the compensation transistor ).
Regarding claim 11, Wang teaches the display substrate according to claim 1 ( as discussed above), wherein the first conductive connection portion ( [0085] the material of the shielding component #50 is an electrical conductive material ) is coupled ( [0032] a shielding component disposed between the substrate and the compensation transistor) to the first electrode of the compensation transistor ( Fig. 7 #20) through a connection via hole ( [ 0023] a first terminal of the compensation transistor is connected with the third node); an orthographic projection ( [0017] orthogonal projections of the first gate and the second gate projected on the first semiconductor layer ) of the connecting via hole ( [0023] a first terminal ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate) is located on a side of the gate electrode ( Fig. 7 gate of #20 ) of the compensation transistor ( Fig. 7 #20 ) away from a channel of the driving transistor ( Fig. 7 a driving transistor #T1).
Regarding claim 12, Wang teaches the display substrate according to claim 8 ( as discussed above), further comprising includes first initial voltage line ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ) in a plurality of rows ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) and data lines ( Fig. 7 Data ) in a plurality columns ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) arranged on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ); wherein the first initial voltage line ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ) includes a third a protrusion portion ( Fig. 7 initialization transistor T4 first gate) and a second main portion extending along a first direction ( Fig. 7 initialization transistor T4 second gate); an orthographic projection ( [0103] The shielding component #50 is located between the substrate and at least one of the first initialization transistor #T4 ) of the third protrusion portion ( Fig. 7: T4 ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) is located between an orthographic projection ( [0007] an orthogonal projection of the shielding component projected on the substrate at least partially overlaps an orthogonal projection of the compensation transistor projected on the substrate ) of the data line ( Fig. 7: Data ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) and an orthographic projection ( [0036] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate ) of the first conductive connection portion ( [0085] the material of the shielding component #50 is an electrical conductive material ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate).
Regarding claim 13, Wang teaches the display substrate according to claim 1 (as discussed above), further comprising first initial voltage lines ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ) in a plurality of rows ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ), second initial voltage ( [0020] a second initialization transistor) lines in a plurality of rows ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ), and reset control lines ( [0016] the display panel further includes a reset metal line) in a plurality of rows ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) arranged on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ); wherein a current pixel driving circuit ( [0006] pixel driving circuit ) is respectively coupled ( [0020] one of the pixel driving circuits includes a first initialization transistor ) to a first initial voltage line ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ) in a current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ), a second initial voltage line ( [0020] a second initialization transistor ) in the current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) and a reset control line ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer ) in the current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ); a pixel driving circuit ( [0006] pixel driving circuit ) of a previous adjacent row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) is respectively coupled to a first initial voltage line ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ) in the previous adjacent row ( [0108] The pixel driving circuit layer includes a plurality of pixel driving circuits, and each of the pixel driving circuits at least includes a compensation transistor ), the second initial voltage line ( [0020] a second initialization transistor ) in the previous adjacent row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) and the reset control line ( [ 0016] the display panel further includes a reset metal line ) in the previous adjacent row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ); an orthographic projection ( [ 0057] an orthogonal projection of the shielding component #50 projected on the substrate #10 at least partially overlaps an orthogonal projection of the compensation transistor #20 projected on the substrate #10 ) of the second initial voltage line ( [0020] a second initialization transistor ) in the previous adjacent row ( 0006] The pixel driving circuit layer includes a plurality of pixel driving circuits) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ), an orthographic projection ( [0017] orthogonal projections of the first gate and second gate projected on the first semiconductor layer ) of the reset control line ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer ) in the current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ), and an orthographic projection ( [0017] orthogonal projections of the first gate and the second gate projected on the first semiconductor layer ) of the first initial voltage line ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ) in the current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) on the base substrate ( [0006] a pixel driving circuit layer disposed on the substrate ) are arranged in sequence along a second direction ( Fig. 7 Scan 1 connected to T4 is in a second direction from Scan 2 connected to #20 ); the second initial voltage line ( [0020] a second initialization transistor ) is located on a same layer ( [0093] The pixel driving circuit includes a first initialization transistor T4, a switching transistor T2, a driving transistor T1, a compensation transistor #20, a second initialization transistor T7 ) as the first initial voltage line ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ), and the reset control line ( [ 0016] the display panel further includes a reset metal line) is located on a different layer ( [0086] a reset metal line VI located between the second gate layer #32 and the second source/drain layer #34 ) from the second initial voltage line ( [0020] a second initialization transistor ).
Regarding claim 14, Wang teaches the display substrate according to claim 1 (as discussed above), further comprising light emitting control lines ( [0025] a light-emitting control signal ) in a plurality of rows ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) arranged on the base substrate ( Fig. 3A a substrate #10 ) ; wherein the pixel driving circuit ( [0020] the pixel driving circuits ) further comprises a first light emitting control transistor ( [0020] pixel driving circuits includes a first initialization transistor, a switching transistor, a driving transistor, the compensation transistor, a second initialization transistor, a first light-emitting control transistor ) and a second light emitting control transistor ( [0020] a second light-emitting control transistor ) ; a gate electrode of the first light emitting control transistor ( [0025] a gate of the first light-emitting control transistor), a gate electrode of the second light emitting control transistor ( [0026] a gate of the second light-emitting control transistor is connected to receive the light-emitting control signal ) and the light emitting control line form an integral structure ( [0025] connected to receive a light-emitting control signal); a first electrode of the first light emitting control transistor ( [0025] a first terminal of the first light-emitting control transistor is connected with a fifth node) is coupled to the first voltage line ( [0025] the first light-emitting control transistor is connected to receive a high-potential power signal through the fifth node ), and a second electrode of the first light emitting control transistor ( [0025] a second terminal of the first light-emitting control transistor is connected with the second node) is coupled to the second electrode of the driving transistor ( [0021] a second terminal of the driving transistor is connected with a second node); a first electrode of the second light emitting control transistor ( [0026] a first terminal of the second light-emitting control transistor is connected with the third node ) is coupled to the first electrode of the driving transistor ( [0021] a first terminal of the driving transistor is connected with a third node ), and a second electrode of the second light emitting control transistor ( [0026] a second terminal of the second light-emitting control transistor is connected with a fourth node ) is coupled to an anode of a corresponding light emitting element ( [0026] a second terminal of the second light-emitting control transistor is connected with a fourth node ), wherein the display substrate further comprises second initial voltage lines ( [0027] a second terminal of the second initialization transistor is connected to receive the first initialization signal ) in a plurality of rows ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits) and data lines ( Fig. 7 Data ) in a plurality columns ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) arranged on the base substrate ( Fig. 3A a substrate #10 ); both a first distance ( Fig. 7 electrodes of the first light emitting control transistor T5 and second initial voltage line T7 shortest distance passes through two transistors T1 and T6) and a second distance ( Fig. 7 second light emitting control transistor T6 and the anode of light emitting element Node C) are greater than a line width of the data line ( Fig. 7: Data signal only passes through T2 to get to Node A) ; the first distance is a shortest distance between an orthographic projection ( [0036] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate ) of electrodes of the first light emitting control transistor ( [0025] a first terminal of the first light-emitting control transistor) on the base substrate ( Fig. 3A a substrate #10 ) and an orthographic projection ( [0036] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate ) of the second initial voltage line ( [0027] a second terminal of the second initialization transistor is connected to receive the first initialization signal) on the base substrate ( Fig. 3A #10) ; the electrodes of the first light emitting control transistor ( [0020] pixel driving circuits includes a first initialization transistor, a switching transistor, a driving transistor, the compensation transistor, a second initialization transistor, a first light-emitting control transistor ) include a first electrode of the first light emitting control transistor ( [0025] a first terminal of the first light-emitting control transistor is connected with a fifth node) and a second electrode of the first light emitting control transistor ( [0025] a second terminal of the first light-emitting control transistor is connected with the second node) ; the second distance is a shortest distance between an orthographic projection ( [0036] an orthogonal projection of the first shielding layer projected on the substrate covers an orthogonal projection of the first semiconductor layer projected on the substrate ) of a coupling portion ( [0026] a second terminal of the second light-emitting control transistor is connected with a fourth node; Fig. 7: Node C) between electrodes of the second light emitting control transistor ( [0020] a second light-emitting control transistor ) and the anode of the corresponding light emitting element ( [0026] a second terminal of the second light-emitting control transistor is connected with a fourth node; Fig. 7 Node C ) on the base substrate ( Fig. 3A #10 ) and the orthographic projection of the second initial voltage ( [0027] a second terminal of the second initialization transistor is connected to receive the first initialization signal ) line on the base substrate ( Fig. 3A #10).
Regarding claim 16, Wang teaches the display substrate according to claim 1 (as discussed above), further comprising scan lines in a plurality of rows ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits), first initial voltage lines ( [0024] a first terminal of the first initialization transistor is connected to receive a first initialization signal ) in a plurality of rows ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits), second initial voltage lines ( [0027] a second terminal of the second initialization transistor is connected to receive the first initialization signal ) in a plurality of rows ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ), and data lines ( Fig. 7 Data ) in a plurality columns ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) arranged on the base substrate ( Fig. 3A #10 ) ; wherein the pixel driving circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) further includes a data writing-in transistor ( Fig. 7: T2 ), a second initialization transistor ( Fig. 7: T7 ) and a second light emitting control transistor ( [0020] a second light-emitting control transistor ); a gate electrode of the data writing-in transistor ( Fig. 7: Scan 2) and a scanning line ( Fig. 7: Scan 2) in a current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) form an integral structure (Fig. 7 same signal for both), a first electrode of the data writing-in transistor is coupled to the data line ( Fig. 7 Data), a second electrode of the data writing-in transistor is coupled to the second electrode of the driving transistor ( Fig. 7 second electrode of T2 is connected to Node A) ; a gate electrode of the second initialization transistor ( [0027] a gate of the second initialization transistor is connected to receive the second scan signal ) is coupled to a reset control line ( [ 0016] the display panel further includes a reset metal line ) in a next adjacent row ( [0016] where in one terminal of the bridge component is disposed on the same layer with and electrically connected with one of the reset metal lines ) , a first electrode of the second initialization transistor ( [0027] a first terminal of the second initialization transistor) is coupled to a second initial voltage ( [0027] a second terminal of the second initialization transistor is connected to receive the first initialization signal ) line in a current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ), and a second electrode of the second initialization transistor ( [0027] a second terminal of the second initialization transistor is connected to receive the first initialization signal; Fig. 7: T7 ) is coupled to the second electrode of the second light emitting control transistor ( [0026] a second terminal of the second light-emitting control transistor is connected with a fourth node; Fig. 7 : T6 connects to T7 through Node C ); the scanning line ( Fig. 7 Scan 1 connected to T7 gate ) in the current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ), the light emitting control line ( [0025] a light-emitting control signal ) in the current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) , the second initial voltage line in the current row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) and the reset control line ( [ 0016] the display panel further includes a reset metal line ) in the next adjacent row ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) are arranged in sequence along a second direction ( [0020] the display panel further includes a plurality of light-emitting units disposed in an array ).
Regarding claim 17, Wang teaches the display substrate according to claim 1 (as discussed above), wherein the display substrate includes a camera area ( [0002] At present, in the field of flat panel displays, such as mobile phones, PDAs, and digital cameras, OLED displays have begun to replace the conventional liquid crystal displays (LCD)) and a first transition area ( [0086] a bridge component located in a non-display area ) ; at least part of pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) in the plurality of rows ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) and the plurality of columns of pixel driving circuits ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) are arranged in the first transition area ( [0086] a bridge component located in a non-display area ); the at least part of pixel driving circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) includes pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) corresponding to the camera area ( [0002] At present, in the field of flat panel displays, such as mobile phones, PDAs, and digital cameras, OLED displays have begun to replace the conventional liquid crystal displays (LCD) and pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) corresponding to the first transition area ( [0086] a bridge component located in a non-display area ); the pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) corresponding to the camera area ( [0002] At present, in the field of flat panel displays, such as mobile phones, PDAs, and digital cameras, OLED displays have begun to replace the conventional liquid crystal displays (LCD)) are respectively coupled to an anode patterns arranged in the camera area through connection lines ( [0015] the light-emitting function layer includes an anode) ; the pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) corresponding to the first transition area ( [0086] a bridge component located in a non-display area ) are coupled to an anode pattern arranged in the first transition area ( [0086] a bridge component located in a non-display area ), wherein the display substrate ( Fig. 3A #10) further comprises a second transition area ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer ) and a normal display area ( [0014] the light-emitting function layer ); at least part of the pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) included in the plurality of rows and the plurality of columns ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) of pixel driving circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) are arranged in the normal display area ( [0014] the light-emitting function layer ), at least part of pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) included in the plurality of rows and the plurality of columns ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) of pixel driving circuits are arranged in the second transition area; the part of the pixel driving circuits ( [0020] the pixel driving circuits drive the light-emitting units ) to emit light arranged in the normal display area ( [0014] the light-emitting function layer ) are coupled to an anode pattern arranged in the normal display area ( [0086] a bridge component located in a non-display area ), and the part of the pixel driving circuits arranged in the second transition area ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer ) are coupled to an anode pattern ( [0015] the second source/drain layer is electrically connected with the anode) arranged in the second transition area ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer ).
Regarding claim 19, Wang teaches the display substrate according to claim 3 (as discussed above), further comprising scanning lines in a plurality of rows ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ) and data lines ( Fig. 7 Data ) in a plurality columns ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) arranged on the base substrate ( Fig. 3A #10); wherein the pixel circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) is electrically connected to a data line ( Fig. 7 Data ) in a row ( [0006] The pixel driving circuit layer includes a plurality of pixel driving circuits ); the compensation transistor is a double-gate transistor ( [0017] the compensation transistor is a dual-gate structure ), and the compensation transistor ( Fig. 7 #20 ) includes a first gate electrode and a second gate electrode (Fig. 7 #20 has two gate electrodes) , and a first active pattern ( Fig. 7 #20 area between node E and node B ) arranged between a first channel of the compensation transistor ( Fig. 7 #20 left gate) and a second channel of the compensation transistor ( Fig. 7 #20 right gate ); the orthographic projection ( [0017] orthogonal projections of the first gate and the second gate projected on the first semiconductor layer are both located in an orthogonal projection of the first shielding layer projected on the first semiconductor layer ) of the first active pattern ( Fig. 7 #20 area between node E and node B ) on the base substrate (Fig. 3A #10) is located between an orthographic projection ( [0017] orthogonal projections of the first gate and the second gate projected on the first semiconductor layer are both located in an orthogonal projection of the first shielding layer projected on the first semiconductor layer ) of the first gate electrode ( Fig. 7 #20 left transistor) or the second gate electrode ( Fig. 7 #20 right transistor) on the base substrate ( Fig. 3a #10) and an orthographic projection ( [0017] orthogonal projections of the first gate and the second gate projected on the first semiconductor layer are both located in an orthogonal projection of the first shielding layer projected on the first semiconductor layer ) of a data line ( Fig. 7: Data) electrically connected to the pixel circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) on the base substrate ( Fig. 3A #10).
Regarding claim 20, Wang teaches display device ( [0057] a display panel ) comprising the display substrate ( Fig. 3A a substrate #10 ) according to claim 1 (as discussed above).
Regarding claim 21, Wang teaches the display device according to claim 20 (as discussed above), wherein the display substrate (Fig. 3A #10) includes a first transition area ( [0086] a bridge component located in a non-display area), a second transition area ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer), and a normal display area ( [0014] the light-emitting function layer ) ; the display substrate ( Fig. 3A #10 ) includes a first pixel driving circuit ( [0039] a light emitting-function layer located on the pixel driving circuit layer ) arranged in the normal display area ( [0014] the light-emitting function layer ), a second pixel driving circuit ( [0040] the pixel driving circuit layer further includes a second thin film transistor electrically connected with the light-emitting function layer ) arranged in the second transition area ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer ), and a third pixel driving circuit ( [0054] The pixel driving circuit layer includes a plurality of pixel driving circuits ) arranged in the first transition area ( [0086] a bridge component located in a non-display area ); the data lines ( Fig. 7 Data ) included in the display substrate ( Fig. 3A #10 ) and coupled to the first pixel driving circuit ( [0020] the pixel driving circuits drive the light-emitting units to emit light ) extend along a column direction ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ); in the second transition area ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer ), the display substrate ( Fig. 3A #10 ) further includes data lines ( Fig. 7: Data ) extending along a row direction ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ) and arranged between a light emitting control transistor ( [0026] the second light-emitting control transistor) included in the second pixel driving circuit ( [0040] the pixel driving circuit layer further includes a second thin film transistor electrically connected with the light-emitting function layer ) and a second initialization voltage line ( [0020] a second initialization transistor ) coupled to the second pixel driving circuit ( [0040] the pixel driving circuit layer further includes a second thin film transistor electrically connected with the light-emitting function layer ); a data line ( Fig. 7: Data ) coupled to the third pixel driving circuit ( [0054] The pixel driving circuit layer includes a plurality of pixel driving circuits ) and included in the display substrate ( Fig. 3A #10) is electrically connected to at least one data line ( Fig. 7: Data ) extending along the row direction ( [0020 the display panel further includes a plurality of light-emitting units disposed in an array ).
Regarding claim 22, Wang teaches the display device according to claim 21 ( as discussed above), wherein an area of an orthographic projection ( [0057] an orthogonal projection of the shielding component #50 projected on the substrate #10 at least partially overlaps an orthogonal projection of the compensation transistor #20 projected on the substrate #10 ) of an anode connection portion ( [0015] the second source/drain layer is electrically connected with the anode ) in the at least one third pixel driving circuit ( [0054] The pixel driving circuit layer includes a plurality of pixel driving circuits ) arranged in the second transition area ( [0041] the display panel further includes a reset metal line located between the second gate layer and the second source/drain layer ) and included in the display substrate ( Fig. 3A #10 ) is larger than an area of an orthographic projection ( [0057] an orthogonal projection of the shielding component #50 projected on the substrate #10 at least partially overlaps an orthogonal projection of the compensation transistor #20 projected on the substrate #10 ) of an anode connection portion ( [0015] the second source/drain layer is electrically connected with the anode ) in the second pixel driving circuit ( [0040] the pixel driving circuit layer further includes a second thin film transistor electrically connected with the light-emitting function layer ) on the base substrate ( Fig. 3A #10 ); the anode connection portion ( [0015] the second source/drain layer is electrically connected with the anode ) is a connection conductive portion between the pixel driving circuit ( [0040] the pixel driving circuit layer further includes a second thin film transistor electrically connected with the light-emitting function layer ) and a corresponding anode pattern ( [0015] the second source/drain layer is electrically connected with the anode ).
Response to Amendment/Arguments
Applicant’s arguments, see page 10 of remarks, filed 03/13/26, with respect to Drawings have been fully considered and are persuasive. The objection of 12/16/25 has been withdrawn.
Applicant’s arguments, see pages 10-12 of remarks, filed 03/13/26, with respect to Claim 1 have been fully considered and are persuasive. The rejection of 12/16/25 has been withdrawn.
Applicant's arguments filed 03/13/26 have been fully considered but they are not persuasive. Applicant argues that claim 1 "the gate electrode of the driving transistor is coupled to a first electrode of the compensation transistor through a first conductive connection portion," is not taught by Wang, however, Fig. 6 provides the semiconductor structure for the driving transistor and Fig. 7 shows how the driving semiconductor is coupled to the compensation transistor through node B.
Applicant further argues that Wang does not disclose “the orthographic projection of Vdd nor that of Vss on the substrate overlaps with the orthographic projection of the gate electrode of the driving transistor on the substrate” is not specifically mentioned in claim 1 so the argument is not relevant. Orthographic projection is mentioned “an orthographic projection of the first voltage line on the base substrate at least partially overlaps an orthographic projection of a gate electrode of the driving transistor on the base substrate,” “an orthographic projection of the first voltage line on the base substrate at least partially overlaps an orthographic projection of the first conductive connection portion on the base substrate wherein a first gate metal layer where the gate electrode of the driving transistor is located is on a side of an active layer where the first electrode of the compensation transistor is located, away from the base substrate; a first source-drain metal layer where the first conductive connection portion is located is on a side of the first gate metal layer where the gate electrode of the driving transistor is located, away from the base substrate,” and “the orthographic projection of the first conductive connection portion on the base substrate at least partially overlaps an orthographic projection of the first active pattern on the base substrate.” All three of these are illustrated in Fig. 6 and the connectivity is described in Fig. 7.
Applicant then argues that Wang does not disclose a component similar to the “first conductive connection portion” however, Fig. 7 node B connects the driving transistor as described in [0094] A gate of the driving transistor T1 is connected to the first node Q(E), a first terminal of the driving transistor T1 is connected to the third node B, and a second terminal of the driving transistor T1 is connected to the second node A.
Applicant further argues that Wang does not disclose a “first active pattern” of the compensation transistor, however, Fig. 6 #21 is the first semiconductor layer 21.
Applicant’s final argument that Wang does not solve the same problem as the present application is also not persuasive According to the MPEP, "the prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed…." In re Fulton, 391 F.3d 1195, 1201, 73 USPQ2d 1141, 1146 (Fed. Cir. 2004). See also MPEP § 2123.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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