DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 8-10 are rejected under 35 U.S.C. 102 as being anticipated by Li et. al., (CN 103390786 B1, cited by the applicant and a machine translation has been relied upon).
Regarding claims 1 and 10, Li teaches a circuit comprising a power divider, comprising: at least two branches (see Fig. 1 of Li);
wherein the at least two branches comprise a first branch (A2’B) coupled between a first port (A) and a second port (2'); and a second branch (A3’C) coupled between the first port (A) and a third port (3');
wherein the first branch (A2’B) comprises a first transmission line (m1Z0, θ1) for power dividing function coupled to the first port (A), and a first impedance matching structure (2’B[Wingdings font/0xE0]m2Z0, θ3) coupled to the second port (2'); and
wherein the second branch (A3’C) comprises a second transmission line (m3Z0, θ5) for power dividing function coupled to the first port (A), and a second impedance matching structure (3’C) coupled to the third port (m4Z0, θ7).
wherein per claim 2, the first impedance matching structure (2’B) is constructed at least based on an impedance matching requirement of a first circuit portion (Z0 at B) following the second port (2'); and
PNG
media_image1.png
404
561
media_image1.png
Greyscale
Fig. 1 of Li annotated by the examiner for ease of reference.
wherein the second impedance matching structure (3’C) is constructed at least based on an impedance matching requirement of a second circuit portion (Z0 at C) following the third port (3').
wherein per claim 3, the first impedance matching structure (2’B) is further constructed to provide impedance transforming between the first transmission line (A2’) and the first circuit portion (Z0 at B); and
wherein the second impedance matching structure (3’C) is further constructed to provide impedance transforming between the second transmission line (A3’) and the second circuit portion (Z0 at C).
wherein per claim 8, an impedance of the first transmission line (m1Z0) and an impedance of the second transmission line (m3Z0) are determined based at least on a power dividing ratio between the second port (2') and the third port (3') (see equations in §0001 through §0012).
wherein per claim 9, the power divider is a Wilkinson power divider, WPD (modified form of Wilkinson power divider, p. 1-2).
Claims 1-7 are rejected under 35 U.S.C. 102 as being anticipated by Wong et. al., (“High-power high-efficiency broadband GaN HEMT Doherty amplifiers for base station applications”, January 2018).
[AltContent: textbox (P2)][AltContent: textbox (P1)][AltContent: textbox (N1)][AltContent: textbox (N2)][AltContent: oval][AltContent: oval][AltContent: oval][AltContent: oval]
PNG
media_image2.png
253
756
media_image2.png
Greyscale
Fig. 6 of Wong et. al., reproduced for ease of reference.
Regarding claims 1 and 10, Wong teaches a circuit, wherein the circuit is a Doherty power amplifier comprising a power divider (Fig. 6), comprising: at least two branches (see Fig. 6 of Wong);
wherein the at least two branches comprise a first branch (top branch to carrier amplifier) coupled between a first port (Pin) and a second port (P1); and a second branch (bottom branch) coupled between the first port (Pin) and a third port (P2);
wherein the first branch (top branch) comprises a first transmission line (Z1, l/4) for power dividing function coupled to the first port (Pin), and a first impedance matching structure (Z2, l/4) coupled to the second port (P1); and
wherein the second branch (bottom branch) comprises a second transmission line (Z1, l/4) for power dividing function coupled to the first port (Pin), and a second impedance matching structure (Z2, l/4) coupled to the third port (P2).
wherein per claim 2, the first impedance matching structure (Z2, l/4) is constructed at least based on an impedance matching requirement of a first circuit portion (input to the carrier amplifier) following the second port (P1); and
wherein the second impedance matching structure (Z2, l/4) is constructed at least based on an impedance matching requirement of a second circuit portion (input to the peaking amplifier) following the third port (P2).
wherein per claim 3, the first impedance matching structure (Z2, l/4) is further constructed to provide impedance transforming (quarter wave transformer) between the first transmission line (Z1, l/4) and the first circuit portion (input to the carrier amplifier); and
wherein the second impedance matching structure (Z2, l/4) is further constructed to provide impedance transforming (quarter wave transformer) between the second transmission line (Z1, l/4) and the second circuit portion (input to the peaking amplifier).
wherein per claim 4, the first circuit portion and the second circuit portion comprise a power amplifying component (carrier and peaking amplifiers respectively).
wherein per claim 5, the power amplifying component comprises a transistor (GaN HEMT transistors).
wherein per claim 6, the first impedance matching structure (Z2, l/4) and the second impedance matching structure (Z2, l/4) have a planar shape (microstrip line, see Fig. 6 above).
wherein per claim 7, the first impedance matching structure (Z2, l/4) and the second impedance matching structure (Z2, l/4) have a rectangle shape (see Fig. 6 above and for regular microstrip line) with a width lager (the characteristic impedance is smaller to match between close to 50 W impedance to very low input impedance of the carrier1/peaking amplifier) than a width (characteristic impedance is larger (close to 50 W because closer to the system input) than the impedance transformer) of the first transmission line (Z1, l/4) and/or the second transmission line (Z1, l/4).
Claims 1, 10-14 are rejected under 35 U.S.C. 102 as being anticipated by Sakata et. al., (“Adaptive Input-Power Distribution in Doherty Power Amplifier using Modified Wilkinson Power Divider, PAWR 2020, cited by the applicant).
[AltContent: textbox (Power Combining)][AltContent: rect][AltContent: textbox (P1)][AltContent: textbox (N2)][AltContent: textbox (P2)][AltContent: textbox (P3)][AltContent: textbox (N3)][AltContent: oval][AltContent: oval][AltContent: oval][AltContent: oval]
PNG
media_image3.png
215
868
media_image3.png
Greyscale
Fig. 6 of Sakata et. al., reproduced for ease of reference.
Regarding claims 1 and 10, Sakata teaches a Doherty Power Amplifier circuit comprising a power divider (between the RF input and the main and Auxiliary amplifier), comprising: at least two branches (see Fig. 3 of Sakata);
wherein the at least two branches comprise a first branch (top branch to main amplifier) coupled between a first port (P1) and a second port (P2); and a second branch (bottom branch to auxiliary amplifier) coupled between the first port (P1) and a third port (P3);
wherein the first branch (top branch) comprises a first transmission line (√2Z0, l/4) for power dividing function coupled to the first port (P1), and a first impedance matching structure (input matching network, main) coupled to the second port (P2); and
wherein the second branch (bottom branch) comprises a second transmission line (√2Z0, l/4) for power dividing function coupled to the first port (P1), and a second impedance matching structure (input matching network, peaking) coupled to the third port (P3).
wherein per claim 11, the power divider functions as an input power splitter of the Doherty power amplifier (the circuit of Fig. 3);
wherein the Doherty power amplifier comprises a first amplifying transistor (main amplifier) coupled to the second port (P2), and a second amplifying transistor (peaking amplifier) coupled to the third port (P3); and
wherein the first amplifying transistor has an offsetting (Z0, l/4) requirement for the first branch of the power divider (see Fig 3 of Sakata).
wherein per claim 12, the first branch further comprises a third transmission line (Z0, l/4) for offsetting function, coupled between the first transmission line ((√2Z0, l/4) and the first impedance matching structure (input matching network, main). wherein per claim 13, the third transmission line (Z0, l/4) is constructed at least based on the offsetting requirement of the first amplifying transistor (main amplifier).
wherein per claim 14, the third transmission line (Z0, l/4) is further constructed to provide impedance transforming between the first transmission line (it also performs impedance transforming as is evident because the first transmission line has a characteristic impedance of √2Z0 while the third transmission line has a characteristic impedance Z0 different from the first transmission line and it is l/4 long hence essentially this third transmission line segment also performs impedance transformation along with a 90 degrees phase offset of the main path signal between the first transmission line) and the first amplifying transistor (main amplifier).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sakata in view of Sneijers (White Paper: Doherty Amplifiers in UHF, published on RF Café, 2016 by Walter Sneijers, RF Application Engineer, Ampleon).
According to claim 15, Sakata teaches all limitations of claim 10, Sakata also teaches that the Doherty amplifier circuit of claim 10 also have a power combining circuit (for the Doherty amplifier, see annotations of Fig. 3 of Sakata);
wherein the power divider functions as an input power splitter (see Fig. 3 of Sakata) of the power combining circuit (see annotations of Fig. 3 of Sakata);
Sakata, however, doesn’t explicitly teaches that the power combining circuit comprises a third amplifying transistor coupled to the second port (P2), and a fourth amplifying transistor coupled to the third port (P3).
Sneijers teaches in Fig. 1B a Doherty amplifier similar to Sakata where the power combining circuit comprises a third amplifying transistor coupled to the second port (P2), and a fourth amplifying transistor coupled to the third port (P3).
A person of ordinary skill in the art would find it obvious to increase the power handling capability of the Doherty amplifier by adding extra transistors in the main amplifying path and in the auxiliary amplifying path as taught by Sneijers, the resultant combination, thereby, teaching all limitations of claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
1 120W GaN input impedance is less than 2 ohms around 2 GHz, see CGH40120P data sheet of 120 W, RF Power GaN HEMT by CREE semiconductor (attached here with as an NPL).
Prosecution Insights