DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 03/17/2026, in which: claims 1, 3, 7-8, 10-11, and 13 are amended; claims 4 and 16-20 stand withdrawn; and the rejection of the claims are traversed. Claims 1-3 and 5-15 are currently pending an Office action on the merits as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-3 and 5-15 are rejected under 35 U.S.C. 103 as being unpatentable over Okabe et al. (WO Publication 2020174605/Machine Translation Document 08/25/2025) in view of Chun et al. (US Publication 20200133083).
Regarding independent claim 1, Okabe teaches a display device (fig. 3, 50D) comprising:
a base substrate (10);
a thin film transistor layer (30a) provided ith:
a semiconductor layer (12ad and 12ae), a gate insulating film (13), a first metal layer (16a and 16b), a first interlayer insulating film (17), a second metal layer (16c), a second interlayer insulating film (19), and a third metal layer (20a, 20b, 20c, 20d, and 20e), in this stated order, on the base substrate (fig. 3), the thin film transistor layer including a thin film transistor (9d) and a capacitor (fig. 4, 9h) arranged for each of a plurality of subpixels; and
a light-emitting element layer (fig. 3, 33) provided on the thin film transistor layer and including a light-emitting element (35) arranged for each of the plurality of subpixels, wherein:
the thin film transistor includes the semiconductor layer, the gate insulating film covering the semiconductor layer, and a gate electrode (16a) provided as the first metal layer on the gate insulating film and arranged in an island shape overlapping with a part of the semiconductor layer in a plan view (fig. 3),
electrode in the plan view (fig. 3), and a capacitance wiring line (20e) provided as the third metal layer on the capacitance electrode and overlapping with the capacitance electrode and the gate electrode in the plan view (fig. 3).
Okabe does not teach the capacitance wiring line is electrically connected to the capacitance electrode, a capacitance of the capacitor is formed between the gate electrode and at least one of the capacitance electrode and the capacitance wiring line, the gate electrode facing the capacitance electrode or capacitance wiring line across the first interlayer insulating film, and a line width of the capacitance wiring line is equal to[[,]] or greater than a line width of the capacitance electrode, and is equal to or less than a line width of the gate electrode.
Chun teaches the capacitance wiring line (fig. 5, 30 on left side occupies space for capacitance wiring line of Okabe) is electrically connected to the capacitance electrode (12 and 21, paragraphs 0062-0066),
a capacitance (CA) of the capacitor is formed between the gate electrode (11 occupies space for gate electrode of Okabe) and at least one of the capacitance electrode and the capacitance wiring line (fig. 5), the gate electrode facing the capacitance electrode or capacitance wiring line across the first interlayer insulating film (17), and a line width of the capacitance wiring line is equal to[[,]] or greater than a line width of the capacitance electrode, and is equal to or less than a line width of the gate electrode (fig. 5, width of 30 greater than width of 12 and less than 11).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device of Okabe and the capacitance of Chun in order to "secure improved storage capacitance due to a large scale and prevent influence of load of a gate driving voltage signal applied to first lines" (Chun paragraph 0068).
Regarding dependent claim 2, Chun further teaches the display device according to claim 1, wherein the capacitance wiring line (fig. 6, 130) is provided along a circumferential end of the gate electrode (110), at an inner side of the circumferential end of the gate electrode (fig. 6, 130 is provided on the inside of 110).
Okabe in view of Chun does not explicitly teach the capacitance electrode is provided along a circumferential end of the capacitance wiring line, however, Chun fig. 6 discloses the capacitance electrode 120 is provided at an outer side of the circumferential end of capacitance wiring line 130.
It would have been an obvious matter of design choice to provide the capacitance electrode at an inner side of the circumferential end of the capacitance wiring line, since such a modification would have involved a mere change in the size of component (e.g., making 120 smaller). A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device of Okabe and the capacitance wiring line position of Chun per the reason(s) stated above in claim 1.
Regarding dependent claim 3, Okabe further teaches the display device according to claim 1,
wherein a first opening (fig. 7, 18m), overlapping with the capacitance wiring line [[,]] in the plan view, and extending through the second interlayer insulating film, is provided in the second interlayer insulating film (fig. 7, 18m extends through 19 and is provided in 19),
the first opening is provided along a circumferential end of the capacitance electrode (fig. 7, 18m surrounds edge of 20e), and
the capacitance electrode or the first interlayer insulating film is exposed from the first opening (fig. 7, 17 is exposed by 18m).
Regarding dependent claim 5, Okabe further teaches the display device according to claim 3, wherein the first interlayer insulating film is exposed from the first opening (fig. 5, edge of 17 is exposed by CCT2), and in the first opening, the capacitance wiring line is formed in the same layer as the capacitance electrode (fig. 5, 12 and portion of 30 are formed in 17).
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Regarding dependent claim 6, Okabe further teaches the display device according to claim 5, wherein a sum of the line width of the capacitance electrode and the line width of the capacitance wiring line in a portion formed in the same layer as the capacitance electrode is equal to or less than the line width of the gate electrode (see figure below).
Regarding dependent claim 7, Okabe further teaches the display device according to claim 1, wherein a first opening (fig. 5, 18m), overlapping with the capacitance wiring line[[,]] in the plan view, and extending through the second interlayer insulating film, is provided in the second interlayer insulating film (fig. 7), and
the first opening is provided in a hole shape and the capacitance electrode is exposed from the first opening (fig. 5).
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Regarding dependent claim 8, Okabe further teaches the display device according to claim 7, wherein a portion of the capacitance wiring line, not overlapping with the capacitance electrode[[,]] in the plan view, is provided on at least one side of the capacitance wiring line in a line width direction (see figure below, portion of 20e in marked area), and a part of the capacitance of the capacitor is formed between the gate electrode and the portion of the capacitance wiring line
Regarding dependent claim 9, Okabe further teaches the display device according to claim 1, wherein the thin film transistor is a drive thin film transistor (machine translation document, page 3 paragraph 5, “drive TFT 9d”).
Regarding dependent claim 10, Okabe further teaches the display device according to claim 9, wherein the capacitance electrode is provided with an opening (fig. 7, 18m) exposing the first interlayer insulating film,
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a contact hole (see figure below) is provided in the first interlayer insulating film and the second interlayer insulating film in the
Okabe does not teach a connection wiring line electrically connected to the gate electrode via the contact hole is provided as the third metal layer on the second interlayer insulating film.
Chun teaches a connection wiring line (fig. 5, 30 on the right side) electrically connected to the gate electrode (11 occupies space for gate electrode of Okabe) via the contact hole (CCT2 right side) is provided as the third metal layer on the second interlayer insulating film (19).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device of Okabe and the connection wiring line of Chun per the reason(s) stated above in claim 1.
Regarding dependent claim 11, Okabe further teaches the display device according to claim 10, wherein the capacitance wiring line is provided along circumferential ends of the gate electrode and the In re Dailey, 149 USPQ 47 (CCPA 1966), see MPEP 2144.04.).
Regarding dependent claim 12, Okabe further teaches the display device according to claim 11, wherein the semiconductor layer includes a channel region (fig. 6, 12ac) overlapping with the gate electrode in the plan view,
a pair of conductor regions (12aa and 12ab) sandwiches the channel region (machine translation document, page 4 paragraph 4, “semiconductor layer 12ad includes an intrinsic region 12ac provided so as to overlap the gate electrode 16a in a plan view, a pair of conductor regions 12aa provided so as to sandwich the intrinsic region 12ac, and 12ab”), and
an intermediate portion of the channel region includes a recessed portion provided in a U-shape in the plan view (fig. 5, center dotted region corresponding to 12ac is in a U-shape, see also machine translation document, page 4 paragraph 4).
Regarding dependent claim 13, Okabe further teaches the display device according to claim 12, wherein the
Regarding dependent claim 14, Okabe further teaches the display device according to claim 13, wherein the connection wiring line intersects the channel region in the recessed portion (fig. 5, 20e can be rearranged to intersect 12ac per MPEP 2144.04 instead of just meeting at recessed portion).
Regarding dependent claim 15, Okabe further teaches the display device according to claim 1, wherein the light-emitting element is an organic electroluminescence element (machine translation document, page 6 paragraph 4).
Response to Arguments
Applicant’s arguments, see page 8, filed 03/17/2026, with respect to the specification and 112(b) rejection have been fully considered and are persuasive. The 112(b) rejection and objection of 03/17/2026 has been withdrawn.
Applicant’s arguments filed 03/17/2026 have been fully considered but are not persuasive.
Applicant argues on page 10 of the instant Remarks: “As shown, FIG. 5 of Chun depicts a configuration in which transparent electrode pattern 30 (the alleged capacitance wiring line) is connected to first metal layer 11 (the alleged gate electrode) via first contact electrode pattern 21. See Chun, at FIG. 5 and paragraphs [0065] and [0066]. However, FIG. 5 of Chun does not teach, disclose, or suggest that transparent electrode pattern 30 is electrically connected to the alleged capacitance electrode 12. As such, Chun fails to teach, disclose, or suggest "the capacitance wiring line is electrically connected to the capacitance electrode," as recited in independent claim 1.
However, as stated above, Chun teaches the capacitance wiring line is electrically connected to the capacitance electrode (paragraphs 0065-0066, 21 and 12 are part of capacitance electrode of Okabe). Thus, independent claim 1 and its dependent claims are not patentably distinguishable over Okabe and Chun, alone or in any permissible combination for at least the reason(s) presented above.
NOTE: Examiner also notes reference US 20170053975 A1 also teaches limitations applicant presented in arguments of claim 1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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