Prosecution Insights
Last updated: April 19, 2026
Application No. 18/025,321

MULTI-WAVELENGTH LED STRUCTURES AND MANUFACTURING METHODS THEREOF

Final Rejection §102§103
Filed
Mar 08, 2023
Examiner
MIYOSHI, JESSE Y
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Enkris Semiconductor Inc.
OA Round
2 (Final)
56%
Grant Probability
Moderate
3-4
OA Rounds
3y 7m
To Grant
76%
With Interview

Examiner Intelligence

Grants 56% of resolved cases
56%
Career Allow Rate
268 granted / 476 resolved
-11.7% vs TC avg
Strong +19% interview lift
Without
With
+19.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
54 currently pending
Career history
530
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
48.3%
+8.3% vs TC avg
§102
25.4%
-14.6% vs TC avg
§112
23.7%
-16.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 476 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 1/15/2026 have been fully considered but they are not persuasive. Applicant argues on page 14 that layer 144 is the uppermost layer of light emitting layer 104 and is in direct contact with the cladding layer 105. Applicant then argues that claimed second anti-annihilation layer does not contact the second semiconductor layer, and there is a second barrier layer between the second anti-annihilation layer and the second semiconductor layer, therefore 144 does not correspond to the second anti-annihilation layer in amended claim 1. Examiner respectfully disagrees. light emitting layer 104 is a MQW structure and there is provided plural second anti-annihilation layers, therefore the below annotated drawing shows how Okuno meets each of the claim limitations alleged as not being taught by Okuno. PNG media_image1.png 538 784 media_image1.png Greyscale Rejection is being maintained and has been updated to include the amended portions. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4, 6-10, 12, 14, 16-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mu et al. (CN105870286; hereinafter “Mu”) in view of Okuno (US PGPub 2017/0092807). Re claim 1: Mu teaches (e.g. figs. 5 and 6) a multi-wavelength LED structure, comprising: a first semiconductor layer (n-type layer 430; e.g. paragraph 56 of translation); a stress release layer (n-type multilayer 341/441; e.g. paragraph 58) located on the first semiconductor layer (430), wherein the stress release layer (341/441) is provided with a V-shaped pit (V-shaped pits 443; e.g. paragraph 57), wherein the V-shaped pit (443) penetrates part of a thickness of the stress release layer (341/441); a first quantum well layer (green MQW region 342C; e.g. paragraph 52) and a second quantum well layer (yellow MQW region 342D; e.g. paragraph 52) stacked from bottom to top on a side wall of the V-shaped pit (443) and a top wall of the stress release layer (341/441); wherein the second quantum well layer (342D) located on the top wall of the stress release layer (341/441) is a first light-emitting region (region of 342D not in 443; hereinafter “1LER”), the first quantum well layer (342C) located on the top wall of the stress release layer (341/441) is a second light-emitting region (region of 342C not in 443; hereinafter “2LER”), and the first quantum well layer (342C) or the second quantum well layer (342D) located on the side wall of the V-shaped pit (443) is a third light-emitting region (region of 342C and 342D in 443; hereinafter “3LER”); and a second semiconductor layer (p-type layer 450; e.g. paragraph 56) located on the second quantum well layer (342D), wherein a conductive type of the second semiconductor layer (p-type layer 450) is opposite to a conductive type of the first semiconductor layer (n-type layer 430); if electron-hole pairs of the second semiconductor layer (450) and the first semiconductor layer (430) recombine in the first light-emitting region (1LER), light corresponding to a first light-emitting wavelength emits (light from 342D emits yellow light); if electron-hole pairs of the second semiconductor layer (450) and the first semiconductor layer (430) recombine in the second light-emitting region (2LER), light corresponding to a second light-emitting wavelength emits (light from 342C emits green light); if electronic-hole pairs of the second semiconductor layer (450) and the first semiconductor layer (430) recombine in the third light-emitting region (3LER) through the side wall of the V-shaped pit (443), light corresponding to a third light-emitting wavelength emits (as MPEP 2112.01(i) states when the structure recited in the reference is substantially identical to that of the claim, claimed properties or functions re presumed to be present); and the first light-emitting wavelength, the second light-emitting wavelength and the third light-emitting wavelength correspond to different colors of lights (as MPEP 2112.01(i) states when the structure recited in the reference is substantially identical to that of the claim, claimed properties or functions re presumed to be present); wherein a conductivity type of the first semiconductor layer (n-type layer 430; e.g. paragraph 56) is N-type, and a conductivity type of the second semiconductor layer (p-type layer 450; e.g. paragraph 56) is P-type; and the second quantum well layer (342D) comprises a second well layer (well layer 342DW; e.g. paragraph 52), second barrier layers (barrier layer 342DB; e.g. paragraph 52) arranged on both sides of the second well layer (342DW), and/or the first quantum well layer (342C) comprises a first well layer (well layer 342CW; e.g. paragraph 52), first barrier layers (barrier layer 342CB; e.g. paragraph 52) arranged on both sides of the first well layer (342CW), and a first anti-annihilation layer (this element is not necessary due to the above bolded “and/or” statement) arranged between the first barrier layer (342CB) adjacent to the second quantum well layer (342DW) and the first well layer (342CW), and a conduction band energy level of the first anti-annihilation layer (this element is not necessary due to the above bolded “and/or” statement) is higher than a conduction band energy level of the first barrier layer (342CB); wherein a conductivity type of the first semiconductor layer (n-type layer 430; e.g. paragraph 56), and a conductivity type of the second semiconductor layer (p-type layer 450; e.g. paragraph 56); and the first quantum well layer (342C) comprises a first well layer (well layer 342CW; e.g. paragraph 52), first barrier layers (barrier layer 342CB; e.g. paragraph 52) arranged on both sides of the first well layer (342CW), and a first anti-annihilation layer (this element is not necessary due to the above bolded “and/or” statement) arranged between the first barrier layer (342CB) adjacent to the stress release layer (341/441) and the first well layer (342CW), and a conduction band energy level of the first anti-annihilation layer (this element is not necessary due to the above bolded “and/or” statement) is higher than a conduction band energy level of the first barrier layer (342CB), and/or the second quantum well layer (342D) comprises a second well layer (well layer 342DW; e.g. paragraph 52), second barrier layers (barrier layer 342DB; e.g. paragraph 52) arranged on both sides of the second well layer (342DW). Mu is silent as to explicitly teaching a second anti-annihilation layer arranged between the second barrier layer (342DB) adjacent to the second semiconductor layer (450) and the second well layer (342DW), and a conduction band energy level of the second anti- annihilation layer is higher than a conduction band energy level of the second barrier layer (342DB) OR teaching a second anti-annihilation layer arranged between the second barrier layer (342DB) adjacent to the first quantum well layer (342CW) and the second well layer (342DW), and a conduction band energy level of the second anti- annihilation layer is higher than a conduction band energy level of the second barrier layer (342DB); and a conductivity type of the first semiconductor layer is P-type, and a conductivity type of the second semiconductor layer is N-type. Okuno teaches (e.g. figs. 1, 3) a second anti-annihilation layer (144; e.g. paragraph 42) arranged between the second barrier layer (141 of Okuno/342DB of Mu) adjacent to the second semiconductor layer (103 of Okuno /450 of Mu) and the second well layer (142 of Okuno /342DW of Mu), and a conduction band energy level of the second anti-annihilation layer (144 of Okuno) is higher than a conduction band energy level of the second barrier layer (141 of Okuno/342DB of Mu); OR a second anti-annihilation layer (144; e.g. paragraph 42) arranged between the second barrier layer (141 of Okuno/342DB of Mu) adjacent to the first quantum well layer (142 of Okuno/342CW of Mu) and the second well layer (142 of Okuno/342DW of Mu), and a conduction band energy level of the second anti- annihilation layer (144; e.g. paragraph 42) is higher than a conduction band energy level of the second barrier layer (342DB). Also, it is known for the conductivity types to be reversed and polarity of voltage applied to be reversed since the order in which the device is formed can be reversed. It would have been obvious to one of ordinary skill in the art, at the time of effective filing, absent unexpected results, to use the anti-annihilation layer within the MQW as taught by Okuno in the device of Mu in order to have the predictable result of making uniform the electron density in the thickness direction and improving emission performance without increasing drive voltage (see paragraphs 60 and of Okuno). Re claim 4: Mu in view of Okuno teaches the multi-wavelength LED structure according to claim 1, wherein a third anti-annihilation layer (144 of Okuno which would be between each MQW; hereinafter “3AAL”) is arranged between the first quantum well layer (342C of Mu) and the second quantum well layer (342D of Mu), and a conduction band energy level of the third anti-annihilation layer (3AAL) is higher than a conduction band energy level of the second barrier layer (141 of Okuno/342DB of Mu). Re claim 6: Mu in view of Okuno teaches the multi-wavelength LED structure according to claim 1, wherein a third anti-annihilation layer (144 of Okuno which would be between each MQW; hereinafter “3AAL”) is arranged between the first quantum well layer (342C of Mu) and the second quantum well layer (342D of Mu), and a conduction band energy level of the third anti-annihilation layer (3AAL) is higher than a conduction band energy level of the first barrier layer (141 of Okuno/342CB of Mu). Re claim 8: Mu in view of Okuno teaches the multi-wavelength LED structure according to claim 1, wherein the first anti-annihilation layer (144 of Okuno within 342C of Mu) contains Al element (Al0.2Ga0.8N layer 144 of Okuno), and from the first barrier layer (342CB of Mu) adjacent to the second quantum well layer (342D of Mu) to the first well layer (342CW of Mu), a proportion of an amount of Al element in the first anti-annihilation layer gradually increases; or the second anti-annihilation layer (144 of Okuno within 342D of Mu) contains Al element (Al0.2Ga0.8N layer 144 of Okuno), and from the second barrier layer (342DB of Mu) adjacent to the second semiconductor layer (450 of Mu) to the second well layer (342DW of Mu), a proportion of an amount of Al element in the second anti-annihilation layer (144 of Okuno within 342D of Mu) gradually increases (there would be an distribution when viewed in the microscopic level that is gradual). Re claim 9: Mu in view of Okuno teaches the multi-wavelength LED structure according to claim 8, wherein from the first barrier layer (342CB of Mu) adjacent to the second quantum well layer (342D of Mu) to the first well layer (342CW of Mu), the proportion of the amount of Al element in the first anti-annihilation layer (144 of Okuno within 342C of Mu) continuously increases or increases stepwise (see fig. 3 of Okuno); or from the second barrier layer adjacent to the second semiconductor layer to the second well layer, the proportion of the amount of Al element in the second anti- annihilation layer continuously increases or increases stepwise. Re claim 10: Mu teaches (e.g. figs. 5 and 6) a manufacturing method of a multi-wavelength LED structure according to claim 1,comprising: epitaxially growing (epitaxial structure for n-type layer 430; e.g. paragraph 53, 56) the stress release layer (341/441) on the first semiconductor layer (n-type layer 430; e.g. paragraph 56 of translation), wherein the stress release layer (341/441) is provided with the V-shaped pit (V-shaped pits 443; e.g. paragraph 57); successively epitaxially growing the first quantum well layer (green MQW region 342C; e.g. paragraph 52) and the second quantum well layer (yellow MQW region 342D; e.g. paragraph 52) on a side wall of the V-shaped pit (443) and the top wall of the stress release layer (341/441); wherein the second quantum well layer (342D) located on the top wall of the stress release layer (341/441) is the first light-emitting region (region of 342D not in 443; hereinafter “1LER”), the first quantum well layer (342C) located on the top wall of the stress release layer (341/441) is the second light-emitting region (region of 342C not in 443; hereinafter “2LER”), and the first quantum well layer (342C) or the second quantum well layer (342D) located on the side wall of the V-shaped pit (443) is the third light- emitting region (region of 342C and 342D in 443; hereinafter “3LER”); and epitaxially growing the second semiconductor layer (p-type layer 450; e.g. paragraph 56) on the second quantum well layer (342D), wherein the conductive type of the second semiconductor layer (p-type layer 450) is opposite to the conductive type of the first semiconductor layer (n-type layer 430); if electron-hole pairs of the second semiconductor layer (450) and the first semiconductor layer (430) recombine in the first light-emitting region (1LER), light corresponding to the first light-emitting wavelength emits (light from 342D emits yellow light); if electron-hole pairs of the second semiconductor layer (450) and the first semiconductor layer (430) recombine in the second light-emitting region (2LER), light corresponding to the second light-emitting wavelength emits (light from 342C emits green light); if electronic-hole pairs of the second semiconductor layer (450) and the first semiconductor layer (430) recombine in the third light-emitting region (3LER) through the side wall of the V-shaped pit (443), light corresponding to the third light-emitting wavelength emits (as MPEP 2112.01(i) states when the structure recited in the reference is substantially identical to that of the claim, claimed properties or functions re presumed to be present); and the first light-emitting wavelength, the second light-emitting wavelength and the third light-emitting wavelength correspond to different colors of lights (as MPEP 2112.01(i) states when the structure recited in the reference is substantially identical to that of the claim, claimed properties or functions re presumed to be present); wherein a conductivity type of the first semiconductor layer (n-type layer 430; e.g. paragraph 56) is N-type, and a conductivity type of the second semiconductor layer (p-type layer 450; e.g. paragraph 56) is P-type; and the second quantum well layer (342D) comprises a second well layer (well layer 342DW; e.g. paragraph 52), second barrier layers (barrier layer 342DB; e.g. paragraph 52) arranged on both sides of the second well layer (342DW), and/or the first quantum well layer (342C) comprises a first well layer (well layer 342CW; e.g. paragraph 52), first barrier layers (barrier layer 342CB; e.g. paragraph 52) arranged on both sides of the first well layer (342CW), and a first anti-annihilation layer (this element is not necessary due to the above bolded “and/or” statement) arranged between the first barrier layer (342CB) adjacent to the second quantum well layer (342DW) and the first well layer (342CW), and a conduction band energy level of the first anti-annihilation layer (this element is not necessary due to the above bolded “and/or” statement) is higher than a conduction band energy level of the first barrier layer (342CB); wherein a conductivity type of the first semiconductor layer (n-type layer 430; e.g. paragraph 56), and a conductivity type of the second semiconductor layer (p-type layer 450; e.g. paragraph 56); and the first quantum well layer (342C) comprises a first well layer (well layer 342CW; e.g. paragraph 52), first barrier layers (barrier layer 342CB; e.g. paragraph 52) arranged on both sides of the first well layer (342CW), and a first anti-annihilation layer (this element is not necessary due to the above bolded “and/or” statement) arranged between the first barrier layer (342CB) adjacent to the stress release layer (341/441) and the first well layer (342CW), and a conduction band energy level of the first anti-annihilation layer (this element is not necessary due to the above bolded “and/or” statement) is higher than a conduction band energy level of the first barrier layer (342CB), and/or the second quantum well layer (342D) comprises a second well layer (well layer 342DW; e.g. paragraph 52), second barrier layers (barrier layer 342DB; e.g. paragraph 52) arranged on both sides of the second well layer (342DW). Okuno teaches (e.g. figs. 1, 3) a second anti-annihilation layer (144; e.g. paragraph 42) arranged between the second barrier layer (141 of Okuno/342DB of Mu) adjacent to the second semiconductor layer (103 of Okuno /450 of Mu) and the second well layer (142 of Okuno /342DW of Mu), and a conduction band energy level of the second anti-annihilation layer (144 of Okuno) is higher than a conduction band energy level of the second barrier layer (141 of Okuno/342DB of Mu); OR a second anti-annihilation layer (144; e.g. paragraph 42) arranged between the second barrier layer (141 of Okuno/342DB of Mu) adjacent to the first quantum well layer (142 of Okuno/342CW of Mu) and the second well layer (142 of Okuno/342DW of Mu), and a conduction band energy level of the second anti- annihilation layer (144; e.g. paragraph 42) is higher than a conduction band energy level of the second barrier layer (342DB). Also, it is known for the conductivity types to be reversed and polarity of voltage applied to be reversed since the order in which the device is formed can be reversed. Re claim 12: Mu teaches the manufacturing method of the multi-wavelength LED structure according to claim 10, wherein the V-shaped pit is formed during a process of epitaxially growing the stress release layer (V-pits are formed by controlling the material growth conditions; e.g. paragraph 15), or the V-shaped pit is formed by etching the stress release layer. Re claim 14: Mu teaches the manufacturing method of the multi-wavelength LED structure according to claim 10, wherein a third anti-annihilation layer (144 of Okuno which would be between each MQW; hereinafter “3AAL”) is arranged between the first quantum well layer (342C of Mu) and the second quantum well layer (342D of Mu), and a conduction band energy level of the third anti-annihilation layer (3AAL) is higher than the conduction band energy level of the second barrier layer (141 of Okuno/342DB of Mu). Re claim 16: Mu in view of Okuno teaches the manufacturing method of the multi-wavelength LED structure according to claim 10, wherein a third anti-annihilation layer (144 of Okuno which would be between each MQW; hereinafter “3AAL”) is arranged between the first quantum well layer (342C of Mu) and the second quantum well layer (342D of Mu), and a conduction band energy level of the third anti-annihilation layer (3AAL) is higher than the conduction band energy level of the first barrier layer (141 of Okuno/342DB of Mu). Re claim 18: Mu teaches the manufacturing method of the multi-wavelength LED structure according to claim 10, wherein the first anti-annihilation layer (144 of Okuno within 342C of Mu) contains Al element (Al0.2Ga0.8N layer 144 of Okuno), and from the first barrier layer (342CB of Mu) adjacent to the second quantum well layer (342D of Mu) to the first well layer (342CW of Mu), a proportion of an amount of Al element in the first anti-annihilation layer gradually increases; or the second anti-annihilation layer (144 of Okuno within 342D of Mu) contains Al element (Al0.2Ga0.8N layer 144 of Okuno), and from the second barrier layer (342DB of Mu) adjacent to the second semiconductor layer (450 of Mu) to the second well layer (342DW of Mu), a proportion of an amount of Al element in the second anti-annihilation layer (144 of Okuno within 342D of Mu) gradually increases (there would be an distribution when viewed in the microscopic level that is gradual). Re claim 19: Mu teaches the manufacturing method of the multi-wavelength LED structure according to claim 18 wherein from the first barrier layer (342CB of Mu) adjacent to the second quantum well layer (342D of Mu) to the first well layer (342CW of Mu), the proportion of the amount of Al element in the first anti-annihilation layer (144 of Okuno within 342C of Mu) continuously increases or increases stepwise (see fig. 3 of Okuno); or from the second barrier layer adjacent to the second semiconductor layer to the second well layer, the proportion of the amount of Al element in the second anti- annihilation layer continuously increases or increases stepwise. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mu in view of Okuno as applied to claim 1, above, and further in view of Choi et al. (US PGPub 2014/0110720; hereinafter “Choi”). Re claim 20: Mu in view of Okuno teaches substantially the entire structure as recited in claim 1 except explicitly teaching the multi-wavelength LED structure according to claim 3, wherein at least one of the first anti-annihilation layer is doped with P-type ions; or the second anti-annihilation layer is doped with P-type ions. Choi teaches (e.g. fig. 1-3) the multi-wavelength LED structure according to claim 3, wherein at least one of the first anti-annihilation layer (first electron blocking layer 51 made form p-InAlGaN; e.g. paragraph 45) is doped with P-type ions; or the second anti-annihilation layer is doped with P-type ions. It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the p-doped anti-annihilation layer as taught by Choi in the device of Mu in view of Okuno in order to have the predictable result of being able to better block electrons to confine them to the active light emitting regions, improving quantum efficiency of the device. Allowable Subject Matter Claims 7 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JESSE Y MIYOSHI/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

Mar 08, 2023
Application Filed
Oct 10, 2025
Non-Final Rejection — §102, §103
Jan 15, 2026
Response Filed
Mar 20, 2026
Final Rejection — §102, §103 (current)

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