DETAILED ACTION
This office action is in response to amendment filed 3/30/2026.
Claims 1, 3-16, and 18-20 are pending. Claims 2 and 17 have been canceled. Claims 5-8, 13-16, and 20 have been withdrawn. Claims 1, 3-5, 8-9, 13-16, and 18-20 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4, 9-12, and 18-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “an orthographic projection of the second semiconductor layer on the substrate overlaps with an orthographic projection of the raised portion on the substrate; the raised portion of the light-emitting chip is formed by the second semiconductor layer” renders the claim indefinite. Firstly, it is unclear if “an orthographic projection of the raised portion on the substrate” is same as the “orthographic projection of the raised portion on the substrate” previously recited in the claim. Proper antecedent basis should be provided if they are intended to refer to the same “orthographic projection of the raised portion on the substrate”.
Claims 3 and 18 reciting “a region where the auxiliary bonding layers is located” renders the claim indefinite. It is unclear if the “the auxiliary bonding layers” is referring to one of the “at least two auxiliary bonding layers” or all of the “at least two auxiliary bonding layers”. Furthermore, it is unclear if the region refers to where all of the “at least two auxiliary bonding layers” are located.
Claim 9 reciting “the auxiliary bonding layers” renders the claim indefinite. It is unclear if the “the auxiliary bonding layers” is referring to one of the “at least two auxiliary bonding layers” or all of the “at least two auxiliary bonding layers”.
Claim 19 reciting “the raised portion of the light-emitting chip is formed by the second semiconductor layer” repeats a limitation already recited in claim 1.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 9-12, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aketa et al. US 2016/0218262 A1 (Aketa).
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In re claim 1, as best understood, Aketa discloses (e.g. FIGs. 13-18 & 25) a light-emitting chip 1d, comprising:
a substrate 10;
a light-emitting structure 19, the light-emitting structure disposed on a side of the substrate 10;
a reflective layer (including 141,151 and 18, where 18 is a reflective dielectric multilayer, ¶ 104), the reflective layer 141+151+18 disposed on a side, facing away from the substrate 10, of the light-emitting structure 19;
at least two auxiliary bonding layers 142+31 (four total at each of the four corners, see FIG. 15), the at least two auxiliary bonding layers 142+31 disposed on a side, facing away from the light-emitting structure 19, of the reflective layer 141+151+18; and
a raised portion (portion of 18 between electrodes 141,151 and raised above the surface 12a of the semiconductor layer 12, see annotated in FIG. 13 above), the raised portion disposed on a side, facing away from the light-emitting structure 19, of the reflective layer 141+151+18 (such interpretation is consistent with Applicant’s disclosure, see FIG. 4A, describing the “raised portion” 30 being an elevated portion of reflective layer 3 above semiconductor layer 22);
wherein an orthographic projection of the raised portion 18 (between 141 and 151 and on surface 12a) on the substrate and an orthographic projection of the at least two auxiliary bonding layers 142+31 on the substrate do not overlap with each other; and
a thickness of the raised portion (portion of 18 between 141 and 151 and on surface 12a) is smaller than a thickness of each of the at least two auxiliary bonding layers 142+31;
an orthographic projection of the light-emitting structure 19 on the substrate overlaps with the orthographic projection of the raised portion (portion of 18 between 141 and 151 and above semiconductor layer 12) on the substrate;
wherein the light-emitting structure 19 comprises a first semiconductor layer 11, a light-emitting layer 13, and a second semiconductor layer 12; the first semiconductor layer 11, the light-emitting layer 13, and the second semiconductor layer 12 are sequentially stacked on a side of the substrate 10; and
an orthographic projection of the second semiconductor layer 12 on the substrate overlaps with an orthographic projection of the raised portion (portion of 18 between 141 and 151 and on surface 12a) on the substrate;
the raised portion 18 (portion of 18 between 141 and 151 and above semiconductor layer 12) of the light-emitting chip is “formed by” the second semiconductor layer 12 (as best understood, the raised portion of 18 is formed above surface 12a of semiconductor layer 12 and is thus understood to by “formed by” the shape/pattern of the semiconductor layer 12 similar to Applicant’s own disclosure to the raised portion 30 being “formed by” the second semiconductor layer 22 as shown in FIG. 4A);
the orthographic projection of the second semiconductor layer 12 on the substrate does not overlap with the orthographic projection of the at least two auxiliary bonding layers 142+31 on the substrate (see FIG. 15, the orthographic projection of the four auxiliary bonding layers 142+31 correspond to the orthographic projection of 14 at the four corners shown in FIG. 15 which does not overlap the orthographic projection of second semiconductor layer 12 since 14 provided on the exposed surface 11a of the first semiconductor layer 11 where the second semiconductor layer 12 is removed, ¶ 95).
In re claim 3, as best understood, Aketa discloses (e.g. FIGs. 13 & 25) wherein a thickness of the reflective layer 18 in a region 12a (region of surface 12a of the second semiconductor layer 22) where the raised portion 18 (portion of 18 between 141 and 151 and on surface 12a of semiconductor layer 12) is located is approximately equal to a thickness of the reflective layer 18 in “a region 11a (region of the exposed surface 11a of the first semiconductor layer 1) where the auxiliary bonding layers 142+31 is located (thickness of layer 18 on the region/surface 12a is the same as the thickness of layer 18 on the region/surface 11a)”.
In re claim 4, Aketa discloses (e.g. FIGs. 13 & 25) wherein the light-emitting chip is a light-emitting chip emitting red light (¶ 92);
the first semiconductor layer 11 is a P-type semiconductor layer (¶ 90); and
the second semiconductor layer 12 is an N-type semiconductor layer (¶ 90).
In re claim 9, as best understood, Aketa discloses (e.g. FIGs. 13-18 & 25) a light-emitting substrate B3,B6, comprising the light-emitting chip 1d according to claim 1, and further comprising a circuit substrate 2d,2g;
wherein the circuit substrate 2d,2g comprises a plurality of sub-substrate pads 211,212,51 (position at four corners, see FIG. 17), and the sub-substrate pads 211,212,51 are soldered to “the auxiliary bonding layers” 31 in a one-to-one corresponding manner.
In re claim 10, Aketa discloses (e.g. FIG. 25) wherein the circuit substrate 2g is provided with a substrate bulge 17 between adjacent sub-substrate pads 211,212,51 (between bonding portions of pads at four corners), the substrate bulge 17 making contact with the raised portion (including portion of 18) between 14 and 15).
In re claim 11, Aketa discloses (e.g. FIGs. 13 & 25) wherein the circuit substrate 2d,2g is provided with a plurality of recessed regions (recessed surface 21a) in regions where the sub-substrate pads 211,212-,51 are located.
In re claim 12, Aketa discloses (e.g. FIGs. 13 & 25) a display device, comprising the light-emitting substrate according to claim 9. No specific “display device” is claimed that would structurally distinguish over the device taught by Aketa used to display optical signal.
In re claim 18, as best understood, Aketa discloses (e.g. FIGs. 13 & 25) wherein a thickness of the reflective layer 18 in a region 12a (region of surface 12a of the second semiconductor layer 22) where the raised portion 18 (portion of 18 between 141 and 151 and on surface 12a of semiconductor layer 12) is located is approximately equal to a thickness of the reflective layer 18 in “a region 11a (region of the exposed surface 11a of the first semiconductor layer 1) where the auxiliary bonding layers 142+31 is located (thickness of layer 18 on the region/surface 12a is the same as the thickness of layer 18 on the region/surface 11a)”.
In re claim 19, as best understood, Aketa discloses (e.g. FIGs. 13 & 25) wherein the light-emitting chip is a light-emitting chip emitting red light (¶ 92);
the first semiconductor layer 11 is a P-type semiconductor layer (¶ 90); and
the second semiconductor layer 12 is an N-type semiconductor layer (¶ 90);
“wherein the raised portion 18 (portion of 18 between 141 and 151 and above semiconductor layer 12) of the light-emitting chip is “formed by” the second semiconductor layer 12 (as best understood, the raised portion of 18 is formed on surface 12a of semiconductor layer 12 and is thus understood to by “formed by” the shape/pattern of the semiconductor layer 12 similar to Applicant’s own disclosure to the raised portion 30 being “formed by” the second semiconductor layer 22 as shown in FIG. 4A)”.
Response to Arguments
Applicant's arguments filed 3/30/2026 have been fully considered but they are not persuasive.
Regarding Aketa, Applicant argues Aketa fails to teach “the orthographic projection of the second semiconductor layer on the substrate does not overlap with the orthographic projection of the at least two auxiliary bonding layers on the substrate (Remark, pages 9-10).
This is not persuasive. Aketa teaches four auxiliary bonding layers including elements 142,31 at the respective four corners of the light emitting chip (see FIG. 15). Thus, the orthographic projection of the at least two auxiliary bonding layers 142,31 on the substrate correspond to the orthographic projection of 14 at the four corners shown in FIG. 15. These element 142,31 are provided on the exposed surface 11a of the first semiconductor layer 11 where the second semiconductor layer 12 is removed by etching. Therefore, the orthographic projection of the second semiconductor layer 12 on the substrate does not overlap with the orthographic projection of the at least two auxiliary bonding layers 142,31 on the substrate (¶ 95).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights