Prosecution Insights
Last updated: October 02, 2026
Application No. 18/026,465

ARRAY BASEPLATE AND PREPARATION METHOD THEREOF, AND DISPLAY DEVICE

Non-Final OA §103
Filed
Mar 15, 2023
Priority
Jun 15, 2022 — nonprovisional of PCTCN2022098989
Examiner
ALBRECHT, PETER M
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
3 (Non-Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
75%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
360 granted / 504 resolved
+3.4% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
22 currently pending
Career history
524
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
46.7%
+6.7% vs TC avg
§102
18.1%
-21.9% vs TC avg
§112
34.0%
-6.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 504 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 13, 2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0318632 A1 (hereinafter “Simin”) in view of US 2014/0264266 A1 (hereinafter “Li”). Regarding claim 1, Simin discloses in Fig. 15 and related text an array baseplate, comprising: a substrate (112; [0082] and [0089]); a drive unit (138; [0093]) disposed on one side (140; [0093]) of the substrate; and a light-emitting unit (150; [0089]; note: “SSLS” stands for solid-state light source) comprising at least one light-emitting subunit and disposed on a side (110; [0089]) of the substrate away from the drive unit, wherein the light-emitting unit is electrically connected to the drive unit through a wiring (132, 134; [0093]) penetrating the substrate, and at least part area of each light-emitting subunit is in direct contact with the substrate; wherein the array baseplate comprises a first wiring (132; [0093]) and a second wiring (134; [0093]), the light-emitting subunit comprises a semiconductor layer (14, 16, 18; [0057]-[0058] and [0089]); the first wiring and the second wiring are electrically connected to the semiconductor layer ([0093]), and the first wiring and the second wiring are electrically connected to the drive unit ([0093]); at least part area of the semiconductor layer is in direct contact with the substrate; at least part area of at least one wiring of the first wiring and the second wiring passes through the substrate and extends to the side of the substrate disposing the drive unit, and is electrically connected to the drive unit ([0093]); the light-emitting unit comprises one light-emitting subunit, the substrate is provided with a first through hole (136 (the via hole on the left); [0093]) and a second through hole (136 (the via hole on the right); [0093]), at least part area of the first wiring is located in the first through hole, and at least part area of the second wiring is located in the second through hole; and the first wiring is located in the first through hole, a part area of the second wiring is located on a side of the semiconductor layer away from the substrate, and the other part area of the second wiring is located in the second through hole. Simin does not explicitly disclose the semiconductor layer is an epitaxial layer. Li teaches in Fig. 1 and related text the semiconductor layer (12, 13, 14; [0059]) is an epitaxial layer. Li employs a metal organic vapor phase epitaxy process to epitaxially grow three gallium nitride based semiconductor sublayers on a silicon carbide substrate, for example ([0059]). Simin discloses that the substrate (112) may be made of silicon carbide ([0082]) and the semiconductor sublayers (14, 16, 18) may be made of group III-nitride semiconductor materials ([0057]-[0058]). Simin and Li are analogous art because they both are directed to light-emitting diodes including III-nitride semiconductor materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Simin with the specified features of Li because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the semiconductor layer to be an epitaxial layer, as taught by Li, in order to obtain a crystalline semiconductor layer, which provides organized atomic structures that prevent defects from trapping energy, ensure smooth flow of electricity, and allow efficient light production. Regarding claim 10, Simin in view of Li disclose a material of the substrate comprises silicon (Simin: [0082]). Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER M ALBRECHT/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Show 1 earlier event
Aug 20, 2025
Response after Non-Final Action
Nov 05, 2025
Non-Final Rejection (signed) — §103
Dec 16, 2025
Non-Final Rejection mailed — §103
Mar 13, 2026
Response Filed
Apr 13, 2026
Final Rejection mailed — §103
Jul 13, 2026
Request for Continued Examination
Jul 14, 2026
Response after Non-Final Action
Aug 05, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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DISPLAY SUBSTRATE, MANUFACTURING METHOD, AND DISPLAY DEVICE
3y 2m to grant Granted Sep 29, 2026
Patent 12745503
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Patent 12740144
DISPLAY APPARATUS
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Patent 12740215
Integrated photodiode manufacturing method, a photodiode, and a photoelectric keyboard
2y 9m to grant Granted Sep 15, 2026
Patent 12733197
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4y 2m to grant Granted Sep 08, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
75%
With Interview (+3.8%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 504 resolved cases by this examiner. Grant probability derived from career allowance rate.

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