DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16 and 27 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 16 recites the limitation “a single bond layer that directly contacts both the substrate and the base plate, the single bond layer being the only bond layer between the metallization layer of the substrate and the base plate”. The instant specification and drawings do not provide sufficient support for this limitation. The specification does not outline an embodiment where specifically the single bond layer is the only bond layer between the metallization layer of the substrate and the base plate, and the drawings only show a single bond layer in cross-sectional view. Thus, it is unclear whether there may be other additional bond layers between the substrate and base plate in other cross-sections of the device. Further, based on the other claim limitations of claim 16 the metallization layer is believed to be drawn to the first metallization layer 5 in the drawings, it could be argued that intervening layers such as the second metallization layer 7 or the electrical insulating layer 6 are also considered as bonding layers in addition to the bond layer 11, since they also attach the first metallization layer 5 to the base plate 9. Thus, new matter has been introduced to the claims.
Similarly, claim 27 recites the limitation “the single layer being the only bond layer between the metallization layer on the first side of each power semiconductor module and the base plate”. For the same reasons as claim 16, new matter has been introduced to the claims.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 recites the limitation "the single layer" in line 10. There is insufficient antecedent basis for this element in the claim.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 36-38 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ueda et al. (“Ueda” US 2012/0313252).
Regarding claim 36, Ueda discloses a power module (Figure 16) comprising:
a power semiconductor module (102/110) having a substrate (102) that comprises an electrical insulating layer (104), a first metallization layer (106) on an upper surface of the electrical insulating layer (104, see Figure 16), and a second metallization layer (108) on a lower surface of the electrical insulating layer (104, see Figure 16), the power semiconductor module also having a semiconductor chip (110) arranged on the upper surface of the electrical insulating layer (104) and electrically connected to the first metallization layer (106);
a base plate (120C) comprising cooling structures (outer surfaces of the base plate 120C is considered cooling structures since they radiate heat away from the chips);
a bond layer (130) formed of a bonding material (solder, para. [0059]) that directly contacts and bonds to both the second metallization layer (108) on the lower surface of the electrical insulating layer (104) and an upper surface of the base plate (120C, see Figure 16); and
a mold compound (140) arranged on the power semiconductor module (102/110) and the base plate (120C), wherein the bond layer (130) is encapsulated completely by direct contact with the power semiconductor module (102/110) from above and direct contact with the base plate (120C) from below (see Figure 16), and wherein the mold compound (140) seals lateral edges of the bond layer (130, see Figure 16) such that the bond layer (130) has no outer surface that is freely accessible (see Figure 16).
Regarding claim 37, Ueda discloses wherein the bond layer (130) is a solder layer (solder, para. [0059]) or a sinter layer that metallurgically bonds directly to both the second metallization layer (108) and the upper surface of the base plate (120C) and wherein the bond layer (130) provides a thermal conduction path from the power semiconductor module (102/110) to the base plate (120C, see Figure 16, since the bond layer is between the module and the base plate and the module generates heat while the base plate dissipated heat, the bond layer provides a thermal conductive path).
Regarding claim 38, Ueda discloses wherein the mold compound (140) directly contacts and seals against a side surface of the power semiconductor module (102/110, see Figure 16), the lateral edges of the bond layer (130), and a side surface of the base plate (120C) adjacent to the upper surface (see Figure 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-23 and 27-30 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda et al. (“Ueda” US 2012/0313252) and Nishi et al. (“Nishi” US 2013/0264702).
Regarding claim 16, Ueda discloses a power module (Figure 16) comprising:
a power semiconductor module (102/110) having a substrate (102) that includes an electrically insulating layer (104) and a metallization layer (106), the power semiconductor module (102/110) also having a semiconductor chip (110) arranged on the substrate (102) and electrically connected to the metallization layer (106);
a lead frame (112) arranged in electrical contact with the semiconductor chip (110);
a base plate (120C);
a single bond layer (130) that directly contacts both the substrate (102) and the base plate (120C, see Figure 16), the single bond layer (130) being the only bond layer between the metallization layer (106) of the substrate (102) and the base plate (120C, see Figure 16, the bond layer 130 is the only layer specifically for adhering the substrate to the base plate); and
a mold compound (140) arranged on the power semiconductor module (102/110, see Figure 16), the bond layer (130) and the base plate (120C), wherein the bond layer (130) is encapsulated completely by the power semiconductor module, the base plate (120C) and the mold compound (140, see Figure 16) and wherein the lead frame (112) is arranged at least partially within the mold compound (140, see Figure 16).
Ueda does not explicitly teach a base plate comprising cooling structures and micro channels that are connected to an inlet port and an outlet port;
Nishi teaches a base plate (30/61/62) comprising cooling structures (61) and micro channels (62) that are connected to an inlet port and an outlet port (not shown in Figure 1, supply pipe and discharge pipe are disclosed in para. [0023]).
It would have been obvious to a person having ordinary skill in the art to combine the teachings of Nishi into the teachings of Ueda to include the base plate with cooling structures and micro channels for the purpose of further enhancing heat dissipation by a flowing coolant (Nishi, para. [0022]).
Regarding claim 17, Ueda teaches wherein the bond layer (130) comprises a solder layer or a sinter layer (solder, para. [0059]).
Regarding claim 18, Ueda teaches wherein the mold compound (140) is in direct contact on a side surface of the base plate (120C) at least in places (see Figure 16).
Regarding claim 19, Ueda teaches wherein the substrate (102) further comprises:
a second metallization layer (108), wherein the electrical insulating layer (104) is arranged between the metallization layer (106) and the second metallization layer (108, see Figure 16).
Regarding claim 20, Ueda teaches wherein:
the base plate (120C) has a protruding part (edge portions) protruding beyond the bond layer (130) in lateral directions (see Figure 16); and
the mold compound (140) is in direct contact with an outer surface of the protruding part (edge portions, see Figure 16).
Regarding claim 21, Nishi teaches wherein the cooling structures (61) comprise pin fins (see Figure 1 and para. [0022]).
Regarding claim 22, Ueda teaches wherein the base plate (120C) comprises interlocking features (surfaces 126) configured to fix the mold compound (140) to the base plate (120C, see para. [0123], the surfaces 126 prevent cracking thus are configured to keep the mold compound fixed to the base plate).
Regarding claim 23, Ueda teaches wherein the power module comprises a plurality of power semiconductor modules arranged spaced apart from one another (see Figure 11), the mold compound (140) being arranged on the power semiconductor modules (see Figure 11).
Regarding claim 27, Ueda teaches a power module (Figure 16) comprising:
a plurality of power semiconductor modules (102/110, see Figures 16 and 11), each power semiconductor module having a substrate (102, Figure 16) that includes a metallization layer (106) on a first side of the substrate (upper side), and a plurality of semiconductor chips (110) arranged on the metallization layer (106) on the first side of the substrate (upper side, see Figure 16);
a lead frame (112) arranged in electrical contact with the semiconductor chips (110);
a base plate (120C);
a bond layer (130) connecting the power semiconductor modules (102/110) and the base plate (120C, see Figure 16), the bond layer (130) comprising a single layer that directly contacts the substrate (102) of each power semiconductor module (102/110) and the base plate (120C, see Figure 16), the single layer being the only bond layer between the metallization layer (106) on the first side of each power semiconductor module and the base plate (120C, see Figure 16, the bond layer 130 is the only layer adhering the substrate to the base plate); and
a mold compound (140) arranged on the power semiconductor module (102/110, see Figure 16), the bond layer (130) and the base plate (120C), wherein the bond layer (130) is encapsulated completely by the power semiconductor module (102/110), the base plate (120C) and the mold compound (140, see Figure 16) and wherein the lead frame (112) is arranged at least partially within the mold compound (140, see Figure 16).
Ueda does not explicitly teach a base plate comprising cooling structures and also comprising micro channels that are connected to an inlet port and an outlet port;
Nishi teaches a base plate (30/61/62) comprising cooling structures (61) and also comprising micro channels (62) that are connected to an inlet port and an outlet port (not shown in Figure 1, supply pipe and discharge pipe are disclosed in para. [0023]).
It would have been obvious to a person having ordinary skill in the art to combine the teachings of Nishi into the teachings of Ueda to include the base plate with cooling structures and micro channels for the purpose of further enhancing heat dissipation by a flowing coolant (Nishi, para. [0022]).
Regarding claim 28, Ueda teaches wherein the semiconductor chips (110) include a first semiconductor chip comprising a switch and a second semiconductor chip comprising a diode (see para. [0005], [0097]-[0098]), the switch and the diode being connected antiparallel to one another to form a half bridge (para. [0097]).
Regarding claim 29, Ueda teaches wherein:
the base plate (120C) has a protruding part (edge portions) protruding beyond the bond layer (130) in lateral directions (see Figure 16); and
the mold compound (140) is in direct contact with an outer surface of the protruding part (edge portions, see Figure 16).
Regarding claim 30, Ueda teaches wherein the base plate (120C) comprises interlocking features (surfaces 126) configured to fix the mold compound (140) to the base plate (120C, see para. [0123], the surfaces 126 prevent cracking thus are configured to keep the mold compound fixed to the base plate).
Claims 24-25 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Ueda and Nishi as applied to claims 23 and 27 above, and further in view of Yu et al. (“Yu” US 2015/0371969).
Regarding claim 24, Ueda does not explicitly disclose that the mold compound comprises a recess between two of the power semiconductor modules.
However, Yu discloses a mold compound (106) that comprises a recess (120) between two dice (112, see Figure 5, para. [0031]).
It would have been obvious to one having ordinary skill in the art to incorporate recesses in the mold compound between devices as taught by Yu into the teachings of Ueda and Nishi for the purpose of mitigating warpage (Yu, para. [0031]).
Regarding claim 25, Yu discloses wherein the recess (120) does not penetrate the mold compound (106) completely (see Figure 5).
Regarding claim 31, Yu teaches wherein the mold compound (106) comprises a recess (120) between two of the power semiconductor modules (analogous to dice 112).
It would have been obvious to one having ordinary skill in the art to incorporate recesses in the mold compound between devices as taught by Yu into the teachings of Ueda and Nishi for the purpose of mitigating warpage (Yu, para. [0031]).
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over Ueda as applied to claim 36 above, and further in view of Nishi et al. (“Nishi” US 2013/0264702).
Regarding claim 39, Nishi teaches a base plate (30/61/62) comprising micro channels (62) embedded within the base plate (30/61/62, see Figure 1) and connected to an inlet port and an outlet port for circulating coolant (supply pipe and discharge pipe connected to the microchannels 62, through which coolant circulates, see para. [0023]).
It would have been obvious to a person having ordinary skill in the art to combine the teachings of Nishi into the teachings of Ueda to include the base plate with cooling structures and micro channels for the purpose of further enhancing heat dissipation by a flowing coolant (Nishi, para. [0022]).
The combination of Ueda and Nishi results in a configuration where the bond layer (130 of Ueda) extends across a region of the base plate (120C) directly above the micro channels (62 of Nishi). Since Nishi’s microchannels are integrated into the base plate of Ueda, the bond layer would be directly above the microchannels.
Response to Arguments
Applicant’s arguments with respect to the prior art rejections have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
