DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 6 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 36 and 38-39 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishi et al. (“Nishi” US 2013/0264702).
Regarding claim 36, Nishi discloses in the embodiment of Figure 1 a power module comprising:
a power semiconductor module (10/20/14) having a semiconductor chip (20) arranged on a substrate (10/14, see Figure 1);
a base plate (30/61/62) comprising cooling structures (61);
a bond layer (metal bonding layer between stress relief member 14 of the substrate 10/14 and the heat sink 30, see para. [0019]) formed of a bonding material (brazed metal material, which is a common bonding material, see para. [0019]) that directly contacts and bonds to both a lower surface of the substrate (10/14, the metal bonding layer is directly between the stress relief member 14 of the substrate 10/14 and the heat sink 30) and an upper surface of the base plate (30/61/62, see para. [0019] which discloses the stress relief member 14 of the substrate 10/14 is directly bonded to the base plate 30/61/62 through the metal bonding layer, thus the metal bonding layer, i.e. the claimed bond layer, is in direct contact with the upper surface of the base plate 30/61/62 and the lower surface of the substrate 10/14), wherein the bond layer (metal bonding layer, para. [0019]) provides a thermal conduction path from the power semiconductor module (10/20/14) to the base plate (30/61/62, since the bond layer, the metal bonding layer, is between the heat source, i.e. the semiconductor chip 20, and the means for heat dissipation, i.e. the base plate and cooling structures 30/61/62, the bond layer thus provides a thermal conduction path from the power semiconductor module to the base plate); and
a mold compound (70) arranged on the power semiconductor module (10/20/14) and the base plate (30/61/62, see Figure 1), wherein the bond layer (metal bonding layer, para. [0019]) is encapsulated completely by direct contact with the power semiconductor module (10/20/14) from above (see Figure 1 and para. [0019]) and direct contact with the base plate (30/61/62) from below (see Figure 1 and para. [0019]), and wherein the mold compound (70) seals lateral edges of the bond layer (metal bonding layer para. [0019]) such that the bond layer (metal bonding layer, para. [0019]) has no outer surface that is freely accessible (Figure 1 shows the mold compound 70 laterally surrounding the base plate portion 30 and the entire power semiconductor module 10/20/14, and the metal bonding layer, i.e. the claimed bond layer, is used to bond the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62 together, thus is located between the stress relief member 14 and the base plate 30/61/62, thus upper and lower surfaces of the bond layer would be entirely encapsulated by the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62 and the lateral edges of the bond layer would be encapsulated/sealed by the mold compound 70).
Regarding claim 38, Nishi discloses wherein the mold compound (70) directly contacts and seals against a side surface of the power semiconductor module (10/20/14, see Figure 1), the lateral edges of the bond layer (metal bonding layer on lower surface of stress relief member 14 of the substrate 10/14, see Figure 1 and para. [0019], Figure 1 shows the mold compound 70 laterally surrounding the base plate portion 30 and the entire power semiconductor module 10/20/14, and the metal bonding layer, i.e. the claimed bond layer, is used to bond the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62 together, thus is located between the stress relief member 14 and the base plate 30/61/62, thus upper and lower surfaces of the bond layer between the stress relief member and the heat sink 30 of the base plate would be entirely encapsulated by the stress relief member 14 and the base plate 30/61/62 and the lateral edges of the bond layer would be encapsulated/sealed by and in direct contact with the mold compound 70), and a side surface of the base plate (30/61/62) adjacent to the upper surface (the side surface of the base plate 30/61/62 adjacent to the upper surface of the base plate 30/61/62 is the lateral edge surfaces of elements 40 and 50, which constitute element 30, which directly contact the mold compound, see Figure 1).
Regarding claim 39, Nishi discloses:
the base plate (30/61/62) comprises micro channels (62) embedded within the base plate (30/61/62, see Figure 1) and connected to an inlet port and an outlet port for circulating coolant (supply pipe and discharge pipe connected to the microchannels 62, through which coolant circulates, see para. [0023]); and
the bond layer (metal bonding layer between stress relief member 14 of the substrate 10/14 and the heat sink 30 of the base plate, para. [0019]) extends across a region of the base plate (30/61/62) directly above the micro channels (62, see Figure 1, the metal bonding layer, i.e. the claimed bond layer, is used to bond the stress relief member 14 and the base plate 30/61/62 together, thus is located between the stress relief member 14 and the base plate 30/61/62, thus the bond layer is located in a region across the base plate that is directly above the microchannels, see Figure 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 37 is rejected under 35 U.S.C. 103 as being unpatentable over Nishi as applied to claim 36 above, and further in view of Pavier et al. (“Pavier” US Patent No. 10,074,590).
Regarding claim 17, Nishi does not disclose that the bond layer is a solder layer or a sinter layer that metallurgically bonds directly to both the lower surface of the substrate and the upper surface of the base plate, rather the bond layer of Nishi (metal bonding layer between the stress relief member 14 of the substrate 10/14 and the base plate, para. [0019]) is a brazed layer.
However, Pavier discloses in col. 5, lines 62-67 a bond layer (sintered layer in col. 5, lines 62-67) is a solder layer or a sinter layer (sinter layer) that metallurgically bonds directly to both the lower surface of the substrate (which comprises an electrically conductive layer that faces away from the electronic chip, thus is a lower surface/layer of the substrate) and the upper surface of the base plate (heat sink, col. 5, lines 62-67, Pavier discloses using a sinter layer to bond a lower surface of an electrically conductive layer facing away from the electronic chip, thus is a lower surface of a conductive layer of a substrate, to a heat sink).
It would have been obvious to one having ordinary skill in the art to incorporate a sinter layer as taught by Pavier into the brazed bond layer of Nishi for the purpose of utilizing a bonding technique that provides high thermal conductivity (see Pavier, col. 14 line 66 to col. 15 line 3).
Claims 16, 18-23, 27, and 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over multiple embodiments of Nishi et al. (“Nishi” US 2013/0264702).
Regarding claim 16, Nishi discloses, in the embodiment of Figure 1 a power module (Figure 1) comprising:
a power semiconductor module (10/20/14) having a semiconductor chip (20) arranged on a substrate (10/14, see Figure 1);
a base plate (30/61/62) comprising cooling structures (61) and micro channels (62) that are connected to an inlet port and an outlet port (not shown in Figure 1, supply pipe and discharge pipe are disclosed in para. [0023]);
a bond layer (metal bonding layer between the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62 and bonding them together, see para. [0019]) connecting the power semiconductor module (10/20/14) and the base plate 30/61/62, see Figure 1 and para. [0019], a brazed metal bonding layer is used to bond the stress relief member 14 of the substrate 10/14 to the base plate 30/61/62), the bond layer (metal bonding layer para. [0019]) comprising a single layer (single metal bonding layer between the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62, thus is a single layer) that directly contacts both the substrate (10/14, see para. [0019]) and the base plate (30/61/62, the metal bonding layer, i.e. the claimed bond layer, is used to bond the stress relief member 14 of the substrate 10/14 to the base plate 30/61/62, see para. [0019], thus would be in direct contact with both elements); and
a mold compound (70) arranged on the power semiconductor module (10/20/14), the bond layer (metal bonding layer between stress relief member 14 of the substrate 10/14 and the heat sink 30 of the base plate, para. [0019]) and the base plate (30/61/62), wherein the bond layer (metal bonding layer between stress relief member 14 of the substrate 10/14 and the heat sink 30 of the base plate, para. [0019]) is encapsulated completely by the power semiconductor module (10/20/14), the base plate (30/61/62) and the mold compound (70, see Figure 1, Figure 1 shows the mold compound 70 laterally surrounding the base plate portion 30 and the entire power semiconductor module 10/20/14, and the metal bonding layer between stress relief member 14 of the substrate 10/14 and the heat sink 30 of the base plate, i.e. the claimed bond layer, is used to bond the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62 together, thus is located between the stress relief member 14 and the base plate 30/61/62, thus upper and lower surfaces of the bond layer would be entirely encapsulated by the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62 and the lateral edges of the bond layer would be encapsulated/sealed by the mold compound 70, thereby encapsulating the bond layer completely).
Nishi discloses, in the embodiment of Figures 2A/2B:
a lead frame (86) arranged in electrical contact with the semiconductor chip (83);
and wherein the lead frame (86) is arranged at least partially within the mold compound. (70, see Figure 2B).
It would have been obvious to one having ordinary skill in the art to combine the teachings of Nishi’s Figure 1 and Figure 2A/2B to include a lead frame (86) as claimed for the purpose of providing external electrical connection of a power source to the semiconductor device (Nishi, para. [0037]).
Regarding claim 18, Nishi discloses wherein the mold compound (70) is in direct contact on a side surface of the base plate (30/61/62) at least in places (see Figure 1).
Regarding claim 19, Nishi discloses wherein the substrate (10/14) comprises:
a first metallization layer (12, para. [0015]);
a second metallization layer (13, para. [0015]); and
an electrical insulating layer (11, para. [0015]) arranged between the first metallization layer (12) and the second metallization layer (13, see Figure 1).
Regarding claim 20, Nishi discloses wherein:
the base plate (30/61/62) has a protruding part (53) protruding beyond the bond layer (metal bonding layer para. [0019] between stress relief member 14 of the substrate 10/14 and the heat sink 30 of the base plate) in lateral directions (see Figure 1); and
the mold compound (70) is in direct contact with an outer surface of the protruding part (see Figure 1).
Regarding claim 21, Nishi discloses wherein the cooling structures (61) comprises pin fins (see Figure 1 and para. [0022]).
Regarding claim 22, Nishi discloses wherein the base plate (30/61/62) comprises interlocking features (43) configured to fix the mold compound (70) to the base plate (30/61/62, extension 43 serves to prevent detachment of the mold compound 70 due to thermal expansion, see para. [0034]).
Regarding claim 23, Nishi does not explicitly disclose that the power module comprises a plurality of power semiconductor modules arranged spaced apart from one another, but does disclose that the mold compound (70) is arranged on the power semiconductor module[s] (10/20, see Figure 1).
However, it would have been obvious to one having ordinary skill in the art to include a plurality of semiconductor modules because mere duplication of parts has no patentable significance unless a new and unexpected result is produced, which Applicant has not disclosed in the instant specification. See MPEP 2144.04(VI)(B).
Regarding claim 27, Nishi discloses in the embodiment of Figure 1 a power module comprising:
a [plurality of power semiconductor modules, each] power semiconductor module (10/20/14, Figure 1) having a plurality of semiconductor chips (20) arranged on a substrate (10/14, see Figure 1);
a base plate (30/61/62) comprising cooling structures (61) and also comprising micro channels (62) that are connected to inlet ports and outlet ports (not shown in Figure 1, supply pipe and discharge pipe disclosed in para. [0023]);
a bond layer (metal bonding layer between the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62 and bonding them together, see para. [0019]) connecting the power semiconductor modules (10/20/14) and the base plate (30/61/62, see Figure 1 and para. [0019]), the bond layer (metal bonding layer between the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62, para. [0019]) comprising a single layer (single metal bonding layer between the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62, thus is a single layer) that directly contacts the substrate (10/14, the metal bonding layer is on a lower surface of the stress relief member 14 of the substrate, see para. [0019]) of each power semiconductor module (10/20/14) and the base plate (30/61/62, the metal bonding layer, i.e. the claimed bond layer, is used to bond the stress relief member 14 of the substrate 10/14 to the base plate 30/61/62, see para. [0019], thus would be in direct contact with both elements); and
a mold compound (70) arranged on the power semiconductor modules (10/20/14), the bond layer (metal bonding layer para. [0019] between elements 14 and 30) and the base plate (30/61/62, see Figure 1), wherein the bond layer (metal bonding layer between elements 14 and 30, para. [0019]) is encapsulated completely by the power semiconductor modules (10/20/14), the base plate (30/61/62) and the mold compound (70, see Figure 1, Figure 1 shows the mold compound 70 laterally surrounding the base plate portion 30 and the entire power semiconductor module 10/20/14, and the metal bonding layer, i.e. the claimed bond layer, is used to bond the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62 together, thus is located between the stress relief member 14 of the substrate 10/14 and the base plate 30/61/62, thus upper and lower surfaces of the bond layer would be entirely encapsulated by the stress relief member 14 of the substrate 10/14 which is a part of the power semiconductor module 10/20/14, and the base plate 30/61/62, and the lateral edges of the bond layer would be encapsulated/sealed by the mold compound 70, thereby encapsulating the bond layer completely).
Nishi discloses, in the embodiment of Figures 2A/2B:
a lead frame (86) arranged in electrical contact to with the semiconductor chips (83, 84);
and wherein the lead frame (86) is arranged at least partially within the mold compound (70, see Figure 2B).
It would have been obvious to one having ordinary skill in the art to combine the teachings of Nishi’s Figure 1 and Figure 2A/2B to include a lead frame (86) as claimed for the purpose of providing external electrical connection of a power source to the semiconductor device (Nishi, para. [0037]).
While Nishi does not explicitly disclose a plurality of semiconductor modules, it would have been obvious to one having ordinary skill in the art to include a plurality of semiconductor modules because mere duplication of parts has no patentable significance unless a new and unexpected result is produced, which Applicant has not disclosed in the instant specification. See MPEP 2144.04(VI)(B).
Regarding claim 29, Nishi discloses wherein:
the base plate (30/61/62) has a protruding part (53) protruding beyond the bond layer (metal bonding layer between the stress relief member 14 of the substrate 10/14 and the heat sink 30 of the base plate, para. [0019], thus would be within the bounds of the protruding part 53) in lateral directions (see Figure 1); and
the mold compound (70) is in direct contact with an outer surface of the protruding part (see Figure 1).
Regarding claim 30, Nishi discloses wherein the base plate (30/61/62) comprises interlocking features (43) configured to fix the mold compound (70) to the base plate (30/61/62, extension 43 serves to prevent detachment of the mold compound 70 due to thermal expansion, see para. [0034]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Nishi as applied to claim 16 above, and further in view of Pavier et al. (“Pavier” US Patent No. 10,074,590).
Regarding claim 17, Nishi does not disclose that the bond layer comprises a solder layer or a sinter layer, rather that the bond layer (metal bonding layer, para. [0019]) is a brazed layer (see para. [0019]).
However, Pavier discloses in col. 5, lines 62-67 a bond layer (sintered layer in col. 5, lines 62-67) is a solder layer or a sinter layer (sinter layer) that metallurgically bonds directly to both the lower surface of the substrate (which comprises an electrically conductive layer that faces away from the electronic chip, thus is a lower surface/layer of the substrate) and the upper surface of the base plate (heat sink, col. 5, lines 62-67, Pavier discloses using a sinter layer to bond a lower surface of an electrically conductive layer facing away from the electronic chip, thus is a lower surface of a conductive layer of a substrate, to a heat sink).
It would have been obvious to one having ordinary skill in the art to incorporate a sinter layer as taught by Pavier into the brazed bond layer of Nishi for the purpose of utilizing a bonding technique that provides high thermal conductivity (see Pavier, col. 14 line 66 to col. 15 line 3).
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Nishi as applied to claim 23 above, and further in view of Yu et al. (“Yu” US 2015/0371969).
Regarding claim 24, Nishi does not explicitly disclose that the mold compound comprises a recess between two of the power semiconductor modules.
However, Yu discloses a mold compound (106) that comprises a recess (120) between two dice (112, see Figure 5, para. [0031]).
It would have been obvious to one having ordinary skill in the art to incorporate recesses in the mold compound between devices as taught by Yu into the teachings of Nishi for the purpose of mitigating warpage (Yu, para. [0031]).
Regarding claim 25, Yu discloses wherein the recess (120) does not penetrate the mold compound (106) completely (see Figure 5).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Nishi as applied to claim 27 above, and further in view of Kapusta et al. (“Kapusta” US 2020/0176360).
Regarding claim 28, Nishi discloses that the semiconductor chips (20) include a first semiconductor chip comprising a switch and a second semiconductor chip comprising a diode (see para. [0017], the chips 20 may be an IGBT, MOSFET, well-known switches in the art, or a diode).
Nishi does not explicitly disclose that the switch and the diode being connected antiparallel to one another to form a half bridge.
Kapusta discloses that the switch (36) and the diode (32) being connected antiparallel to one another to form a half bridge (see para. [0028] and Figure 2).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kapusta into the teachings of Nishi in the manner above because a half-bridge, antiparallel connection is a fundamental building block for power converters and provide a desired power conversion (Kapusta, para. [0028]).
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Nishi as applied to claim 27 above, and further in view of Yu et al. (“Yu” US 2015/0371969).
Regarding claim 31, Nishi does not explicitly disclose that the mold compound comprises a recess between two of the power semiconductor modules.
However, Yu discloses a mold compound (106) that comprises a recess (120) between two dice (112, see Figure 5, para. [0031]).
It would have been obvious to one having ordinary skill in the art to incorporate recesses in the mold compound between devices as taught by Yu into the teachings of Nishi for the purpose of mitigating warpage (Yu, para. [0031]).
Response to Arguments
Applicant’s arguments with respect to claims 16, 27, and 36 have been considered but are moot because the new ground of rejection does not rely on any interpretation of the Nishi reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The Examiner would like to note that the stress relief member (14) of Nishi has been construed as part of a substrate. It is the Examiner’s position that, since substrates in the art provide electrical connection and mechanical support for semiconductor packages, it is within the broadest reasonable interpretation to include the stress relief member of Nishi as a part of the substrate because it provides mechanical support for the device. The stress relief member provides mechanical support for the device because it reduces thermal stress, prevents cracks from occurring at connections in the package, and prevents the mold resin from being detached (see para. [0034] pf Nishi).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights