DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 5-13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 2/26/2026.
Applicant's election with traverse of Species A in the reply filed on 2/26/2026 is acknowledged. The traversal is on the ground(s) that there is no undue burden on the examiner and subject matter in the listed species is sufficiently related such that a search for the subject matter of any one of these species would encompass a search for the subject matter of the remaining species. This is not found persuasive because the species or groupings of patentably indistinct species require a different field of search (e.g., searching different classes /subclasses or electronic resources, or employing different search strategies or search queries).
The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/26/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the first through holes and the second through holes". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tu et al (US 2015/0295154; hereinafter Tu).
Regarding claim 1, Figs 6A and 7A of Tu discloses an LED light source assembly substrate, comprising:
a first substrate (23; Fig 6A/ 7A; ¶ [0042]), wherein a die bonding configured to a front side (Top side; Fig 6A/7A) of the first substrate (23; Fig 6A/ 7A; ¶ [0042]) comprises at least two electrode soldering regions (22 (top); Fig 6A/7A; ¶ [0042]) which are connected to a positive electrode (107A; Fig 6A; ¶ [0029]) and a negative electrode (107b; Fig 6A; ¶ [0029]) of an LED chip (101; Fig 6A; ¶ [0044]), and at least two first conductive regions (22 (bottom); Fig 6A; ¶ [0042]) configured to a back side (Bottom side; Fig 6A) of the first substrate correspond to the electrode soldering regions;
a second substrate (73; Fig 7A; ¶ [0056]) stacked with the first substrate (23; Fig 6A/ 7A; ¶ [0042]), wherein at least two second conductive regions (22 top; Fig 7A; ¶ [0056]) configured to a front side (Top side; Fig 7A) of the second substrate (73; Fig 7A; ¶ [0056]) are electrically connected (Fig 7A) to the corresponding first conductive regions (22 (bottom); Fig 6A; ¶ [0042]), and at least two third conductive regions (72; Fig 7A; ¶ [0056]) configured to a back side (bottom side; Fig 7A) of the second substrate correspond to the second conductive regions;
first conductive members (22a in first substrate (23); Fig 3F; ¶ [0047]) embedded in the first substrate (23; Fig 6A/ 7A; ¶ [0042]) and electrically connecting the electrode soldering regions (22 (top); Fig 6A/7A; ¶ [0042]) to the corresponding first conductive regions (22 (bottom); Fig 6A; ¶ [0042]); and
second conductive members (22a in second substrate (73); Fig 3F; ¶ [0056]) embedded in the second substrate (73; Fig 7A; ¶ [0056]) and electrically connecting the second conductive regions (22 top; Fig 7A; ¶ [0056]) to the corresponding third conductive regions (72; Fig 7A; ¶ [0056]).
Regarding claim 2, Figs 6A and 7A of Tu discloses the first conductive members comprise metal conductive pillars (22a in first substrate (23); Fig 3F; ¶ [0047]) filled in the first through holes (22a; Fig 3F) and the second conductive members (22a in second substrate (73); Fig 3F; ¶ [0056]) comprise metal conductive layers formed on sidewalls of second through holes (Fig 7A).
Claim(s) 1-4, 14-15, 17-18, 20-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2010/0148316; hereinafter Kim).
Regarding claim 1, Fig 8 of Kim discloses an LED light source assembly substrate, comprising:
a first substrate (308; Fig 8; ¶ [0077]), wherein a die bonding configured to a front side (Top side; Fig 8) of the first substrate (308; Fig 8; ¶ [0077]) comprises at least two electrode soldering regions (327/328; Fig 8; ¶ [0079]) which are connected to a positive electrode (Fig 8) and a negative electrode (Fig 8) of an LED chip (340/342; Fig 8; ¶ [0082]), and at least two first conductive regions (320; Fig 8; ¶ [0078]) configured to a back side (Bottom side; Fig 8) of the first substrate correspond to the electrode soldering regions;
a second substrate (310; Fig 8; ¶ [0077]) stacked with the first substrate (308; Fig 8; ¶ [0077]), wherein at least two second conductive regions (330; Fig 8; ¶ [0080]) configured to a front side (Top side; Fig 8) of the second substrate (310; Fig 8; ¶ [0077]) are electrically connected (Fig 8) to the corresponding first conductive regions (320; Fig 8; ¶ [0078]), and at least two third conductive regions (337/338; Fig 8; ¶ [0083]) configured to a back side (bottom side; Fig 8) of the second substrate correspond to the second conductive regions;
first conductive members (322; Fig 8; ¶ [0078]) embedded in the first substrate (308; Fig 8; ¶ [0077]) and electrically connecting the electrode soldering regions (327/328; Fig 8; ¶ [0079]) to the corresponding first conductive regions (320; Fig 8; ¶ [0078]); and
second conductive members (332; Fig 8; ¶ [0080]) embedded in the second substrate (310; Fig 8; ¶ [0077]) and electrically connecting the second conductive regions (330; Fig 8; ¶ [0080]) to the corresponding third conductive regions (337/338; Fig 8; ¶ [0083]).
Regarding claim 2, Fig 8 of Kim discloses the first conductive members (322; Fig 8; ¶ [0078]) comprise metal conductive pillars (322; Fig 8; ¶ [0078]) filled in the first through holes (322; Fig 8; ¶ [0078]) and the second conductive members (332; Fig 8; ¶ [0080]) comprise metal conductive layers formed on sidewalls of second through holes (Fig 8).
Regarding claim 3, Fig 8 of Kim discloses a solder resist ink layer (326; Fig 8; ¶ [0079]) and a plurality of first locating structures (Fig 8) arranged on the front side of the first substrate and located around the electrode soldering regions (327/328; Fig 8; ¶ [0079]), and the at least two electrode soldering regions (327/328; Fig 8; ¶ [0079]) extend on the front side of the first substrate along a first direction and are spaced apart;
the solder resist ink layer (326; Fig 8; ¶ [0079]) is arranged on the front side (Fig 8) of the first substrate, and comprises a windowed region (Region where 327/328 is formed; Fig 8) for exposing the electrode soldering regions, a plurality of hollowed regions for exposing the plurality of first locating structures (326; Fig 8) and a plurality of second locating structures located around the windowed region and spaced apart from the plurality of first locating structures; and
a coordinate of the die bonding region in the first direction is determined according to the plurality of second locating structures, a coordinate of the die bonding region in a second direction is determined according to the plurality of first locating structures, and the second direction is perpendicular to the first direction such that the die bonding region is located in the windowed region and covers the electrode soldering regions (Fig 8).
Regarding claim 4, Fig 8 of Kim discloses a pattern formed by connecting lines formed by sequentially connecting the plurality of first locating structures is a non-regular polygon and a maximum distance between the plurality of first locating structures along the first direction is not equal to a maximum distance along the second direction.
Regarding claim 14, Fig 8 of Kim discloses a first through holes (322; Fig 8; ¶ [0078]) and a second through holes (332; Fig 8; ¶ [0080]) do not overlap in a stacking direction of the first substrate and the second substrate.
Regarding claim 15, Fig 8 of Kim discloses the die bonding region is configured to hold a plurality of LED chips (Fig 4) and at least one of the electrodes soldering regions functions as a common electrode (Fig 4) electrically connecting at least two of the LED chips.
Regarding claim 17, Fig 8 of Kim discloses at least one of the first conductive regions (320; Fig 8; ¶ [0078]) at least partially overlaps (Fig 8) a corresponding one of the second conductive regions (330; Fig 8; ¶ [0080]) in a stacking direction of the first substrate and the second substrate. (Fig 8)
Regarding claim 18, Fig 8 of Kim discloses a conductive adhesive layer (312; Fig 8; ¶ [0077]) disposed between the first conductive regions (320; Fig 8; ¶ [0078]) and the second conductive regions (330; Fig 8; ¶ [0080]) to electrically connect the first conductive regions to the second conductive regions.
Regarding claim 20, Fig 8 of Kim discloses at least one of a first bonding layer (312; Fig 8; ¶ [0077]) disposed on a back side of the first substrate (308; Fig 8; ¶ [0077]) and in a region other than the first conductive regions (Fig 8).
Regarding claim 21, Fig 8 of Kim discloses the first conductive members (322; Fig 8; ¶ [0078]) comprise metal conductive layers formed on sidewalls of first through holes (322; Fig 8; ¶ [0078]) extending through the first substrate (308; Fig 8; ¶ [0077]) and the second conductive members (332; Fig 8; ¶ [0080]) comprise metal conductive layers formed on sidewalls of second through holes (332; Fig 8; ¶ [0080]) extending through the second substrate.
Regarding claim 22, Fig 8 of Kim discloses at least one of the first conductive regions (320; Fig 8; ¶ [0078]) at least partially overlaps a corresponding one of the second conductive regions in a stacking direction of the first substrate and the second substrate.
Regarding claim 23, Fig 8 of Kim discloses an LED light source assembly substrate, comprising:
a first substrate (308; Fig 8; ¶ [0077]) and a second substrate (310; Fig 8; ¶ [0077]) arranged in a stacked manner,
the first substrate (308; Fig 8; ¶ [0077]) having a front side (Top side; Fig 8) and a back side (Bottom side; Fig 8), the front side comprising a die bonding region and at least two electrode soldering regions (327/328; Fig 8; ¶ [0079]) located within the die bonding region and extending along a first direction while being spaced apart from each other, and the back side comprising at least two first conductive regions (320; Fig 8; ¶ [0078]) corresponding to the electrode soldering regions;
first conductive members (322; Fig 8; ¶ [0078]) embedded in the first substrate and electrically connecting the electrode soldering regions to the corresponding first conductive regions;
the second substrate (310; Fig 8; ¶ [0077]) having a front side (Top side; Fig 8) and a back side (Bottom side; Fig 8), the front side comprising at least two second conductive regions (330; Fig 8; ¶ [0080]) corresponding to the first conductive regions and electrically connected thereto, and the back side comprising at least two third conductive regions corresponding to the second conductive regions (337/338; Fig 8; ¶ [0083]);
second conductive members (332; Fig 8; ¶ [0080]) embedded in the second substrate and electrically connecting the second conductive regions to the corresponding third conductive regions; and
the front side of the first substrate further comprising a plurality of first locating structures (326; Fig 8) and a plurality of second locating structures (326; Fig 8) arranged around the electrode soldering regions, and a solder resist layer (326; Fig 8; ¶ [0080]) disposed on the front side of the first substrate, the solder resist layer including a window region (Region where 327/328 is formed; Fig 8) exposing the electrode soldering regions and a plurality of hollow regions exposing the first locating structures, the second locating structures being disposed around the window region and spaced apart from the first locating structures (Fig 8).
Regarding claim 24, Fig 8 of Kim discloses the first conductive members (322; Fig 8; ¶ [0078]) comprise metal conductive layers formed on sidewalls of first through holes (322; Fig 8; ¶ [0078]) extending through the first substrate (308; Fig 8; ¶ [0077]) and the second conductive members (332; Fig 8; ¶ [0080]) comprise metal conductive layers formed on sidewalls of second through holes (332; Fig 8; ¶ [0080]) extending through the second substrate,
Wherein the first conductive members and the second conductive members do not overlap in a thickness direction of the substrate; and
wherein at least one of the first conductive regions function as a common electrode for electrically connecting at least two corresponding electrode soldering regions. (Fig 4)
Regarding claim 25, Fig 8 of Kim discloses a position of the die bonding region in the first direction is determined according to the plurality of second locating structures, and a position of the die bonding region in a second direction perpendicular to the first direction is determined according to the plurality of first locating structures, such that the die bonding region is located within the window region and covers the electrode soldering regions.
Regarding claim 26, Fig 8 of Kim discloses a pattern formed by sequentially connecting the plurality of first locating structures defines a non-regular polygon, and a maximum distance between the first locating structures measured along the first direction is different from a maximum distance measured along the second direction.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16, 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2010/0148316; hereinafter Kim) in view of Wu et al (US 2017/0358518; hereinafter Wu).
Regarding claim 16, Fig 8 of Kim discloses the electrode soldering regions.
However Kim does not expressly disclose the electrode soldering regions comprises a multi-layer structure including a copper layer, a nickel layer formed on the copper layer and a gold layer formed on the nickel layer.
In the same field of endeavor, Wu discloses a solder region can be made of multi-layer structure including a copper layer, a nickel layer formed on the copper layer and a gold layer formed on the nickel layer. (¶ [0018])
Accordingly it would have been obvious to the person in the ordinary skill of the art before the effective filing date of the invention such that a solder region can be made of multi-layer structure including a copper layer, a nickel layer and a gold layer as taught by Wu for the purpose of using well known and suitable materials known in the art for forming solder regions (¶ [0018]).
Regarding claim 27, Fig 8 of Kim discloses the electrode soldering regions.
However Kim does not expressly disclose the electrode soldering regions comprises a multi-layer structure including a copper layer, a nickel layer formed on the copper layer and a gold layer formed on the nickel layer.
In the same field of endeavor, Wu discloses a solder region can be made of multi-layer structure including a copper layer, a nickel layer formed on the copper layer and a gold layer formed on the nickel layer. (¶ [0018])
Accordingly it would have been obvious to the person in the ordinary skill of the art before the effective filing date of the invention such that a solder region can be made of multi-layer structure including a copper layer, a nickel layer and a gold layer as taught by Wu for the purpose of using well known and suitable materials known in the art for forming solder regions (¶ [0018]).
Regarding claim 28, Fig 8 of Kim discloses the electrode soldering regions.
However Kim does not expressly disclose the electrode soldering regions comprises a multi-layer structure including a copper layer, a nickel layer formed on the copper layer and a gold layer formed on the nickel layer.
In the same field of endeavor, Wu discloses a solder region can be made of multi-layer structure including a copper layer, a nickel layer formed on the copper layer and a gold layer formed on the nickel layer. (¶ [0018])
Accordingly it would have been obvious to the person in the ordinary skill of the art before the effective filing date of the invention such that a solder region can be made of multi-layer structure including a copper layer, a nickel layer and a gold layer as taught by Wu for the purpose of using well known and suitable materials known in the art for forming solder regions (¶ [0018]).
Allowable Subject Matter
Claims 19 and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 19, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the first substrate comprises at least three first alignment holes that are not collinear with each other and the second substrate comprises at least three second alignment holes or at least three alignment protrusions corresponding to the first alignment holes”.
Regarding claim 29, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the first substrate comprises at least three first alignment holes that are not collinear with each other and the second substrate comprises at least three second alignment holes or at least three alignment protrusions corresponding to the first alignment holes”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lin et al (US 10217724)
Hirai (US 2019/0103546)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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