DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election, with traverse, of species I, reading on all patent claims 1-11 and 22-30 in ”Response to Election / Restriction Filed - 10/14/2025”, is acknowledged along with cancellation of claims 12-21.
As applicant selected all remaining claims 1-11 and 22-30, and examiner entered the selection, the traversal argument is moot.
In view of the above, this office action considers claims 1-11and 22-30 pending for prosecution, where claims 1, 25 and 30 are independent claims, and all elected claims 1-11 and 22-30 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as 10; Fig 4; [0021]) = (element 10; Figure No. 4; Paragraph No. [0021]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 6-9, 11, and 24-30 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by TAKAHASHI TORU et al. (US 20100072563 A1; also published as WO 2010032820 A1) hereinafter Takahashi.
Regarding Claim 1. Takahashi teaches a wafer level package for a device, the package (figure 4: discloses a wafer level package for a device i.e. a MEMS sensor), the package comprising: (see the entire document, Figs 4-6, along with subject matter referenced in other figures, specifically, as cited below):
PNG
media_image1.png
306
1171
media_image1.png
Greyscale
Takahashi Figure 4 and Figure 6
-- a first substrate (10, obtained from SOI, though labelled as functional layer its is also labelled as substrate; fig 4; [0021]) and a second substrate (2: [0020]),
-- at least one insulating stand-off structure (30; Figs 4-6; [0020]) between the first substrate (10) and the second substrate (2),
-- a bonding layer (32, Fig 4; [0050]: "eutectic bonding" is between 32 and 42 ) on the at least one insulating stand-off structure, and
-- a first lateral electrical connection line (42 connection metal layer) on a surface of the first substrate (zoomed in to 17 that’s a part of 10; Figs 4-6) and a second lateral electrical connection line (35 : [0047], "... lead layer 35 which makes electrical connection with) on a surface of the second substrate (2; note 35 not directly on the substrate 2 since it lies on an insulating thin film part of 30, that met the claimed limitation, as this is equivalent to the layers 111 and 211 in the instant application),
-- wherein electrical connection is formed between the first lateral electrical connection line (42) and the second lateral electrical connection line (35) via the bonding layer (32; depicted in Fig 5-6) of the at least one insulating stand-off structure (30) , and
-- wherein the bonding layer (32) comprises a eutectic alloy (through eutectic bonding; [0050]).
Regarding Claim 6. Takahashi as applied to the wafer level package of claim 1, further teaches, further teaches, wherein the first substrate (10) comprises a passivation layer (3B; Fig 4) on the surface of the first substrate (10) and the second substrate 2) comprises a passivation layer (30 underlying 35; Fig 4-6)on the surface of the second substrate (2).
Regarding Claim 7. Takahashi as applied to the wafer level package of claim 1, further teaches, (the package) further teaches, wherein the package comprises at least one trench (51/52; Fig 6 [0065]) in the first substrate (10).
Regarding Claim 8. Takahashi as applied to the wafer level package of claim 7, further teaches, wherein electrical connection is formed over the at least one trench (51/52; Fig 6) via the second lateral electrical connection line (35).
Regarding Claim 9. Takahashi as applied to the wafer level package of claim 7, further teaches, wherein electrical connection is formed (Fig 6) over the at least one trench (51/52) via a second bonding material layer (32).
Regarding Claim 11. Takahashi as applied to the wafer level package of claim 1, further teaches, wherein the package is for contains a MEMS device (a MEMS sensor ; Figs 1, 4; [0019]: depicting a functional substrate layer 10, a movable electrode unit, a fixed electrode unit and a frame layer).
Regarding Claim 24. Takahashi as applied to the wafer level package of claim 1, further teaches, wherein the first substrate (10) is a MEMS device wafer (a MEMS sensor ; Figs 1, 4; [0019]: depicting a functional substrate layer 10, a movable electrode unit, a fixed electrode unit and a frame layer) and the second substrate is a cap wafer (2).
Regarding Claim 25. Takahashi teaches a wafer level package for a MEMS device (figure 4: discloses a wafer level package for a device i.e. a MEMS sensor ; Figs 1, 4; [0019]: depicting a functional substrate layer 10, a movable electrode unit, a fixed electrode unit and a frame layer), the package comprising (see the entire document, Figs 1, 4-6, along with subject matter referenced in other figures, specifically, as cited below):
--a MEMS device (Fig 1; [0019]) wafer (10, obtained from SOI, though labelled as functional layer 10 its is also labelled as substrate; fig 1, 4; [0019, 0021]);
--a first lateral electrical connection line (42 connection metal layer) on a surface of the first substrate (zoomed in to 17 that’s a part of 10; Figs 4-6) on a surface of the MEMS device wafer;
--a cap wafer (2; [0020]);
--a second lateral electrical connection line (35: [0047], "... lead layer 35 which makes electrical connection with) on a surface of the cap wafer (2 ; note 35 not directly on the substrate 2 since it lies on an insulating thin film part of 30, that met the claimed limitation, as this is equivalent to the layers 111 and 211 in the instant application);;
--at least one insulating stand-off structure (30; Figs 4-6; [0020]) between the MEMS device wafer (10) and the cap wafer (2); and
--a bonding layer (32, Fig 4; [0050]: "eutectic bonding" is between 32 and 42 ) on the at least one insulating stand-off structure (30);
--wherein the first lateral electrical connection line (42) is electrically connected to the second lateral electrical connection line (35) via the bonding layer (32; Fig 5) of the at least one insulating stand-off structure (30).
Regarding Claim 26. Takahashi as applied to the wafer level package of claim 25, further teaches, wherein the package comprises at least one (51/52; Fig 6 [0065]) in the MEMS device wafer (10).
Regarding Claim 27. Takahashi as applied to the wafer level package of claim 26, further teaches, wherein the second lateral electrical connection line (35) forms an electrical connection (Fig 6) over the at least one trench (51/52.
Regarding Claim 28. Takahashi as applied to the wafer level package of claim 25, further teaches,, wherein the package comprises a seal ring (33; Fig 4;[0045-0046]) between the MEMS device (10) wafer and the cap wafer (2).
Regarding Claim 26. Takahashi as applied to the wafer level package of claim 25, further teaches, wherein the bonding layer (32) comprises a eutectic alloy (through eutectic bonding; [0050]).
Regarding Claim 30. Takahashi teaches a wafer level package for a device, the package (figure 4: discloses a wafer level package for a device i.e. a MEMS sensor), the package comprising: (see the entire document, Figs 4-5, along with subject matter referenced in other figures, specifically, as cited below):
--a first substrate (10, obtained from SOI, though labelled as functional layer its is also labelled as substrate; fig 4; [0021]);
a first lateral electrical connection line (42 connection metal layer) on a surface of the first substrate (zoomed in to 17 that’s a part of 10; Figs 4-5);
--a second substrate (2: [0020]);
--a second lateral electrical connection line (35 : [0047], "... lead layer 35 which makes electrical connection with) on a surface of the second substrate (2; note 35 not directly on the substrate 2 since it lies on an insulating thin film part of 30, that met the claimed limitation, as this is equivalent to the layers 111 and 211 in the instant application);
--at least one insulating stand-off structure (30; Figs 4-5; [0020]) between the first substrate (10) and the second substrate (2);
--a bonding layer (32, Fig 4; [0050]: "eutectic bonding" is between 32 and 42 ) on the at least one insulating stand-off structure (30), the bonding layer comprising a eutectic alloy (through eutectic bonding; [0050]), and
--the bonding layer (32) electrically connecting (Fig 5) the first lateral electrical connection line (42) to the second lateral electrical connection line (35).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Dehe; Alfons et al. (US 20120319217 A1) hereinafter Dehe TAKAHASHI TORU et al. (US 20100072563 A1; also published as WO 2010032820 A1) hereinafter Takahashi.
Regarding Claims 2-3, 5, 22, 23, Takahashi as applied to the wafer level package of claim 1, is silent on, wherein
For claim 2: each of the at least one insulating stand-off structure (30) has a height less than 10 μm.
For claim 3: the thickness of the first lateral electrical connection (42) line is 0.2-5 μm.
For claim 5: the thickness of the bonding layer (32) is less than 5 μm.
For claim 22: each of the at least one insulating stand-off structure (40) has a height less than 5 μm.
For claim 23: each of the at least one insulating stand-off structure has a height between 1-2 μm; the thickness of the first lateral electrical connection line is 0.5-1 μm; and the thickness of the bonding layer is 0.5-2 μm.
Notwithstanding, the Applicant has not presented persuasive evidence that having the dimensional height or thickness as claimed in claims 2-3,5, 22, 23 are critical to the overall claimed invention (i.e. the invention would not work without the specific claimed thickness). Also, the applicant has not shown that the claimed height or thickness as in claims 2-3,5, 22, 23 produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
On the other hand, Takahashi establishes ([0061]) the thickness of substrates and layers can be controlled with high precision without variation, then height/thickness would be considered as result effective variable. Accordingly, the claims are obvious without showing that the claimed range(s) of height and/or thickness to achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize that it would be obvious to adjust the height and/or thickness value in order to adjust the movement margin value along with to realize a thin MEMS sensor with high dimension precision and high bonding strength thereof and optimize “ height and or thickness value” as a "result effective variable”, and arrives at the recited limitation in claims 2-3,5, 22, 23.
Regarding Claim 4. Takahashi as applied to the wafer level package of claim 1, further teaches, further teaches, wherein the thickness of the first lateral electrical connection line (42) is less (obvious from relative dimension of 42 and 30 in Fig 6) than the height of the at least one insulating stand-off structure (30).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Dehe; Alfons et al. (US 20120319217 A1) hereinafter Dehe TAKAHASHI TORU et al. (US 20100072563 A1; also published as WO 2010032820 A1) hereinafter Takahashi;; in view of Noda; Naoki et al. (US 20120299128 A1; hereinafter Noda.
Regarding Claim 10. Takahashi as applied to the wafer level package of claim 1, while further teaches, wherein the package comprises at least one sealing structure (33; Fig 4;[0045-0046]), which sealing structure comprises:
a seal ring between the first substrate (10) and the second substrate (2),
a bonding layer (32) on a surface of the second substrate (2); but, Takahashi does not expressly disclose, “plurality of micro-rings within the seal ring to confine metal melt of the bonding layer between micro-rings”.
However, in the analogous art, Noda teaches bonding of two semiconductor substrates by eutectic bonding and a MEMS device formed by the same ([0001]) wherein (Figs 9A-9C; [0050-0052]) the plurality of aluminum ring-shaped layer sections 37 are formed in a ring shape in a plan view concentrically with the bonding section 30b, and are disposed to be orthogonal in the inner/outer direction of the bonding section 30b. FIG. 9C illustrates the bonding section after eutectic bonding. A eutectic alloy in a melting state formed by heating spreads into the plurality of pits 41 thoroughly by capillary action in vacuum by pressurization. Then, the fixed eutectic alloy layer 33 is formed to bite into the bonding section 30 (substrate 11) of the MEMS chip 10. In other words, as illustrated, since the eutectic alloy layer 33 is formed vertically with respect to a surface direction of the bonding section, bonding with higher bonding strength can be achieved.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate teaching of Noda into Takahashi‘s bonding region, thereafter, the combination of (Takahashi and Noda)’s package comprises plurality of micro-rings (Noda) within the seal ring (Takahashi) to confine metal melt of the bonding layer between micro-rings, since this inclusion, at least, bonding with higher bonding strength can be achieve (Noda [0052]) .
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOAZZAM HOSSAIN whose telephone number is (571)270-7960. The examiner can normally be reached M-F: 8:30AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
December 16, 2025