DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 16, 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 6-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CN 114122228 A to Shiwei et al. (hereinafter “Shiwei” – previously cited reference).
Regarding claim 1, Shiwei discloses a light emitting diode chip, comprising:
a base substrate (light emitting element having substrate 100; Figs. 1-3; paragraph [0037]);
at least two light emitting units disposed on the base substrate, wherein the at least two light emitting units comprise adjacent first light emitting unit and second light emitting unit (first and second light emitting diodes 210, 220 formed on substrate 100; Figs. 1-3; paragraph [0044]), and each of the first light emitting unit and the second light emitting unit comprises:
a first semiconductor layer disposed on the base substrate;
a light emitting layer disposed on the first semiconductor layer away from the base substrate; and
a second semiconductor layer disposed on the light emitting layer away from the base substrate (LEDs 210, 220 each comprise first semiconductor layer 211, active layer 212, and second semiconductor layer 213 sequentially arranged upon substrate 100; Figs. 1-3; paragraph [0044]),
wherein the light emitting diode chip further comprises a bridging part for conducting, and the bridging part is configured to electrically connect the second semiconductor layer of the first light emitting unit with the first semiconductor layer of the second light emitting unit (first portion of bridge metal 216 electrically connects layers 211-213 of LEDs 210, 220; Figs. 1-3; paragraph [0044]),
wherein the first light emitting unit comprises a first side wall close to the second light emitting unit, the bridging part comprises an inclined connecting part disposed on the first side wall of the first light emitting unit, and the inclined connecting part is inclined with respect to a surface of the base substrate facing the at least two light emitting units (isolation groove 400 forms sidewall of LEDs 210, 220 where bridge metal 216 formed over groove 400 has inclined portion relative substrate 100; Figs. 1-3; paragraphs [0057]-[0058]),
wherein the light emitting diode chip further comprises a first insulation layer, the first insulation layer comprises an inclined part sandwiched between the first side wall of the first light emitting unit and the inclined connecting part (current blocking layer 500 comprises inclined portion between groove 400 and bridge metal 216 inclined portion; Figs. 1-3; paragraphs [0045], [0057]-[0058]), at least a part of the inclined part is inclined with respect to the surface of the base substrate facing the at least two light emitting units at an inclination θ, and the inclination θ ≤ 60 ° (layer 500 inclined portion is inclined at an angle of less than 60 degrees relative substrate 100; Figs. 1-3; paragraphs [0057]-[0058]),
wherein the inclined part comprises a first side surface close to the first light emitting unit; a part of the first side surface is in contact with the first semiconductor layer of the first light emitting unit, and the part of the first side surface in contact with the first semiconductor layer of the first light emitting unit comprises a first sub-side surface and a second sub-side surface directly connected with each other (inclined portion of layer 500 comprises first side surface adjacent semiconductor layer 211 of LED 210, where first side surface comprises first and second sub-side surfaces at left and right sides of layer 500 which are directly connected to one another at the bottom of layer 500; Figs. 1-3; paragraphs [0057]-[0058]); and
the first sub-side surface is inclined with respect to the surface of the base substrate facing the at least two light emitting units at an inclination α, the second sub-side surface is inclined with respect to the surface of the base substrate facing the at least two light emitting units at the inclination θ, and the inclination α is not equal to the inclination θ (first sub-side surface portion of layer 500 inclined at an angle relative substrate 100 that is different than inclination angle of second sub-side surface portion of layer 500; Fig. 2), and wherein the first sub-side surface is closer to the base substrate than the second sub-side surface, and the inclination α is greater than the inclination θ (portion of first sub-side surface portion of layer 500 closer to substrate 100 than portion of second sub-side surface portion of layer 500, where first sub-side surface is inclined at a first angle relative substrate 100 and second sub-side surface is inclined at a second angle relative substrate 100, where the first angle is greater than the second angle; Fig. 2).
Regarding claim 2, Shiwei discloses the light emitting diode chip of claim 1, wherein the light emitting diode chip comprises at least two bridging parts, each of the at least two bridging parts is configured to electrically connect the second semiconductor layer of the first light emitting unit with the first semiconductor layer of the second light emitting unit, and orthographic projections of the at least two bridging parts on the base substrate are spaced from each other (first and second portions of bridge metal 216 electrically connects layers 211-213 of LEDs 210, 220, where the first and second portions are spaced apart from one another in a horizontal direction parallel to substrate 100; Figs. 1-3; paragraph [0044]).
Regarding claim 6, Shiwei discloses the light emitting diode chip of claim 1, wherein the first side surface further comprises a platform surface connecting the first sub-side surface and the second sub-side surface, and the platform surface is parallel to the surface of the base substrate facing the at least two light emitting units (first side surface of layer 500 includes portion parallel to substrate 100 between first and second sub-side surface portions; Fig. 2).
Regarding claim 7, Shiwei discloses the light emitting diode chip of claim 1, wherein the first side surface further comprises a third sub-side surface in contact with the light emitting layer of the first light emitting unit and a fourth sub-side surface in contact with the second semiconductor layer of the first light emitting unit; each of the third sub-side surface and the fourth sub-side surface is inclined with respect to the surface of the base substrate facing the at least two light emitting units at the inclination θ (first side surface of layer 500 having third and fourth sub-side portions in contact with layers 211, 212 of LEDs 210, 220 and inclined at the angle less than 60 degrees relative the substrate 100; Fig. 2).
Regarding claim 8, Shiwei discloses the light emitting diode chip of claim 1, wherein the first insulation layer further comprises a first plane part, the first plane part is parallel to the surface of the base substrate facing the at least two light emitting units, the first plane part is located in an interval between the first light emitting unit and the second light emitting unit, and a width of the first plane part is less than or equal to a width of the interval (first side surface of layer 500 includes portion parallel to substrate 100 between first and second LEDs 210, 220 with a width less than space between LEDs 210, 220; Fig. 2).
Regarding claim 9, Shiwei discloses the light emitting diode chip of claim 8, wherein the first plane part comprises a first sub-plane part and a second sub-plane part, the first sub-plane part is closer to the first light emitting unit than the second sub-plane part, and a height of the first sub-plane part is greater than a height of the second sub-plane part (first portion of parallel portion closer to LED 210 than second portion of parallel portion with the first portion having a height greater than second portion; Fig. 2).
Regarding claim 10, Shiwei discloses the light emitting diode chip of claim 1, wherein the light emitting diode chip further comprises an avoidance structure (LED 220 comprising concave structures at corners of sidewall thereof; Fig. 1); the avoidance structure comprises a first avoidance concave part located on at least a part of the first side wall, the first avoidance concave part causes at least a part of the first side wall to be concaved towards a first direction, and the first direction is a direction directing from the second light emitting unit to the first light emitting unit (concave structure located at sidewall of LED 220 in direction from LED 220 to LED 210; Fig. 1); and/or the second light emitting unit comprises a second side wall close to the first light emitting unit, the avoidance structure comprises a second avoidance concave part located on at least a part of the second side wall, the second avoidance concave part causes at least a part of the second side wall to be concaved towards a second direction, and the second direction is a direction directing from the first light emitting unit to the second light emitting unit (only one of the conditional ‘or’ limitation is required to be taught by the prior art to read on the claim language).
Regarding claim 11, Shiwei discloses the light emitting diode chip of claim 10, wherein the bridging part comprises a third side wall facing an interval between the first light emitting unit and the second light emitting unit (bridge metal 216 having side surface facing interval between LEDs 210, 220; Figs. 1-2), the avoidance structure comprises a third avoidance concave part located on at least a part of the third side wall, the third avoidance concave part causes at least a part of the third side wall to be concaved towards a third direction, and the third direction is a direction directing from the interval to a body of the bridging part (LED 220 having another concave structure above side surface of metal 216 and forms concave shape of side surface of metal 216 in direction from interval between LEDs 210, 220 and metal 216; Figs. 1-2).
Regarding claim 12, Shiwei discloses the light emitting diode chip of claim 1, wherein a contour of an orthographic projection of the light emitting diode chip on the base substrate has a shape of square (light emitting element has a square shape on substrate 100; Fig. 1).
Regarding claim 13, Shiwei discloses the light emitting diode chip of claim 12, wherein orthographic projections of the at least two light emitting units on the base substrate are arranged symmetrically with respect to a geometric center of the square (LEDs 210, 220 arranged symmetric about center of square shape of light emitting diode; Fig. 1).
Regarding claim 14, Shiwei discloses a display substrate comprising a light emitting diode chip of claim 1 (display device having light emitting element on substrate; abstract).
Regarding claim 15, Shiwei discloses a display device comprising a light emitting diode chip of claim 1 (display device having light emitting element; abstract).
Response to Arguments
Applicant's arguments filed April 16, 2026 have been fully considered. Applicant presents substantive amendments to claim 1 with corresponding arguments. Specifically, Applicant recites similar arguments previously presented that the part of layer 500 in contact with layer 211 is inclined at the same overall angle and does not comprise two sub-parts with unequal inclination angles. However, layer 500 comprises a bottom side surface having a portion at least partially contacting layer 211, where this portion of bottom side surface comprises left and right sub-side surfaces that have different inclination angles relative one another and associated different distances to substrate 100 and further directly connected at the bottom of layer 500. It appears the broadest reasonable interpretation of Applicant’s claim 1 language is broader than the scope being argued by Applicant in these arguments. Examiner recommends amending the associated claim language to differentiate between Examiner’s interpretation of Shiwei and Applicant’s intended claim scope which would then overcome the current 35 USC 102 rejection using Shiwei. Therefore, amended claim 1 is disclosed by Shiwei and the corresponding 35 USC 102 rejection is maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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