Prosecution Insights
Last updated: October 02, 2026
Application No. 18/028,299

ARRAY SUBSTRATE AND ELECTRONIC APPARATUS

Non-Final OA §103
Filed
Mar 24, 2023
Priority
May 27, 2022 — nonprovisional of PCTCN2022095708
Examiner
CRITE, ANTONIO B
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
68%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
376 granted / 461 resolved
+13.6% vs TC avg
Minimal -13% lift
Without
With
+-13.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
28 currently pending
Career history
484
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
24.6%
-15.4% vs TC avg
§112
19.6%
-20.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 461 resolved cases

Office Action

§103
DETAILED ACTION This Action is responsive to the Amendment filed on 07/27/2026. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/27/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rinne (US 2021/0135070), in view of Brunner (US 2025/0143051), in view of Yang (US 2023/0178701), in view of Li (CN 109656059 A). Regarding claim 1, Rinne (see, e.g., FIG. 7) discloses an array substrate, comprising: a base substrate 10 (Para 0075); a first conductive layer 14, 16, disposed on the base substrate 10, wherein the first conductive layer 14, 16 comprises a plurality of pads 14 (Para 0075); and an electronic element 32 (30, 36), disposed on a side e.g., top side of the first conductive layer 14, 16 facing away from the base substrate 10, wherein the electronic element 32 (30, 36) comprises an electronic element body 34 and a plurality of pins 38 at a side e.g., bottom side of the electronic element body 34 facing the base substrate 10, and the plurality of pins 38 are connected with the plurality of pads 14 (Para 0069, Para 0070, Para 0075); wherein the first conductive layer 14, 16 comprises first wires 16 arranged on a same layer e.g., both on the base substrate as the pads 14, and a thickness of the first wire 16 is less than a thickness of the pad 14 (Para 0075). Although Rinne shows substantial features of the claimed invention, Rinne fails to expressly teach that each of the plurality of pads comprises a first metal layer, a material of the first metal layer comprises Cu, a content of the Cu is greater than or equal to 99%, and a thickness of the first metal layer is greater than 2 µm; a first insulating layer between the first conductive layer and the base substrate; and a second conductive layer between the first insulating layer and the base substrate; an orthographic projection of the second conductive layer on the base substrate completely covers an orthographic projection of the pin on the base; and an orthographic projection of the first insulating layer on the base substrate entirely and completely covers the orthographic projection of the second conductive layer on the base substrate. Brunner (see, e.g., FIG. 1) teaches each of the plurality of pads 104, 105 comprises a first metal layer e.g., copper, a material of the first metal layer e.g., copper comprises Cu, a content of the Cu is greater than or equal to 99%, and a thickness of the first metal layer e.g., copper is greater than 2 µm (Para 0064, Para 0140). Yang, on the other hand, teaches that copper is a metallic material with good electrically conductivity (Para 0021, Para 0027). Examiner note: of the available options, copper, without containing other materials therein, is listed as a metal material for the pads. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the material of the pads in the device of Rinne to comprise a first metal layer where the material of the first metal layer comprises Cu, a content of the Cu is greater than or equal to 99% as described by Brunner/Yang for the purpose of providing a metallic material with good electrically conductivity (Para 0021, Para 0027). Li (see, e.g., FIG. 7) teaches an array substrate further comprises: a first insulating layer 14 (pg 7, para 7); and a second conductive layer 4 between the first insulating layer 14 and the base substrate 13 (pg 7, para 7); and an orthographic projection of the first insulating layer 14 on the base substrate 13 entirely and completely covers the orthographic projection of the second conductive layer 4 on the base substrate 13 for the purpose of improving light extraction efficiency (pg 2, para 5; pg 6, para 2; pg 7, para 7). The combination of Rinne (see, e.g., FIG. 7) / Li (see, e.g., FIG. 7) teaches a first insulating layer 14 (as taught by Li) between the first conductive layer 14, 16 (as taught by Rinne) and the base substrate 13 (as taught by Li); an orthographic projection of the second conductive layer 4 (as taught by Li) on the base substrate 13 (as taught by Li) completely covers an orthographic projection of the pin 38 (as taught by Rinne) on the base substrate 13 (as taught by Li) Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the base substrate of Rinne/Brunner/Yang to include the second conductive layer between the first insulating layer and the base substrate as described by Li to for the purpose of improving light extraction efficiency (pg. 8, para 6). Regarding claim 19, Rinne (see, e.g., FIG. 7) teaches the array substrate according to claim 1, wherein the electronic element 32 (30, 36) is a mini light-emitting diode, LED, a micro LED, or a micro driver chip (Para 0064, Para 0069). Regarding claim 20, Rinne (see, e.g., FIG. 7) teaches an electronic apparatus e.g., display structure 99, comprising the array substrate according to claim 1 (Para 0073-Para 0075). Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Rinne (US 2021/0135070), in view of Brunner (US 2025/0143051), in view of Yang (US 2023/0178701), in view of Li (CN 109656059 A), and further in view of Cao (WO 2022/056842 A1). Regarding claim 2, although Rinne/Brunner/Yang/Li show substantial features of the claimed invention, Rinne/Brunner/Yang/Li fail to expressly teach that each of the plurality of pads further comprises a second metal layer; and the second metal layer is disposed on a side of the first metal layer close to the base substrate; wherein a material of the second metal layer comprises molybdenum-niobium alloy or molybdenum-nickel-titanium alloy. Cao (see, e.g., FIG. 10) teaches array substrate according to claim 1, wherein a second metal layer 210 (pg. 8, para 4); and the second metal layer 210 is disposed on a side of the first metal layer 220 close to the base substrate 100 (pg. 8, para 4); wherein a material of the second metal layer 210 comprises molybdenum-niobium alloy or molybdenum-nickel-titanium alloy for the purpose of increasing the adhesion between the copper metal layer and other film layers (pg 7, para 6; pg. 8, para 4). The combination of Rinne (see, e.g., FIG. 7) / Brunner (see, e.g., FIG. 1) / Cao (see, e.g., FIG. 10) teaches each of the plurality of pads 14 (as taught by Rinne with material modified by Brunner) further comprises a second metal layer 210 (as taught by Cao); and the second metal layer 210 (as taught by Cao) is disposed on a side of the first metal layer e.g., copper material of 14 (as taught by Rinne with material modified by Brunner) close to the base substrate 10 (as taught by Rinne); wherein a material of the second metal layer 210 (as taught by Cao) comprises molybdenum-niobium alloy or molybdenum-nickel-titanium alloy. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the second metal layer wherein a material of the second metal layer comprises molybdenum-niobium alloy or molybdenum-nickel-titanium alloy as described by Cao in the device of Rinne/Brunner for the purpose of increasing the adhesion between the copper metal layer and other film layers (pg 7, para 6). Regarding claim 3, although Rinne/Brunner/Yang/Li show substantial features of the claimed invention, Rinne/Brunner/Yang/Li fail to expressly teach that a plurality of first protective layers between the plurality of pins and the plurality of pads, wherein a material of the first protective layers is a conductive material. Cao (see, e.g., FIG. 10) teaches array substrate according to claim 2, wherein a plurality of first protective layers 240, wherein a material of the first protective layers 240 is a conductive material e.g., copper-nickel alloy for the purpose of preventing the copper metal layer from being oxidized (pg 8, para 1, para 4). The combination of Rinne (see, e.g., FIG. 7) / Brunner (see, e.g., FIG. 1) / Cao (see, e.g., FIG. 10) teaches a plurality of first protective layers 240 (as taught by Cao) between the plurality of pins 38 (as taught by Rinne) and the plurality of pads 14 (as taught by Rinne with material modified by Brunner), wherein a material of the first protective layers 240 (as taught by Cao) is a conductive material e.g., copper-nickel alloy (as taught by Cao) (pg 8, para 4). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the plurality of first protective layers, wherein a material of the first protective layers is a conductive material as described by Cao into the device of Rinne/Brunner for the purpose of preventing the copper metal layer from being oxidized (pg 8, para 1). Regarding claim 4, Cao (see, e.g., FIG. 10) teaches array substrate according to claim 3, wherein a thickness of each of the first protective layer 240 ranges from 100 A to 5000 A (pg 8, para 4). Regarding claim 5, Cao (see, e.g., FIG. 10) teaches array substrate according to claim 4, wherein a material of each of the first protective layers 240 comprises CuNi (pg 8, para 4). Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Rinne (US 2021/0135070), in view of Brunner (US 2025/0143051), in view of Yang (US 2023/0178701), in view of Li (CN 109656059 A), in view of Cao (WO 2022/056842 A1), and further in view of Yoo (KR 2019 0097739 A), in view of Nitta (US 2024/0408703). Regarding claim 6, although Rinne/Brunner/Yang/Li/Cao show substantial features of the claimed invention, Rinne/Brunner/Yang/Li/Cao fail to expressly teach that the plurality of pins are connected with the plurality of first protective layers by means of soldering flux, and a material of the soldering flux comprises Sn; each of the plurality of pads further comprises: a first intermetallic compound layer disposed on a side of the first metal layer facing away from the second metal layer; and a material of the first intermetallic compound layer comprises CuxSny, wherein x=1 or x=6, and y=3 or y=5. Yoo (see, e.g., FIG. 1) teaches the array substrate according to claim 4, wherein that the plurality of pins 121, 122 are connected by means of soldering flux 191, 192, and a material of the soldering flux 191, 192 comprises Sn (Para 0062, Para 0064); each of the plurality of pads P11, P21 further comprises: a first intermetallic compound layer IMC disposed on a side of the first metal layer e.g., metal material of P11, P21 for the purpose of providing a physically, electrically, stably coupling between the first and second bonding parts and the first and second pad parts (Para 0065-Para 0069). The combination of Rinne (see, e.g., FIG. 7) / Brunner (see, e.g., FIG. 1) / Cao (see, e.g., FIG. 10) / Yoo (see, e.g., FIG. 1) teaches that that the plurality of pins 38 (as taught by Rinne) are connected with the plurality of first protective layers 240 (as taught by Cao) by means of soldering flux 191, 192 (as taught by Yoo), and a material of the soldering flux 191, 192 (as taught by Yoo) comprises Sn; each of the plurality of pads 14 (as taught by Rinne) further comprises: a first intermetallic compound layer IMC (as taught by Yoo) disposed on a side of the first metal layer e.g., copper material layer of 14 (as taught by Rinne with material modified by Brunner) facing away from the second metal layer 210 (as taught by Cao). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the soldering flux, and a material of the soldering flux comprises Sn; each of the plurality of pads further comprises: a first intermetallic compound layer IMC disposed on a side of the first metal layer as described by Yoo into the device of Rinne/Brunner/Yang/Li/Cao for the purpose of providing a physically, electrically, stably coupling between the first and second bonding parts and the first and second pad parts (Para 0069). Nitta teaches that a material of the first intermetallic compound layer e.g., bonding layer CuSn.sub.3 comprises CuxSny, wherein x=1 or x=6, and y=3 or y=5 for the purpose of providing a bonding layer with extremely high shear resistance, heat resistance, electrical conductivity, and heat dissipation properties (Para 0111-Para 0112, Para 0115). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first intermetallic compound layer of Rinne/Brunner/Yang/Cao/Yoo to be a material of the first intermetallic compound layer that comprises CuxSny, wherein x=1 or x=6, and y=3 or y=5 as described by Nitta for the purpose of providing a bonding layer with extremely high shear resistance, heat resistance, electrical conductivity, and heat dissipation properties (Para 0115). Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONIO CRITE whose telephone number is (571) 270-5267. The examiner can normally be reached Monday - Friday, 10:00 am - 6:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Mar 24, 2023
Application Filed
Dec 30, 2025
Non-Final Rejection mailed — §103
Mar 27, 2026
Response Filed
Apr 29, 2026
Final Rejection mailed — §103
Jul 27, 2026
Request for Continued Examination
Jul 29, 2026
Response after Non-Final Action
Aug 11, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
68%
With Interview (-13.4%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 461 resolved cases by this examiner. Grant probability derived from career allowance rate.

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