DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment/Restriction
Applicant's election with traverse of Group I and claims 1-12 and 20 in the reply filed on December 19, 2025 is acknowledged. The traversal is on the ground(s) that “Under MPEP §803…it is respectfully submitted that it would not be a serious burden upon the Examiner to examine all of the claims in the application…and to examine all of the Groups 1-3 claims pending in this application.” This is not found persuasive because the Restriction Requirement is under Unity of Invention/PCT Rule 13.1. Arguments regarding the lack of burden is based on the U.S. restriction practice and is not applicable. As set forth under MPEP §1850, “when the Office considers international applications as an International Searching Authority, as an International Preliminary Examining Authority, and during the national stage as a Designated or Elected Office under 35 U.S.C. 371, PCT Rule 13.1 and 13.2 will be followed when considering unity of invention of claims of different categories without regard to the practice in national applications filed under 35 U.S.C. 111.”
The requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is broad and not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 9-12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over CN 110534542 A to Li et al. (“Li”) in view of U.S. Patent Application Publication No. 2016/0284673 A1 to Kong et al. (“Kong”). As to claim 1, Li in view of Kong discloses a light-emitting diode chip, comprising: a substrate (10); a plurality of epitaxial structures on a side of the substrate (10), wherein a gap (at 50) exists between any two adjacent ones of the plurality of epitaxial structures, each epitaxial structure comprises a first semiconductor pattern (corresponding 40), a light-emitting pattern (61, 71, 81) and a second semiconductor pattern (63, 73, 83) which are sequentially stacked, and the first semiconductor patterns (corresponding 40) of the plurality of epitaxial structures are coupled to each other to form a first semiconductor layer (40); a first light-blocking layer (50/1) on a side of the first semiconductor layer (40) away from the substrate (10), wherein the first light-blocking layer (50/1) is provided therein with a plurality of accommodating holes (for at least light-emitting pattern) in one-to-one correspondence with the plurality of epitaxial structures, and the light-emitting patterns (61, 71, 81) and the second semiconductor patterns (63, 73, 83) of the plurality of epitaxial structures are in corresponding ones of the plurality of accommodating holes (for at least light-emitting pattern); a second light-blocking layer (50/1) on a side of the first light-blocking layer (50/1) away from the substrate (10), wherein the second light-blocking layer (50/1) is provided therein with a plurality of pixel openings (for 110) in one-to-one correspondence with the plurality of accommodating holes (for at least light-emitting pattern); an orthographic projection of each pixel opening (for 110) on the substrate (10) overlaps with an orthographic projection of the corresponding accommodating hole (for at least light-emitting pattern) on the substrate (10); a light processing pattern (110) is in at least one pixel opening (for 110) and includes a color conversion pattern (110) configured to convert light of a preset color emitted by the light-emitting pattern (61, 71, 81) into light of other color; at least one first electrode (102) electrically coupled to the first semiconductor layer (40); and a plurality of second electrodes (101) in one-to-one correspondence with the plurality of epitaxial structures and electrically coupled to the second semiconductor patterns (63, 73, 83) of corresponding ones of the plurality of epitaxial structures (See Li et al. Fig. 1, Page 2-Page 9, and Kong et al. Fig. 1, ¶ 0027-¶ 0037) (Notes: the first and second light-blocking layers are formed as one-piece opaque structure as recited in claim 2 to prevent light mix till the topmost emitting surfaces of the light processing patterns to reduce the volume of LED display chip panel as taught by Kong ¶ 0035). As to claim 2, Li in view of Kong further discloses wherein the first light-blocking layer (50/1) and the second light-blocking layer (50/1) have one-piece structure (50/1) (See Li Fig. 1 and Kong Fig. 1). As to claim 3, Li in view of Kong further discloses wherein the orthographic projection of each pixel opening (for 110/80-82) on the substrate (10) completely covers the orthographic projection of the corresponding accommodating hole (for at least light-emitting pattern) on the substrate (10) (See Li Fig. 1 and Kong Fig. 1). As to claim 4, Li in view of Kong further discloses wherein the at least one first electrode (102) is on a side of the second light-blocking layer (50/1) away from the substrate (10), and is coupled to and in contact with the first semiconductor layer (40) in a via manner (See Li Fig. 1 and Kong Fig. 1) (Notes: the via manner is interpreted as through and adjacent to the light-blocking layer in a vertical direction). As to claim 9, Li in view of Kong further discloses wherein the light of the preset color is blue light; and the light of other color comprises at least one of red light, green light, cyan light, magenta light, and yellow light (See Li ¶ 0058, ¶ 0060, ¶ 0069 and Kong ¶ 0033). As to claim 10, Li in view of Kong further discloses wherein the substrate (10) comprises a first region and a second region along a second direction; the at least one first electrode (102) is in the first region; the plurality of epitaxial structures are in the second region and are sequentially arranged in the second region along a first direction; the plurality of pixel openings (for 110) corresponding to the plurality of epitaxial structures are in the second region and are sequentially arranged in the second region along the first direction; and an orthographic projection of each second electrode (101) on the substrate (10) overlaps with an orthographic projection of the pixel opening (for 110) of the corresponding epitaxial structure on the substrate (10), and the orthographic projection of each second electrode (101) on the substrate (10) is at one end, which is close to the first region, of the orthographic projection of the pixel opening (for 110) of the corresponding epitaxial structure on the substrate (10) (See Li Fig. 1) (Notes: the 3D epitaxial structures are arranged in the first direction and the one end is adjacent/close the edges). As to claim 11, Li in view of Kong further discloses wherein the at least one first electrode (102) comprises one first electrode (102) at a middle position of the first region in the first direction; the plurality of pixel openings (for 110) corresponding to the plurality of epitaxial structures are arranged at equal intervals along the first direction in the second region; and the plurality of second electrodes (101) corresponding to the plurality of epitaxial structures are arranged at equal intervals along the first direction in the second region (See Li Fig. 1). As to claim 12, Li in view of Kong further discloses wherein a length of each light-emitting pattern (61, 71, 81) in the first direction is in a range from 10 μm to 100 μm; and a length of each light-emitting pattern (61, 71, 81) in the second direction is in a range from 30 μm to 200 μm (See Li ¶ 0057) (Notes: an array of the light-emitting patterns is generally formed in squares and is formed with about 100 μm in first and second directions. The dimensions also determine the numbers of the light-emitting patterns can be packed on the substrate). As to claim 20, Li in view of Kong discloses further comprising a buffer layer (20) between the first semiconductor layer (40) and the substrate (10) (See Li Fig. 1, ¶ 0036).
Claim(s) 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over CN 110534542 A to Li et al. (“Li”) and U.S. Patent Application Publication No. 2016/0284673 A1 to Kong et al. (“Kong”) as applied to claim 4 above, and further in view of U.S. Patent Application Publication No. 2008/0258161 A1 to Edmond et al. (“Edmond”). As to claim 5, Li in view of Kong and Edmond further discloses wherein each epitaxial structure further comprises an ohmic contact pattern (90/20, 21) on a side of the second semiconductor pattern (63, 73, 83/12, 13) away from the substrate (10), the ohmic contact pattern (90/20, 21) is in the corresponding accommodating hole (for at least light-emitting pattern); and the plurality of second electrodes (101) are on the side of the second light-blocking layer (50/1) away from the substrate (10), and each second electrode (101) is coupled to and in contact with the ohmic contact pattern (90/20, 21) of the corresponding epitaxial structure in a via manner (See Li Fig. 1, ¶ 0062, Kong Fig. 1, and Edmond Fig. 1, ¶ 0039, ¶ 0042-¶ 0044) (Notes: the via manner is interpreted as through and adjacent to the light-blocking layer in a vertical direction) such that the transparent ohmic contact pattern allows great light extraction and low contact resistance. As to claim 6, Li in view of Kong further discloses wherein the light processing pattern (110/80-82) is in each pixel opening (for 110/80-82); and wherein the light processing pattern (110/80-82) in a part of the plurality of pixel openings (for 110/80-82) is the color conversion pattern (110/80-82), and the light processing pattern (110/80-82) in other part of the plurality of pixel openings (for 110/80-82) is a light-transmitting pattern configured to allow light of the preset color to pass therethrough (See Kong ¶ 0032, ¶ 0033) (Notes: different combinations of the light processing patterns of filters and phosphors and the preset color are considered as desired). As to claim 7, Li in view of Kong and Edmond further discloses wherein the first electrode (102) is in contact with the first semiconductor layer (40) through a first connection hole (not occupied by 50/1) in the first light-blocking layer (50/1) and the second light-blocking layer (50/1); and each second electrode (101) is in contact with the ohmic contact pattern (90/20, 21) of the corresponding epitaxial structure through a second connection hole (between, not occupied by 50/1) in the corresponding light processing pattern (110/80-82) (See Li Fig. 1, Kong Fig. 1, and Edmond Fig. 1). As to claim 8, Li further discloses wherein the at least one first electrode (102) and the plurality of second electrodes (101) are in a same layer (See Li Fig. 1) (Notes: the same layer as the common patterned and deposited layer on the epitaxial structures (See Fig. 1, ¶ 0064).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815