DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claim 8 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/2/25.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2, the claimed formula can only be solved if the exponent is dimensionless. The function is not practicable since the exponent has units (eV).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over JP 4951872 (hereinafter ‘872) in view of JP 02-022823 (hereinafter ‘823).
Regarding Claim 1, ‘872 teaches a semiconductor device manufacturing method comprising: a first step of introducing oxygen (Paragraph 2)
a second step (Paragraph 10) of forming a first surface structure (3c, 4) in a first surface of the silicon wafer after the first step;
a third step (Paragraph 11) of grinding the silicon wafer from a second surface opposite the first surface after the first step;
and a fourth step (Paragraph 11) of forming a second surface structure (8) in the second surface of the silicon wafer after the third step.
Regarding Claim 1, ‘872 teaches adjustment of the claimed threshold (Paragraph 2), but does not expressly teach a first step of introducing oxygen is performed to increase an oxygen concentration of a silicon wafer when the oxygen concentration of the silicon wafer is lower than a predetermined threshold, and deriving oxygen to decrease the oxygen concentration of the silicon wafer when the oxygen concentration of the silicon wafer is higher than the threshold. However, the claimed adjustment inevitably occurs during a high temperature treatment in an oxygen atmosphere since oxygen concentration corresponding to the respective solubility limit will always be reached as shown by ‘823 (Paragraphs 23-27 and Fig 1-2).
Regarding Claim 3, ‘872 teaches a fifth step of irradiating the silicon wafer with a charged particle beam (“implanting argon ions…capturing a crystal defect”) to form point defects after the first step; and a sixth step of performing annealing for at least one of formation of composite defects including the point defects and oxygen or annihilation of some of the point defects after the fifth step.
Regarding Claim 4, ‘872 teaches in the fifth step, the first surface or the second surface of the silicon wafer is irradiated with an electron beam (Paragraph 10) as the charged particle beam to form the point defects in an entire portion of the silicon wafer after the third step.
Regarding Claim 5, ‘872 teaches in the fifth step, the first surface or the second surface of the silicon wafer is irradiated with protons or helium ions (Paragraph 10) as the charged particle beam to form the point defects in a local portion of the silicon wafer after the third step.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over JP 4951872 (hereinafter ‘872) in view of JP 02-022823 (hereinafter ‘823) and DE 102015114361 (hereinafter ‘361).
Regarding Claim 6, ‘872 in view of ‘823 does not expressly teach an entire portion or a portion on a side of the first surface of the silicon wafer after the third step has an oxygen concentration of 2x10¹⁶ cm -3 or more and 5x10¹⁷ cm -3 or less. However, the concentration of interstitial oxygen post-processing is known to one of ordinary skill in the art. For example, DE 102015114361 (hereinafter ‘361) (Paragraph 21) teaches a concentration of interstitial oxygen is reduced below 5E17 cm -3. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the silicon wafer oxygen concentration of 2x10¹⁶ cm -3 or more and 5x10¹⁷ cm -3 or less for producing a device with predictable results.
Regarding Claim 7, ‘872 in view of ‘823 does not expressly teach the silicon wafer before the first step has an oxygen concentration of 1x10¹⁵ cm⁻³ or more and 1x10¹⁸ cm⁻³ or less. However, the concentration of interstitial oxygen pre-processing is known to one of ordinary skill in the art. For example, DE 102015114361 (hereinafter ‘361) teaches (Paragraph 2) a typical concentration of 5E17 cm -3 and teaches (Paragraph 17) a maximum concentration of interstitial oxygen 6E17 cm -3. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the silicon wafer oxygen concentration concentration of 1x10¹⁵ cm⁻³ or more and 1x10¹⁸ cm⁻³ or less for a wafer grown in the conventional manner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent 11,124,893 to Choi et al. teaches method for reducing the size and density of defects in a single crystal silicon wafer. The method involves subjected a single crystal silicon ingot to an anneal prior to wafer slicing.
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/ROBERTS P CULBERT/Primary Examiner, Art Unit 1716