DETAILED ACTION
This is the first office action on the merits. Claims 1-16 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because the abstract contains more than 150 words and the abstract contains a drawing. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
Claim 15 objected to because of the following informalities: “claim7” should be “claim 7”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6, 8, 14, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanemura et al., US 20200088876 A1 (“Tanemura”).
Regarding claim 1, Tanemura discloses an array coherent ranging chip, comprising a modulated light source unit, an on-chip emission unit and a reception array, wherein the modulated light source unit is used for generating a modulated light beam (Fig. 1, LD 1, modulator 2, amplifier 3, Paragraph [0036]) and splitting the modulated light beam into signal light and reference light (Fig. 1, demultiplexer 4, Paragraph [0045]), and then outputting the signal light and the reference light (Fig. 1, optical waveguides 12a, optical waveguides 12b, Paragraph [0045]); the on-chip emission unit is used for irradiating the signal light onto a target object at a preset divergence angle so as to have the signal light reflected to form multi-angle signal light (Fig. 1, scanning unit 5, phase shifters 20, Paragraph [0049]-[0051]); and the reception array is used for receiving the reference light and the multi-angle signal light (Fig. 1, light receiver 6, light receiving antennas 21, multiplexers 7, Paragraph [0057],[0063]-[0064]) and respectively performing conversion and detection on both the reference light and the signal light of each angle so as to obtain a plurality of ranging signals (Fig. 1, converters 8, TIAs 9, Paragraph [0064]-[0065], [0067]-[0068]).
Regarding claim 6, Tanemura discloses the array coherent ranging chip according to claim 1, wherein the on-chip emission unit comprises an on-chip beam expansion structure and a diffraction structure, and wherein the on-chip beam expansion structure is configured to shape and then output the signal light (Fig. 1, scanning unit 5, phase shifters 20, optical waveguides 12c, Paragraph [0049]-[0051]); and the diffraction structure is configured to irradiate the signal light, after being shaped, onto a target object at the preset divergence angle so as to have the signal light reflected to form multi-angle signal light (Fig. 15-16, diffractive grating 44, optical waveguide 12c, Paragraph [0125]).
Regarding claim 8, Tanemura discloses the array coherent ranging chip according to claim 1 wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Regarding claim 14, Tanemura discloses the array coherent ranging chip according to claim 6, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Regarding claim 16, Tanemura discloses an array coherent ranging system, comprising a signal processing unit and the array coherent ranging chip according to claim 1, wherein the signal processing unit is configured to receive the ranging signals output by the array coherent ranging chip and calculate a distance from the target object by a spectrum analysis (Fig. 1, calculation unit 10, Paragraph [0070]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-4 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tanemura in view of Swanson et al., US 20170299697 A1 (“Swanson”).
Regarding claim 2, Tanemura discloses the array coherent ranging chip according to claim 1, wherein the reception array comprises a plurality of reception units (Fig. 1, light receiver 6, light receiving antennas 21, multiplexers 7, Paragraph [0057],[0063]-[0064]), and each of the reception units comprises a diffraction structure (Fig. 6, light receiving antenna 21, Paragraph [0058]), a light combination assembly (Fig. 1, multiplexers 7, Paragraph [0063]-[0064]) and a detector sensor (Fig. 1, converters 8, Paragraph [0064]-[0065]), and wherein the diffraction structure is configured to receive reflected light of a corresponding angle and guides the reflected light of the corresponding angle to an input end of the light combination assembly (Fig. 6, light receiving antenna 21, waveguide 12, Paragraph [0058]); the light combination assembly is configured to receive the reference light and the reflected light of the corresponding angle (Fig. 6, light receiving antenna 21, Paragraph [0058]), combine the reference light and the reflected light of the corresponding angle into a composite signal (Fig. 1, multiplexers 7, Paragraph [0063]-[0064]), […].
Tanemura does not teach: and divide the composite signal into a first detection signal and a second detection signal; and the sensor is configured to receive the first detection signal and the second detection signal, convert the first detection signal and the second detection signal into electric signals, and output a difference between the electric signals to obtain the ranging signals.
However, Swanson teaches reference and sample light that are combined in a 90 degree hybrid processor, which may be a multimode interference coupler or a star coupler, and then separated and directed to two dual-balanced detectors to produce an in-phase and quadrature signal. The in-phase and quadrature signals are used to calculate phase-sensitive light detection (Fig. 3, 90 degree hybrid processor, Ix, Q-x, PD, Paragraph [0096]-[0097]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s light receiver system by substituting Swanson’s 90 degree hybrid processor and balanced detectors for Tanemura’s multiplexers and converters. One of ordinary skill in the art would have been motivated to make this modification in order to gain signal processing improvements from the additional phase information, as suggested by Swanson (Paragraph [0097]).
Regarding claim 3, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 2, wherein the diffraction structure comprises a one-dimensional or two-dimensional diffractive optical element (Tanemura, Fig. 6, light receiving antenna 21, Paragraph [0058]); the light combination assembly comprises any one of a diffractive optical element, a diffraction grating, a metasurface, a Y-branch, a multimode interference coupler, a directional coupler, a star coupler and a polarizing beamsplitter (Swanson, 90 degree hybrid processor, Paragraph [0096]); the sensor comprises any one of an avalanche photodiode, a photomultiplier tube and a PIN diode (Tanemura, Fig. 1, converters 8, Paragraph [0065]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s light receiver system by substituting Swanson’s 90 degree hybrid processor and balanced detectors for Tanemura’s multiplexers and converters. One of ordinary skill in the art would have been motivated to make this modification in order to gain signal processing improvements from the additional phase information, as suggested by Swanson (Paragraph [0097]).
Regarding claim 4, Tanemura discloses the array coherent ranging chip according to claim 1, wherein the modulated light source unit comprises a modulation unit and a beam splitting unit, and wherein the modulation unit comprises a light source and a signal generator (Fig. 1, LD 1, Paragraph [0041]), the light source has a modulation manner which is external modulation or internal modulation (Fig. 1, modulator 2, Paragraph [0043]),
Tanemura does not teach: an external modulator that comprises an intensity modulator and the beam splitting unit comprises any one of a Y-branch, a star coupler, a multimode interference coupler, a directional coupler, a polarizing beamsplitter, a partially diffractive and partially transmissive waveguide grating.
However, Swanson teaches an external modulator that may be used to set intensity information (Fig. 7, modulator, Paragraph [0107]). Swanson also teaches directional couplers that are used to couple light into a phase shifter (Fig. 29, directional couplers Ci1 through CiN, Paragraph [0190]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s light transmission system by substituting Swanson’s modulator and directional couplers for Tanemura’s modulator and demultiplexer. One of ordinary skill in the art would have been motivated to make this modification in order to gain signal processing improvements from extracting additional features and controlling complexity, as suggested by Swanson (Paragraph [0107], [0191]).
Regarding claim 10, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 2, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Regarding claim 11, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 3, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Regarding claim 12, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 4, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Claims 5, 9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tanemura in view of Sayyah et al., US 9310471 B2 (“Sayyah”).
Regarding claim 5, Tanemura discloses the array coherent ranging chip according to claim 1.
Tanemura does not teach: wherein an operating wavelength range of the modulated light source unit comprises a visible band and a near-infrared band.
However, Sayyah teaches a laser diode that may operate in the visible and near-IR spectral regions (Fig. 1A, laser diode 12, Col. 3 lines 6-10).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s laser diode to output both visible and near-infrared wavelengths, as taught by Sayyah. One of ordinary skill in the art would have been motivated to make this modification in order to an adaptability to different operating wavelengths, as suggested by Sayyah (Col. 6 lines 20-28).
Regarding claim 9, Tanemura, as modified in view of Sayyah, discloses the array coherent ranging chip according to claim 5, further comprising any one of a rectangular waveguide, a ridge waveguide and a slot waveguide which are used for transmitting an on-chip optical signal (Tanemura, Fig. 2, waveguide 12, Paragraph [0039]), wherein when the operating wavelength is within the visible band (Sayyah, Fig. 1A, laser diode 12, Col. 3 lines 6-10), a platform that is hybrid-integrated on the basis of silicon nitride and silicon is employed for chip integration, wherein silicon nitride is employed as waveguide material (Tanemura, Fig. 2, waveguide 12, Paragraph [0039]); and when the operating wavelength is within the near-infrared band, chip integration is performed on the basis of a silicon platform disposed on an insulator (Tanemura, Fig. 2, waveguide 12, Paragraph [0039], See also Paragraph [0042]).
Regarding claim 13, Tanemura, as modified in view of Sayyah, discloses the array coherent ranging chip according to claim 5, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tanemura in view of Luff et al., US 20200256956 A1 (“Luff”).
Regarding claim 7, Tanemura discloses the array coherent ranging chip according to claim 6,[…]; and the diffraction structure comprises a waveguide diffraction grating array or a planar waveguide grating (Fig. 15-16, diffractive grating 44, optical waveguide 12c, Paragraph [0125]).
Tanemura does not teach: wherein the on-chip beam expansion structure comprises any one of a thermal insulation inversely tapered waveguide, a planar waveguide concave reflection mirror, a planar waveguide lens based on a waveguide layer with a thickness that gradually changes, a micro-nano-structure based planar waveguide lens with a refractive index that gradually changes, a cascaded beam splitter and a star coupler.
However, Luff teaches a utility waveguide that can include a tapered portion before the facet (Fig. 1, waveguide 16, taper 20, Paragraph [0032]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s waveguide to include a taper at the facet, as taught by Luff. One of ordinary skill in the art would have been motivated to make this modification in order to couple single mode geometry to multi-mode geometry without exciting higher modes, as suggested by Luff (Paragraph [0068]).
Regarding claim 15, Tanemura, as modified in view of Luff, discloses the array coherent ranging chip according to claim7, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Conclusion
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/RACHEL NGUYEN/Examiner, Art Unit 3645
/YUQING XIAO/Supervisory Patent Examiner, Art Unit 3645