DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The following addresses applicant’s remarks/amendments dated 7 May 2026.
The amendment is sufficient to overcome the objection to the abstract.
The amendment is sufficient to overcome the objection to claim 15.
Claims 1, 3-4, 7-9, 11-13, and 15-16 were amended. Claim 2, 6, 10, and 14 was cancelled. No new claims were added. Therefore, claims 1, 3-5, 7-9, 11-13, and 15-16 are currently pending in the current application and are addressed below.
Response to Arguments
Applicant's arguments filed 7 May 2026 have been fully considered but they are not persuasive.
Applicant states three arguments:
(1) Tanemura does not disclose separately converting the reference light and the signal light of each angle or obtaining a plurality of ranging signals after detection
(2) Tanemura does not disclose “the on-chip emission unit comprises an on-chip beam expansion structure and a diffraction structure”
(3) Swanson does not “teach or suggest a light combination assembly that combines the reference light and the reflected light into a composite signal and splits the composite signal into a first detection signal and a second detection signal, or a detector that converts the two detection signals into electrical signals and outputs a difference of the electrical signals as the ranging signal.”
Regarding (1), the amended claim 1 recites the limitation “wherein the reception array is used for receiving the reference light and the multi-angle signal light and respectively performing conversion and detection on both the reference light and the signal light of each angle so as to obtain a plurality of ranging signals.” MPEP 2111.01 I states “under a broadest reasonable interpretation (BRI), words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification.” Tanemura teaches “the reception array is used for receiving the reference light and the multi-angle signal light” through the light receiver 6, light receiving antennas 21, and multiplexers 7 as shown in Fig. 1 (Paragraph [0057], [0063]). Tanemura also teaches “respectively performing conversion and detection on both the reference light and the signal light of each angle so as to obtain a plurality of ranging signals” as each multiplexer 7 corresponds to a distance measurement at a different vertical angle (Paragraph [0047], [0063]). Thus, Tanemura teaches separately performing conversion and detection – through converters 8, TIAs 9, and calculation unit 10 (Fig. 1, Paragraph [0067]-[0068]) – for each angle to obtain a plurality of ranging signals (Paragraph [0082]).
Regarding (2), the amended claim 1 recites the limitation “wherein the on-chip emission unit comprises an on-chip beam expansion structure and a diffraction structure; and wherein the on-chip beam expansion structure is configured to shape and then output the signal light.” Applicant points to a diffusion lens, which is not used in the original rejection. However, under the broadest reasonable interpretation (BRI) of the claim language (MPEP 2111.01 I), the claim limitation does not specify that the diffraction structure is an on-chip element. Nevertheless, Tanemura teaches “the on-chip emission unit comprises an on-chip beam expansion structure” that is “configured to shape and then output the signal light” through scanning unit 5’s phase shifters 20 and optical waveguides 12c (Fig. 1, Paragraph [0049]-[0050]). Tanemura also teaches an on-chip diffractive grating 44, shown in Fig. 15-16 and Paragraph [0125].
Regarding (3), Applicant argues that Swanson does not teach an assembly that combines the reference light and the reflected light into a composite signal. MPEP 2145 IV states that “one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references.” Swanson was not relied on to teach that limitations the Applicant references. Swanson was only relied on to teach “and divide the composite signal into a first detection signal and a second detection signal; wherein the sensor is configured to receive the first detection signal and the second detection signal, convert the first detection signal and the second detection signal into electric signals, and output a difference between the electric signals to obtain the ranging signals.” In Fig. 3, Swanson teaches dividing a signal containing a reference and probe signal into a first detection signal and a second detection signal (Fig. 3, 90 degree hybrid to dual-balanced I and Q channels, Paragraph [0096]). Swanson also teaches an electrical processing module which converts the first and second signals into electric signals and outputs the difference to obtain a ranging signal (Fig. 3, Paragraph [0093], [0097]; See also: claim 137).
Thus, the combination of Tanemura and Swanson teaches the limitations of amended claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-5, 7-9, 11-13, and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a diffraction structure” to refer to a structure that is configured to receive reflected light as well as a structure configured to irradiate the signal light. It is unclear if the same diffraction structure irradiates and receives light or if the diffraction structures are distinct.
Claims 3-5, 7-9, 11-13, and 15-16 are rejected due to dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 8, 11-12, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tanemura et al., US 20200088876 A1 (“Tanemura”) in view of Swanson et al., US 20170299697 A1 (“Swanson”).
Regarding claim 1, Tanemura discloses an array coherent ranging chip, comprising:
a modulated light source unit;
an on-chip emission unit; and
a reception array;
wherein the modulated light source unit is used for generating a modulated light beam (Fig. 1, LD 1, modulator 2, amplifier 3, Paragraph [0036]) and splitting the modulated light beam into signal light and reference light (Fig. 1, demultiplexer 4, Paragraph [0045]), and then outputting the signal light and the reference light (Fig. 1, optical waveguides 12a, optical waveguides 12b, Paragraph [0045]);
wherein the on-chip emission unit is used for irradiating the signal light onto a target object at a preset divergence angle so as to have the signal light reflected to form multi-angle signal light (Fig. 1, scanning unit 5, phase shifters 20, Paragraph [0049]-[0051]);
wherein the reception array is used for receiving the reference light and the multi-angle signal light (Fig. 1, light receiver 6, light receiving antennas 21, multiplexers 7, Paragraph [0057],[0063]-[0064]) and respectively performing conversion and detection on both the reference light and the signal light of each angle so as to obtain a plurality of ranging signals (Fig. 1, converters 8, TIAs 9, Paragraph [0064]-[0065], [0067]-[0068]);
wherein the reception array comprises a plurality of reception units (Fig. 1, light receiver 6, light receiving antennas 21, multiplexers 7, Paragraph [0057],[0063]-[0064]), and each of the reception units comprises a diffraction structure (Fig. 6, light receiving antenna 21, Paragraph [0058]), a light combination assembly (Fig. 1, multiplexers 7, Paragraph [0063]-[0064]) and a detector sensor (Fig. 1, converters 8, Paragraph [0064]-[0065]);
wherein the diffraction structure is configured to receive reflected light of a corresponding angle and guides the reflected light of the corresponding angle to an input end of the light combination assembly (Fig. 6, light receiving antenna 21, waveguide 12, Paragraph [0058]);
wherein the light combination assembly is configured to receive the reference light and the reflected light of the corresponding angle (Fig. 6, light receiving antenna 21, Paragraph [0058]), combine the reference light and the reflected light of the corresponding angle into a composite signal (Fig. 1, multiplexers 7, Paragraph [0063]-[0064]), […];
[…];
wherein the on-chip emission unit comprises an on-chip beam expansion structure (Fig. 1, scanning unit 5, phase shifters 20, optical waveguides 12c, Paragraph [0049]-[0051]) and a diffraction structure (Fig. 15-16, diffractive grating 44, optical waveguide 12c, Paragraph [0125]); and
wherein the on-chip beam expansion structure is configured to shape and then output the signal light (Fig. 1, scanning unit 5, phase shifters 20, optical waveguides 12c, Paragraph [0049]-[0051]); and the diffraction structure is configured to irradiate the signal light, after being shaped, onto a target object at the preset divergence angle so as to have the signal light reflected to form multi-angle signal light (Fig. 15-16, diffractive grating 44, optical waveguide 12c, Paragraph [0125]).
Tanemura does not teach: and divide the composite signal into a first detection signal and a second detection signal;
wherein the sensor is configured to receive the first detection signal and the second detection signal, convert the first detection signal and the second detection signal into electric signals, and output a difference between the electric signals to obtain the ranging signals.
However, Swanson teaches dividing a signal, that consists of a composite signal of reference and probe light, into a first detection signal and a second detection signal (Fig. 3, 90 degree hybrid processor, Ix, Q-x, PD, Paragraph [0096]-[0097]). The first and second detection signals are received by a balanced detection sensor, which then converts the first and second detection signals into electric signals and obtains a ranging signal based on the phase difference between electric signals (Fig. 3, Ix, Q-x, PD, TIA, ADC, DAC, DSP, Paragraph [0093], [0097]; See also: claim 137).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s light receiver system by replacing Tanemura’s converters with Swanson’s coupler and balanced detectors. One of ordinary skill in the art would have been motivated to make this modification in order to gain signal processing improvements from the additional phase information, as suggested by Swanson (Paragraph [0097]).
Regarding claim 3, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 1, wherein the diffraction structure comprises a one-dimensional or two-dimensional diffractive optical element (Tanemura, Fig. 6, light receiving antenna 21, Paragraph [0058]);
wherein the light combination assembly comprises any one of a diffractive optical element, a diffraction grating, a metasurface, a Y-branch, a multimode interference coupler, a directional coupler, a star coupler and a polarizing beamsplitter (Swanson, 90 degree hybrid processor, Paragraph [0096]);
wherein the sensor comprises any one of an avalanche photodiode, a photomultiplier tube and a PIN diode (Tanemura, Fig. 1, converters 8, Paragraph [0065]).
Regarding claim 4, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 1, wherein the modulated light source unit comprises a modulation unit and a beam splitting unit;
wherein the modulation unit comprises a light source and a signal generator (Tanemura, Fig. 1, LD 1, Paragraph [0041]);
wherein the light source has a modulation manner which is external modulation or internal modulation (Tanemura, Fig. 1, modulator 2, Paragraph [0043]),
Tanemura, as modified in view of Swanson, does not teach: an external modulator that comprises an intensity modulator and the beam splitting unit comprises any one of a Y-branch, a star coupler, a multimode interference coupler, a directional coupler, a polarizing beamsplitter, a partially diffractive and partially transmissive waveguide grating.
However, Swanson teaches an external modulator that may be used to set intensity information (Fig. 7, modulator, Paragraph [0107]). Swanson also teaches beam splitting unit that are directional couplers that are used to couple light into a phase shifter (Fig. 29, directional couplers Ci1 through CiN, Paragraph [0190]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s light transmission system by replacing Tanemura’s modulator and demultiplexer with Swanson’s modulator and directional couplers. One of ordinary skill in the art would have been motivated to make this modification in order to gain signal processing improvements from extracting additional features and controlling complexity, as suggested by Swanson (Paragraph [0107], [0191]).
Regarding claim 8, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 1 wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]); and
wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Regarding claim 11, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 3, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]); and
wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Regarding claim 12, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 4, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and
wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Regarding claim 16, Tanemura, as modified in view of Swanson, discloses an array coherent ranging system, comprising a signal processing unit and the array coherent ranging chip according to claim 1, wherein the signal processing unit is configured to receive the ranging signals output by the array coherent ranging chip and calculate a distance from the target object by a spectrum analysis (Tanemura, Fig. 1, calculation unit 10, Paragraph [0070]).
Claims 5, 9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tanemura in view of Swanson in view further of Sayyah et al., US 9310471 B2 (“Sayyah”).
Regarding claim 5, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 1.
Tanemura, as modified in view of Swanson, does not teach: wherein an operating wavelength range of the modulated light source unit comprises a visible band and a near-infrared band.
However, Sayyah teaches a laser diode that may operate in the visible and near-IR spectral regions (Fig. 1A, laser diode 12, Col. 3 lines 6-10).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s laser diode to output both visible and near-infrared wavelengths, as taught by Sayyah. One of ordinary skill in the art would have been motivated to make this modification in order to an adaptability to different operating wavelengths, as suggested by Sayyah (Col. 6 lines 20-28).
Regarding claim 9, Tanemura, as modified in view of Swanson and Sayyah, discloses the array coherent ranging chip according to claim 5, further comprising any one of a rectangular waveguide, a ridge waveguide and a slot waveguide which are used for transmitting an on-chip optical signal (Tanemura, Fig. 2, waveguide 12, Paragraph [0039]), wherein when the operating wavelength is within the visible band (Sayyah, Fig. 1A, laser diode 12, Col. 3 lines 6-10), a platform that is hybrid-integrated on the basis of silicon nitride and silicon is employed for chip integration, wherein silicon nitride is employed as waveguide material (Tanemura, Fig. 2, waveguide 12, Paragraph [0039]); and when the operating wavelength is within the near-infrared band, chip integration is performed on the basis of a silicon platform disposed on an insulator (Tanemura, Fig. 2, waveguide 12, Paragraph [0039], See also Paragraph [0042]).
Regarding claim 13, Tanemura, as modified in view of Swanson and Sayyah, discloses the array coherent ranging chip according to claim 5, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and
wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Tanemura in view of Swanson in further view of Luff et al., US 20200256956 A1 (“Luff”).
Regarding claim 7, Tanemura, as modified in view of Swanson, discloses the array coherent ranging chip according to claim 1,[…]; and
wherein the diffraction structure comprises a waveguide diffraction grating array or a planar waveguide grating (Tanemura, Fig. 15-16, diffractive grating 44, optical waveguide 12c, Paragraph [0125]).
Tanemura, as modified in view of Swanson, does not teach: wherein the on-chip beam expansion structure comprises any one of a thermal insulation inversely tapered waveguide, a planar waveguide concave reflection mirror, a planar waveguide lens based on a waveguide layer with a thickness that gradually changes, a micro-nano-structure based planar waveguide lens with a refractive index that gradually changes, a cascaded beam splitter and a star coupler.
However, Luff teaches a utility waveguide that can include a tapered portion before the facet (Fig. 1, waveguide 16, taper 20, Paragraph [0032]).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Tanemura’s waveguide to include a taper at the facet, as taught by Luff. One of ordinary skill in the art would have been motivated to make this modification in order to couple single mode geometry to multi-mode geometry without exciting higher modes, as suggested by Luff (Paragraph [0068]).
Regarding claim 15, Tanemura, as modified in view of Swanson and Luff, discloses the array coherent ranging chip according to claim 7, wherein on-chip optical elements and on-chip electrical elements are integrated on one chip or respectively on two chips (Tanemura, Fig. 1 shows optical and electrical elements integrated on a single chip, substrate 11, optical waveguides 12, wires 13, calculation unit 10, Paragraph [0036]), and
wherein when integrated respectively on two chips, the two chips are interconnected via an optical signal or an electrical signal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RACHEL N NGUYEN whose telephone number is (571)270-5405. The examiner can normally be reached Monday - Friday 8 am - 5:30 pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yuqing Xiao can be reached at (571) 270-3603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RACHEL NGUYEN/Examiner, Art Unit 3645
/YUQING XIAO/Supervisory Patent Examiner, Art Unit 3645
Prosecution Insights