Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed December 19th, 2025, with respect to the 35 U.S.C. 112 rejections have been fully considered and are persuasive in light of the claim amendments. The 35 U.S.C. 112 rejection has been withdrawn.
2. Applicant's arguments filed December 19th, 2025, with respect to the rejection of claim 16 and its dependents have been fully considered but they are not persuasive.
Applicant argues that Tran fails to teach the limitations of claim 16 as Tran “nowhere discloses or suggests dispatching dependent instructions to another queue” and Tran “teaches keeping dependent instructions and their associated independent instructions in the same queue”, in contrast with the limitations of claim 16.
In response to the above argument, Examiner respectfully disagrees. While Tran does disclose that some instructions maintain their dependent instructions in the same queue, Tran also explicitly states that the exemplary extended load queue entry is used as a means to maintain dependent instructions when an overflow condition occurs in the initial queue where the independent instruction is held (Tran [0024], [0036]). Tran states that “extended queue 206 is used to store dependent instructions that overflow the queue where the related dependent instructions are stored”. As the language of claim 16 merely requires that using the “another queue” occurs “when the respective instruction is a dependent instruction”, the usage of an extended (“another”) queue by Tran for dependent instructions is considered to read on the language of claim 16. Therefore, Applicant’s arguments are not considered persuasive and the rejection is maintained.
The rest of Applicant’s arguments are based on the argument addressed above. The above response is thus applicable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 16-23 and 25-30 are rejected under 35 U.S.C. 103 as being unpatentable over Tran (US 2012/0221835, cited in the IDS dated March 29th, 2023) and Abeed et al (US 2018/0004527, herein Adeeb).
Regarding claim 16, Tran teaches a central processing unit, CPU comprising a plurality of physical registers and instruction queues respectively configured to buffer instructions for execution; the instructions referencing one or more of the physical registers; (Fig 2, [0021], [0025], registers, instruction queues, and scheduling circuitry) the CPU configured to:
when a respective instruction is an independent load instruction ([0029], independent load instructions),
wherein the independent load instruction is a load instruction to load data from an addressable memory into a physical register, and is independent from instructions buffered in the instruction queues through the physical registers, then dispatch the respective instruction to a first queue of the instruction queues ([0026], [0029], [0033-0034], [0039], assign instructions to queues based on dependency indicators); and
when the respective instruction is a dependent instruction dependent on the independent load instruction through the physical registers, then dispatch the respective instruction to another queue of the instruction queues ([0039-0040], execution of independent loads and their dependents through various queues, [0024], [0036], use of extended queue for dependent instructions).
Tran fails to teach the CPU further comprising a dispatching circuitry.
Adeeb teaches a central processing unit comprising dispatching circuitry and instruction queues ([0022], [0035], [0038], [0049], dispatch circuitry and instruction queues).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tran and Adeeb to utilize dispatch circuitry. While Tran does disclose the dispatching of instructions from the various types of queues (Tran [0029]), Tran does not explicitly disclose the use of dispatch circuitry. However, as dispatch circuitry and units are a routine and conventional aspect of the microprocessor art, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 17, the combination of Tran and Adeeb teaches the CPU according to claim 16 wherein the dispatching circuitry is further configured to: when the respective instruction is neither the independent load instruction nor the dependent instruction, dispatch the respective instruction to the first queue (Tran [0026], independent instructions are free to issue).
Regarding claim 18, the combination of Tran and Adeeb teaches the CPU according to claim 16 wherein the dispatching circuitry is further configured to: when the dependent instruction is a load instruction, then dispatch the dependent instruction to a second queue of the instruction queues; and otherwise, dispatch the dependent instruction to a third queue of the instruction queues (Tran Fig 2, additional load and instruction queues, [0039-0040], dependent instruction issuing).
Regarding claim 19, the combination of Tran and Adeeb teaches the CPU according to claim 18 wherein the instruction queues comprise a fourth queue; and wherein the CPU comprises redirecting circuitry configured to redirect a head instruction from the head of the third queue to the fourth queue when the head instruction has not been executed within a time threshold (Tran Fig 2, [0066], [0068], tracking delay times & [0026], changing queues).
Regarding claim 20, the combination of Tran and Adeeb teaches the CPU according to claim 19 wherein the redirecting circuitry further comprises a counter configured to trigger the redirecting of the head instruction after a certain amount of clock cycles and to reset after the redirecting (Tran [0026], [0066-0068]).
Regarding claim 21, the combination of Tran and Adeeb teaches the CPU according to claim 19 wherein the time threshold corresponds to a time for accessing a memory cache (Tran [0026], [0041], cache miss tracking).
Regarding claim 22, the combination of Tran and Adeeb teaches the CPU according to claim 16 further comprising a selection circuitry configured to pop an instruction from one of the instruction queues for further execution (Tran [0034], load arbiter).
Regarding claim 23, the combination of Tran and Adeeb teaches the CPU according to claim 22 wherein the selection circuitry is further configured to perform the popping according to a selection policy (Tran [0034-0036], load arbiter selection).
Regarding claim 25, the combination of Tran and Adeeb teaches the CPU according to claim 16 wherein the dispatching circuitry is further configured to stall when a queue targeted for dispatching is full (Tran [0036]).
Regarding claim 26, the combination of Tran and Adeeb teaches the CPU according to claim 16 wherein the dispatching circuitry is further configured to: when the respective instruction is an independent load instruction, mark at least one destination physical register referenced to by the independent load instruction, when the respective instruction reads a marked physical register, then mark one or more destination physical registers of the respective instruction; and wherein the CPU is configured to, when executing or selecting the respective instruction, unmark one or more of the marked physical registers (Tran [0021], [0032], tagging of source and destination operand dependencies).
Regarding claim 27, the combination of Tran and Adeeb teaches the CPU according to claim 16 further comprising a register renaming circuitry configured to obtain instructions referencing one or more architectural registers, and to rename the referenced architectural registers to one or more of the physical registers (Tran [0021-0022], renaming).
Regarding claim 28, the combination of Tran and Adeeb teaches the CPU according to claim 16 wherein the queues are in-order instruction queues (Tran [0026], in-order queues).
Regarding claim 29, the combination of Tran and Adeeb teaches the CPU according to claim 16 wherein one or more of the queues are out-of-order instruction queues (Tran [0039], out-of-order queues).
Claim 30 refers to a method embodiment of the CPU embodiment of claim 16. Therefore, the above rejection for claim 16 is applicable to claim 30.
Allowable Subject Matter
4. Claim 24 is allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183