DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-14 and 16-20) in the reply filed on 02/11/2026 is acknowledged.
Claim 15 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/16/2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 recites the limitation "the compensation signal line" in page 4 ln. 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-12, 14, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (CN Publication 112331714/Machine Translation Document 12/19/2025) in view of Senda et al. (US Publication 20170287994).
Regarding independent claim 1, Zhang teaches a display substrate (fig. 2A, 10), comprising a base substrate (fig. 3B, 101) and a plurality of display units (fig. 2A, 100) disposed on the base substrate, the display area comprises a plurality of sub-pixels (P1-P4);
the display area is provided with a first power supply line (240 left) and a second power supply line (240 right) along a first direction (D2);
the first power supply line and the second power supply line extend along a second direction (fig. 3A, D1);
the display area is provided with a first scan signal line (151), a second scan signal line (161), a second scan connection line (horizontal parts of 162) and a first scan connection line (horizontal parts of 152) along the second direction (fig. 3A);
the second scan connection line and the second scan signal line are connected to each other to form a first annular structure (fig. 3A, rectangular loop structure formed in scan line 160);
the display area is provided with a third scan connection line (vertical parts of 152) between the first scan signal line and the first scan connection line;
the third scan connection line, the first scan connection line and the first scan signal line are connected to each other to form a second annular structure (fig. 3A, rectangular loop structure formed in scan line 150), and the first direction intersects with the second direction (fig. 3A); and
an orthographic projection of the first annular structure on the base substrate is not overlapped with an orthographic projection of the first power supply line and the second power supply line on the base substrate (fig. 3A, annular structures between 230 do not overlap with 240 left or 240 right);
an orthographic projection of the second annular structure on the base substrate is not overlapped with the orthographic projection of the first power supply line and the second power supply line on the base substrate (fig. 3A, annular structures between 230 at DL2/DL3, 230 and DL1/DL4 do not overlap).
Zhang does not teach wherein each display unit comprises a display area and a transparent area.
Senda teaches wherein each display unit (fig. 3, 1) comprises a display area (100) and a transparent area (200).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Zhang and the display and transparent areas of Senda in order to transmit external light (Senda paragraph 0028).
Regarding dependent claim 2, Zhang further teaches the display substrate according to claim 1, wherein the orthographic projection of the first annular structure on the base substrate is not overlapped with the orthographic projection of the second annular structure on the base substrate (fig. 3A), and the orthographic projection of the second annular structure on the base substrate wraps the orthographic projection of the first annular structure on the base substrate (fig. 3A).
Regarding dependent claim 3, Zhang further teaches the display substrate according to claim 1, wherein in a direction perpendicular to the display substrate, a sub-pixel comprises a drive circuit layer (fig. 3B, all the layers between 101 and 125) disposed on the base substrate and a light emitting structure layer (125) disposed at a side of the drive circuit layer away from the base substrate, the drive circuit layer comprises a first conductive layer (501), a semiconductor layer (104), a second conductive layer (502), and a third conductive layer (503);
the first conductive layer comprises a compensation signal line (fig. 4A, 231, see also machine translation, page 24 paragraph 6) and a first plate (170), the semiconductor layer comprises active layers of a plurality of transistors (fig. 4B),
the second conductive layer comprises the first scan signal line, the second scan signal line, the first scan connection line, the second scan connection line, a second plate (fig. 4C, 180) and gates of the plurality of transistors (fig. 4C),
the third conductive layer comprises the first power supply line, the second power supply line, the third scan connection line, a data signal line, and sources and drains of the plurality of transistors (fig. 4D), and there is an overlapped area between an orthographic projection of the second plate on the base substrate and an orthographic projection of the first plate on the base substrate, so that a first capacitance is formed (fig. 3B);
the second scan connection line and the second scan signal line are connected to each other to form an integrated structure (fig. 3A); and
the third scan connection line is electrically connected to the first scan connection line and the first scan signal line through vias respectively (fig. 3A).
Regarding dependent claim 4, Zhang further teaches the display substrate according to claim 1, wherein at least one of the sub-pixels comprises a first transistor (fig. 2B, T2), a second transistor (TT), a third transistor (T3) and a first capacitor (Cst), the first capacitor comprises a first plate (Cb) and a second plate (Ca),
wherein a gate of the first transistor is electrically connected to the first scan signal line (machine translation, page paragraph), a first electrode of the first transistor is electrically connected to the data signal line (fig. 2B), a second electrode of the first transistor is electrically connected to a gate of the second transistor (fig. 2B), a first electrode of the second transistor is electrically connected to the first power supply line (machine translation, page 25 paragraph 4), a second electrode of the second transistor is electrically connected to a first electrode of an organic light emitting diode (fig. 2B), a gate of the third transistor is electrically connected to the second scan signal line (machine translation, page 33 paragraph 10), a first electrode of the third transistor is electrically connected to the compensation signal line (230), a second electrode of the third transistor is electrically connected to the second electrode of the second transistor (fig. 2B), a second electrode of the organic light emitting diode is electrically connected to the second power supply line (fig. 2B), the first plate is electrically connected to the second electrode of the second transistor (fig. 2B), and the second plate is electrically connected to the gate of the second transistor (fig. 2B).
Regarding dependent claim 5, Zhang further teaches the display substrate according to claim 1, wherein the plurality of sub-pixels comprises a first sub-pixel (fig. 3A, P2), a second sub-pixel (P3), a third sub-pixel (P6), and a fourth sub-pixel (P7), in the first direction, the first sub-pixel and the second sub-pixel are alternately arranged to form a first row (fig. 3A), the third sub-pixel and the fourth sub-pixel are alternately arranged to form a second row (fig. 3A); and
the first scan connection line and the second scan connection line are located in the first sub-pixel and the second sub-pixel respectively (fig. 3A), and the first scan signal line and the second scan signal line are located in the third sub-pixel and the fourth sub-pixel respectively (fig. 3A).
Regarding dependent claim 6, Zhang further teaches the display substrate according to claim 5, wherein at least one of the sub-pixels comprises a first transistor (fig. 2B, T2), a second transistor (T1) and a third transistor (T3), the first transistor comprises a first active layer (T2a), a first gate (T2g), a first source (T2s), and a first drain (T2d), the second transistor comprises a second active layer (T1a), a second gate (T1g), a second source (T1s), and a second drain (T1d), and the third transistor comprises a third active layer (fig. 4B, T3a), a third gate (fig. 4C, T3g), a third source (fig. 4D, T3s), and a third drain (T3d),
wherein an area where the second scan signal line is overlapped with the third active layers in the third sub-pixel and the fourth sub-pixel serves as third gates in the third sub-pixel and the fourth sub-pixel (fig. 3A);
an area where the second scan connection line is overlapped with the third active layers in the first sub-pixel and the second sub-pixel serves as third gates in the first sub-pixel and the second sub-pixel (fig. 3A); and
an area where the first scan signal line is overlapped with the first active layers in the third sub-pixel and the fourth sub-pixel serves as first gates in the third sub-pixel and the fourth sub-pixel (fig. 3A);
an area where the first scan connection line is overlapped with the first active layers in the first sub-pixel and the second sub-pixel serves as first gates in the first sub-pixel and the second sub-pixel (fig. 3A).
Regarding dependent claim 7, Zhang further teaches the display substrate according to claim 6, wherein at least one of the display areas further comprises a compensation signal line (fig. 3A, 230) extending in the second direction;
the first gates, the second gates and the third gates in the first sub-pixel and the second sub-pixel are mirror-symmetrical with respect to a vertical axis (figs. 3A and 4C), the first gates, the second gates and the third gates in the third sub-pixel and the fourth sub-pixel are mirror-symmetrical with respect to the vertical axis (fig. 3A), wherein the vertical axis is the compensation signal line (fig. 3A).
Regarding dependent claim 8, Zhang teaches the display substrate according to claim 7, wherein the compensation signal line is provided with a compensation connection line (fig. 4A, 231) protruding in the first direction and in an opposite direction of the first direction (fig. 4A);
the compensation connection line is located at an abutment position of the first sub-pixel and the third sub-pixel and an abutment position of the second sub-pixel and the fourth sub-pixel (fig. 3A); and
the compensation connection line is electrically connected to the third source of the third transistor through a via (10).
Regarding dependent claim 9, Zhang further teaches the display substrate according to claim 8, wherein the third active layers in the first sub-pixel to the fourth sub-pixel are each disposed at a position close to the compensation connection line (fig. 3A), and there is an overlapped area between an orthographic projection of the third active layers on the base substrate and an orthographic projection of the compensation connection line on the base substrate (fig. 3A, third active layers can be rearranged such that orthographic projection overlaps with orthographic projection of compensation connection line per MPEP 2144.04).
Regarding dependent claim 10, Zhang further teaches the display substrate according to claim 8, wherein the third active layer in the first sub-pixel and the third active layer in the third sub-pixel are connected to each other to form an integrated structure, and the third active layer in the second sub-pixel and the third active layer in the fourth sub-pixel are connected to each other to form an integrated structure (figs. 3A and 4B, T3a of P2 and P3 can be rearranged to form an integrated structure with T3a of P6 and P7 respectively per MPEP 2144.04).
Regarding dependent claim 11, Zhang further teaches the display substrate according to claim 6, wherein at least one of the sub-pixels further comprises a first capacitor (fig. 2B, Cst), the first capacitor comprises a first plate (fig. 4A, Cc) and a second plate (fig. 4B, 180) disposed oppositely, and the second gate is disposed across the second active layer (fig. 3B) and connected to the second plate (fig. 4C) to form an integrated structure.
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Regarding dependent claim 12, Zhang further teaches the display substrate according to claim 11, wherein the first plate in the first sub-pixel is provided with a first opening (fig. 4A, see figure below) at a side close to the third sub-pixel and away from the second sub-pixel (fig. 3A, first opening can be rearranged to be close to P6 and away from P3 per MPEP 2144.04);
the first plate in the second sub-pixel is further provided with the first opening at a side close to the fourth sub-pixel and away from the first sub-pixel (fig. 4A);
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the first plate in the third sub-pixel is provided with a second opening (see figure below) at a side close to the first sub-pixel and close to the fourth sub-pixel (fig. 3A, second opening can be rearranged to be close to P3 and P7 per MPEP 2144.04);
the first plate in the fourth sub-pixel is further provided with the second opening at a side close to the second sub-pixel and close to the third sub-pixel (fig. 3A, second opening can be rearranged to be close to P3 and P6 per MPEP 2144.04); and
the first active layers in the first sub-pixel and the second sub-pixel are each disposed at a position close to the respective first opening, and the first active layers in the third and fourth sub-pixels are each disposed at a position close to the respective second opening (fig. 4B, T1a can be rearranged to be close to their respective first and second openings in their respective sub-pixels per MPEP 2144.04).
Regarding dependent claim 14, Zhang further teaches a display device (fig. 6), including the display substrate of claim 1 (machine translation, page 36 paragraph 3).
Regarding dependent claim 16, Zhang further teaches the display substrate according to claim 1, wherein the first scan signal line and the second scan signal line extend along the first direction and are sequentially arranged along the second direction (fig. 3A).
Regarding dependent claim 17, Zhang further teaches the display substrate according to claim 3, wherein the first power supply line, the data signal line, and the compensation signal line extend along the second direction and are correspondingly disposed along the first direction (fig. 3A).
Regarding dependent claim 18, Zhang further teaches the display substrate according to claim 3, wherein four data signal lines and one compensation signal line are disposed between the first power supply line and the second power supply line, two of the four data signal lines are disposed between the compensation signal line and the first power supply line, and the other two of the four data signal line are disposed between the compensation signal line and the second power supply line (fig. 3A).
Regarding dependent claim 20, Senda further teaches the display substrate according to claim 3, wherein the third conductive layer comprises an auxiliary cathode (fig. 4, 160), and the auxiliary cathode and the second power supply line (ELVSS) are connected to each other to form an integrated structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Zhang and the auxiliary cathode of Senda per the reason(s) stated in claim 1 above.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Senda as applied to claim 11 above, and further in view of Cho et al. (US Publication 20200184903).
Regarding dependent claim 13, Zhang further teaches the display substrate according to claim 11, wherein at least one of the sub-pixels further comprises a second capacitor (fig. 3B, C2), the second capacitor comprises a second plate (Ca) and a third plate (Cb) oppositely disposed, there is an overlapped area between an orthographic projection of the third plate on the base substrate and an orthographic projection of the second plate on the base substrate (fig. 3B).
Zhang in view of Senda does not teach and the third plate is electrically connected to the first plate through a via.
Cho teaches and the third plate (fig. 6, P3) is electrically connected to the first plate (P1) through a via (fig. 7, H2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Zhang in view of Senda and the electric connection between the first and third plates of Cho in order to generate dual storage capacitors (Cho paragraph 0177).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Senda as applied to claim 3 above, and further in view of Ma et al. (US Publication 10756136).
Regarding dependent claim 19, Zhang in view of Senda teaches the display substrate according to claim 3.
Zhang in view of Senda does not teach wherein the second conductive layer comprises a longitudinal power supply connection line and an auxiliary power supply line, the first power supply line is electrically connected to the longitudinal power supply connection line through a via to form a double-layer first power supply trace, and the second power supply line is electrically connected to the auxiliary power supply line through a via to form a double-layer second power supply trace.
Ma teaches wherein the second conductive layer comprises a longitudinal power supply connection line (fig. 11, 25 in 23) and an auxiliary power supply line (25 in 24), the first power supply line is electrically connected to the longitudinal power supply connection line through a via to form a double-layer first power supply trace (23), and the second power supply line is electrically connected to the auxiliary power supply line through a via to form a double-layer second power supply trace (24, see also column 8, ln. 29-31).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display substrate of Zhang in view of Senda and the power supply lines of Ma in order to effectively reduce the voltage drop of the display panel due to the trace resistance (Ma column 8, ln. 32-33).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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