DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on January 29, 2026.
Claims 1-3, 6-7, 13 and 16-17 have been amended. No new claims have been added. Claims 8, 10-12, 15 and 18-19 have been withdrawn. Claim 5 has been canceled. Currently, claims 1-4, 6-7, 9, 13-14 and 16-17 are pending.
Cancellation of claim 5 renders moot the 112(b) rejection of claim 4 set forth in the previous Office Action.
Response to Arguments
Applicant's arguments filed on January 29, 2026 have been fully considered but they are not persuasive. The Applicant argues, “that the steps
(1) removing an exposed portion of the P-type semiconductor layer by in-situ etching with a corrosive gas, by using the patterned mask layer as a mask; and
(2) activating P-type dopant ions in the P-type semiconductor layer that is etched, wherein in the activating step, the patterned mask layer remains; and
(3) growing an N-type semiconductor layer on two sides of the P-type semiconductor layer that is etched and on the heterojunction structure by using the patterned mask layer as the mask after activating P-type doped ions in the P-type semiconductor layer that is etched;
should be viewed as a whole rather than separating the three steps for inventiveness evaluation”.
The Examiner respectfully disagrees with this assessment.
While Zhou teaches etching a p-type GaN layer using a photoresist mask, Zhou does not explicitly teach in-situ etching techniques. However, the adaptation of the etching process in Zhou to an in-situ method using the teachings of Bour, specifically to minimize surface contamination, constitutes a matter of routine engineering optimization.
Furthermore, regarding the sequencing of steps, Zhou discloses the formation of a Mg-doped GaN layer but is silent on the specific timing of activating p-type Mg-doped GaN impurities. Nonetheless, activation is recognized as a necessary step for achieving a functional p-type GaN layer.
Nishimori teaches activating the dopants via annealing prior to etching the p-type GaN layer 5. The sequence of activating the p-type dopant and etching the p-GaN layer presents a finite and predictable set of alternatives. Selecting the order of these steps is a matter of routine optimization.
Furthermore, activating the p-type dopants under a mask is well-known in the art as taught by Agraffeil (US 2016/0093495 A1), applied specifically to limit impairment of the underlying semiconductor layer (see e.g., Figures 2-4).
Finally, Nishimori teaches forming a mask layer 10 on the activated p-type GaN layer 5a and forming AlN layer 6 and AlGaN layer 7 (equivalent to the N-type semiconductor layer) on the two sides of the etched p-type GaN layer 5a. the combination of Zhou, Nishimori and Agraffeil therefore renders the claimed steps obvious.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 6, 9, 13-14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (WO 2018032601 A1; hereafter Zhou) in view of Nishimori et al. (US 2014/0084339 A1; hereafter Nishimori), Bour et al. (US 2014/0045306 A1; hereafter Bour), Chu et al. (US 2019/0207021 A1; hereafter Chu) and Agraffeil (US 2016/0093495 A1).
Regarding claim 1, Zhou teaches a method for manufacturing a semiconductor structure (see e.g., Example 1, Figures 3-4), comprising:
providing a substrate (see e.g., the HEMT device formed on a substrate made of silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride or graphene, Figures 3-4), a heterojunction structure (see e.g., heterostructure including an AlGaN barrier layer and a GaN channel layer, Figures 3-4), and a P-type semiconductor layer, which are distributed from bottom to up (see e.g., p-GaN layer formed over the heterojunction structure having a magnesium doping concentration range from 10 .sup.18 to 10 .sup.21 /cm .sup.3, Figures 3-4);
forming a patterned mask layer on the P-type semiconductor layer, wherein the patterned mask layer covers at least a portion of the P-type semiconductor layer in the gate region; removing an exposed portion of the P-type semiconductor layer by etching with a corrosive gas, by using the patterned mask layer as a mask (see e.g., using a photoresist as a mask the p-GaN layer is etched by inductive coupled plasma etching technique using the mixed gas flow of chlorine, oxygen and nitrogen, Figures 3-4); and
It is understood that the mask covers a portion of the p-type GaN layer in the gate region, since the remaining portion not covered by the mask is etched and later on the non-etched portion of the p-GaN layer a gate electrode is formed.
Zhou does not explicitly teach
“removing …. P-type semiconductor layer by in-situ etching..”
In a similar field of endeavor Bour teaches
removing …. P-type semiconductor layer by in-situ etching (see e.g., in-situ etching of p-type GaN layer 114. The hydrogen rich environment will typically also include the use of ammonia or other suitable nitrogen source during the in-situ etch to stabilize the III-nitride material and prevent the decomposition of the semiconductor materials into metallic portions (e.g., gallium metal produced by the preferential evaporation of nitrogen), Paras [0032] – [0033], Figures 1B-1C)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bour’s teachings of removing …. P-type semiconductor layer by in-situ etching in the method of Zhou is a matter of routine optimization in order to prevent exposure to ambient atmosphere and to ensure superior surface quality.
Zhou does not explicitly teach
“activating P-type dopant ions in the P-type semiconductor layer that is etched,…and growing an N-type semiconductor laver on two sides of the P-type semiconductor laver that is etched and on the heterojunction structure by using the patterned mask laver as the mask after activating P-type doped ions in the P-type semiconductor laver that is etched.”.
While Zhou discloses the formation of a Mg-doped GaN layer, the reference is silent regarding the specific timing of the activation anneal for these impurities. However, it is well-established in the art that activation is a necessary step to convert Mg-doped GaN into a functional, conductive p-type layer.
In a similar field of endeavor Nishimori teaches
activating P-type dopant ions in the P-type semiconductor layer (see e.g., after forming the p-type GaN layer 5 annealing is applied to the p-GaN layer 5 to activate the doped Mg, Para [0044], Figures 2A-2B).
The sequence of activating the p-type dopant and etching the p-GaN layer presents a finite and predictable set of alternatives: either activate first or etch first. Choosing the order of these steps is a matter of routine optimization.
growing an N-type semiconductor layer on two sides of the P-type semiconductor layer that is etched and on the heterojunction structure by using the patterned mask layer as the mask after activating P-type doped ions in the P-type semiconductor layer that is etched (see e.g., a mask layer 10 covers an upper surface of the p-type GaN layer 5a. Then an AlN layer 6 and an AlGaN layer 7 are formed, using MOVPE method, on the two sides of the activated p-type GaN layer 5a and on the underlying III-V semiconductor layers, Paras [0049], [0050], Figure 2C).
The two sides of the P-type semiconductor layer maybe completely covered by the carier providing layer 110 (N-type semiconductor layer) as taught by Chu (see e.g., Figure 1D).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Nishimori’s teachings of activating P-type dopant ions in the P-type semiconductor layer that is etched .. growing an N-type semiconductor layer on two sides of the P-type semiconductor layer that is etched and on the heterojunction structure by using the patterned mask layer as the mask after activating P-type doped ions in the P-type semiconductor layer that is etched in the method of Zhou in order to combine known elements according to known methods to yield predictable results.
Zhou does not explicitly teach
“wherein in the activating step, the patterned mask layer remains;”
In a similar field of endeavor Agraffeil provides a generic teaching of forming a cap layer 2 (see e.g., Figure 3) before or after implantation and before the heat treatment step for activation of the dopant impurities on semiconductor layer 1b (see e.g., Para [0041]). Agraffeil teaches that this capping layer limits the dopant species dose loss and increases the thermal activation budget undergone by semiconductor layer 1b. Heat treatments performed at higher temperature and therefore over a shorter period can be envisaged, which enables the method to be implemented in a shorter time. The activation ratio of dopant impurities 3 is also improved.
Therefore, it would have been obvious to one skilled dint he art at the time the invention was effectively filed to adapt the process in Zhou to maintain the patterned mask layer during the activation step, essentially using it as a cap layer taught by Agraffeil. This modification would yield predictable results, namely preventing surface damage, limiting dopant out-diffusion and permitting higher activation temperatures over a shortened duration to improve process efficiency.
Regarding claim 3, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 1 as mentioned above. Zhou further teaches
wherein a material of the P-type semiconductor layer is GaN (see e.g., the p-type layer is P-GaN, Figures 3-4), removing the exposed portion of the P-type semiconductor layer by etching ….the corrosive gas comprises one or both of H2 or NH3, a mixture of Cl2 and N2, or HCl (see e.g., exposed portions of the p-GaN layer are etched using mixed gas chloring, oxygen and nitrogen).
Zhou does not explicitly teach
“removing .. the P-type semiconductor layer by in-situ etching is performed at a temperature higher than 300..”
In a similar field of endeavor Bour teaches
removing … the P-type semiconductor layer by in-situ etching is performed at a temperature higher than 300 (see e.g., the temperature range during the in-situ etching of p-type GaN layer 114 is performed at a temperature range from about 1020.degree. C. to about 1080.degree. C., for instance about 1040.degree. C.-1050.degree. C, Paras [0032], [0033], Figures 1B and 1C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bour’s teachings of removing … the P-type semiconductor layer by in-situ etching is performed at a temperature higher than 300 in the method of Zhou as this is a routine parameter choice based on semiconductor physics. High temperatures are suitable for removal of III-nitride layers.
Regarding claim 4, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 3 as mentioned above. Zhou does not explicitly teach
“wherein removing the exposed portion of the P-type semiconductor layer by in-situ etching is performed at a temperature higher than 700 °C”.
In a similar field of endeavor Bour teaches
wherein removing the exposed portion of the P-type semiconductor layer by in-situ etching is performed at a temperature higher than 700 °C (see e.g., the temperature range during the in-situ etching of p-type GaN layer 114 is performed at a temperature range from about 1020.degree. C. to about 1080.degree. C., for instance about 1040.degree. C.-1050.degree. C, Paras [0032], [0033], Figures 1B and 1C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bour’s teachings of wherein removing the exposed portion of the P-type semiconductor layer by in-situ etching is performed at a temperature higher than 700 °C in the method of Zhou as this is a routine parameter choice based on semiconductor physics. High temperatures are suitable for removal of III-nitride layers.
Regarding claim 6, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 1 as mentioned above. Zhou does not explicitly teach
“wherein a material of the N-type semiconductor layer is GaN or AlGaN”.
In a similar field of endeavor Chu teaches
wherein a material of the N-type semiconductor layer is GaN or AlGaN (see e.g., the carrier providing layer 110 includes InAlGaN, AlGaN, AlInN, AlN, GaN or a combination thereof and maybe doped, Para [0040], Figures 1C and 1D)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chu’s teachings of wherein a material of the N-type semiconductor layer is GaN or AlGaN in the method of Zhou to enhance device performance.
Regarding claim 9, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 3 as mentioned above. Zhou further teaches
wherein a material of the heterojunction structure adjacent to the P-type semiconductor layer is AlGaN (see e.g., an AlGaN layer is adjacent to the p-GaN layer, Figures 3-4).
Regarding claim 13, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 1 as mentioned above. Zhou does not explicitly teach
“wherein P-type dopant ions in the P-type semiconductor layer are activated by annealing at a temperature greater than 500 °C”.
In a similar field of endeavor Nishimori teaches
wherein P-type dopant ions in the P-type semiconductor layer is activated by annealing at a temperature greater than 500 °C (see e.g., annealing is applied to p-GaN layer 5, for example, at 800.degree. C. for about 20 minutes to activate the doped Mg, Para [0044], Figure 2).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Nishimori’s teachings of wherein P-type dopant ions in the P-type semiconductor layer is activated by annealing at a temperature greater than 500 °C in the method of Zhou in order to make the p-GaN functional.
Regarding claim 14, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 1 as mentioned above. Zhou does not explicitly teach
“wherein a material of the patterned mask layer is silicon dioxide, silicon nitride or silicon oxynitride”.
In a similar field of endeavor Bour teaches
wherein a material of the patterned mask layer is silicon dioxide, silicon nitride or silicon oxynitride (see e.g., the masking layer 116 may include dielectrics such as silicon oxides (Si.sub.xO.sub.y), silicon nitrides (Si.sub.xN.sub.y), silicon oxynitrides (SiON), Para [0027], Figures 1A and 1B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Bour’s teachings of wherein a material of the patterned mask layer is silicon dioxide, silicon nitride or silicon oxynitride in the method of Zhou in order to use masks which are stable and inert in the high temperature reactor environment.
Regarding claim 16, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 1 as mentioned above. Zhou further teaches
further comprising, removing the patterned mask layer to expose the P-type semiconductor layer (see e.g., the p-GaN layer is etched under a mask and the mask is removed to expose the patterned p-GaN layer, Figures 3 and 4).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (WO 2018032601 A1; hereafter Zhou) in view of Nishimori et al. (US 2014/0084339 A1; hereafter Nishimori), Bour et al. (US 2014/0045306 A1; hereafter Bour), Chu et al. (US 2019/0207021 A1; hereafter Chu) and Agraffeil (US 2016/0093495 A1) and further in view of Lin et al. (US 2019/0207012 A1; hereafter Lin).
Regarding claim 2, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 1 as mentioned above. Zhou does not explicitly teach
“wherein the in-situ etching comprises:
forming and etching the patterned mask layer in one reaction chamber, or in different chambers of one vacuum interconnect device”.
In a similar field of endeavor Lin teaches
wherein the in-situ etching comprises:
forming and etching the patterned mask layer in one reaction chamber, or in different chambers of one vacuum interconnect device (see e.g., etching the silicon-containing insulating layer 104 and etching the GaN-based semiconductor layer 102 are sequentially performed in the same etching chamber 502, Paras [0031] – [0033], Figures 1B-1D).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein the in-situ etching comprises: forming and etching the patterned mask layer in one reaction chamber, or in different chambers of one vacuum interconnect device in the method of Zhou so that by in-situ etching the silicon-containing insulating layer and the GaN-based semiconductor layer, the production efficiency of semiconductor devices containing the semiconductor structure can be enhanced.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (WO 2018032601 A1; hereafter Zhou) in view of Nishimori et al. (US 2014/0084339 A1; hereafter Nishimori), Bour et al. (US 2014/0045306 A1; hereafter Bour), Chu et al. (US 2019/0207021 A1; hereafter Chu) and Agraffeil (US 2016/0093495 A1) and further in view of Yang et al. (CN 107742644 A; hereafter Yang).
Regarding claim 17, Zhou, as modified by Bour, Nishimori, Chu and Agraffeil, teaches the limitations of claim 1 as mentioned above. Zhou further teaches
further comprising, removing the patterned mask to expose the P-type semiconductor layer that is etched (see e.g., the p-GaN layer is etched under a mask and the mask is removed to expose the patterned p-GaN layer, Figures 3 and 4).
Zhou does not explicitly teach
“the patterned mask layer removed using wet etching”.
In a similar field of endeavor Yang teaches
the patterned mask layer removed using wet etching (see e.g., the SiO2 mask layer 9 on the gate region may be removed by wet etching, Figures 1-10).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Yang’s teachings of the patterned mask layer removed using wet etching in the method of Zhou in order to use a predictable application of a known technique to achieve mask removal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAKEHA SEHAR/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893