DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 02/04/2026. Claims 1-2, 4-11, and 13-19 are pending in this application. Claims 1, 4, 7, and 13 are amended. Claims 18-19 are new.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 01/28/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 11, 14-16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Mevellec et al. (WO 2020/161256; hereinafter ‘Mevellec’) in view of Liu (US 2020/0091164) and Senna et al. (Journal of Applied Electrochemistry 33: 1155–1161, 2003; hereinafter ‘Senna’).
Regarding claim 1, Mevellec teaches a process for fabricating a semiconductor device (p.13, lines 30-32), said process comprising the steps (the electrochemical process, p.9, line 25-p.10, line 4) of
a) electrodepositing an alloy of copper and of a dopant metal (electrodepositing the alloy of the first metal selected from Cu and the second metal, p.5, lines 4-5)
by bringing a first surface of a metal layer into contact (by bringing the first (conductive) surface of a metallic seed layer, p.7, lines 2-4; p.10, lines 5-6)
with an electrolyte comprising copper (II) ions and dopant metal ions (the electrolyte comprising Cu II ions and metal ions selected from Mn II ions or Zn II ions, p.5, lines 7-8, 10), and then
polarizing said first surface (polarizing the first surface in ramp mode, galvano-static mode, and galvano-pulsed mode, p.9, line 30; p.11, lines 14-15)
for a time sufficient to cover it with the copper-dopant metal alloy (for a period of time sufficient to carry out conformal and complete filling with the alloy of Cu-Mn or Cu-Zn, p.9, lines 30-33), and
b) annealing the alloy to cause it to separate (annealing the alloy deposit of Cu-Mn or Cu-Zn forming two layers, p.12, lines 20-23) and
form a first layer of copper and a second layer comprising the dopant metal and/or an oxide thereof (form the first layer comprising essentially Cu, and the second layer comprising essentially Mn or Zn),
wherein the dopant metal is selected from the group consisting of manganese and zinc (the second metal is selected from Mn or Zn, p.5, lines 5-6).
Mevellec does not teach that the semiconductor device is a 3D-NAND flash memory.
Liu teaches a process (FIG. 3E, [0012]) for fabricating a 3D-NAND flash memory (3D memory device is a NAND flash memory device, [0031]), including formation of conductive interconnect structures and bit lines using electroplating/electrodeposition techniques [0059-0060].
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec to obtain and achieve the process for fabricating the 3D-NAND flash memory as claimed, because vertically stacked 3D-NAND memory devices include conductive bit lines and semiconductor interconnect structures (Liu: [0031, 0039-0040]) to which the Cu-Mn/Cu-Zn alloy electrodeposition and annealing process of Mevellec would have been applicable for conformal filling and Mn/Zn interface formation in semiconductor interconnect structures (Mevellec: p.9, lines 30-33; p12, lines 20-23).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Mevellec due to above reason.
Mevellec in view of Liu does not teach the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0.
Senna teaches a process (2.2. Alloy electrodeposition experiments) wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0 (the electrolyte for Cu-Zn alloy electrodeposition is maintained at pH 8.0 (2.1. Cathodic polarization curves).
As taught by Senna, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec in view of Liu to obtain and achieve the process the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0 as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Senna in combination with Mevellec in view of Liu due to above reason.
Regarding claim 2, Mevellec in view Liu and Senna teaches the process as claimed in claim 1, Mevellec in view of Senna does not teach the process wherein the first layer of copper forms a copper bit line of the 3D-NAND flash memory.
Liu teaches the process wherein the first layer of copper forms a copper bit line of the 3D-NAND flash memory (330 is the bit line of the 3D-NAND flash memory and includes Cu, [0059-0060]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Liu to obtain and achieve the process wherein the first layer of copper forms a copper bit line of the 3D-NAND flash memory as claimed, because copper is a well-known material and widely used as a bit line in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Regarding claim 11, Mevellec in view of Liu and Senna teaches the process as claimed in claim 1, wherein the metal layer is a trench-filling copper deposit, and the step of electrodepositing the copper-dopant metal alloy is performed for a time sufficient to cover the trench-filling copper deposit, in order to form an alloy deposit (Mevellec: the electrodeposition step is stopped when the alloy deposit covers the flat surface of the substrate, which indicates that the cavities have been completely filled with the alloy, p.12, lines 6-9).
Although, Mevellec in view of Liu and Senna does not explicitly teach the process wherein the first copper layer formed as a result of the annealing step being subsequently polished in a third chemical-mechanical polishing step.
Mevellec, however, provides that the cavities are obtained by implementation of a damascene process, which involves filling metal into trenches or vias, forming an overburden metal layer, and planarizing the surface by CMP (p.10, lines 18-19).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Mevellec to obtain and achieve the process, wherein the second surface of the metal layer in contact with the conducting area being made of a contact metal selected from tungsten, molybdenum, cobalt and ruthenium as claimed, because CMP is part of the damascene process, as planarization of the overfilled metal layers is a necessary step to complete the interconnect formation.
Regarding claim 14, Mevellec in view of Liu and Senna teaches the process as claimed in claim 1, wherein the electrolyte comprising copper (II) ions and dopant metal ions comprises a concentration of copper (II) ions between 1 mM and 12 mM, wherein the copper (II) ions are substantially in the form of complexes (Mevellec: the concentration of Cu (II) ions is from 15.74 mM to 78.68 mM, p.2, line 31).
Regarding claim 15, Mevellec in view of Liu and Senna teaches the process as claimed in claim 1, but Mevellec in view of Liu does not teach the process wherein the electrolyte comprising copper (II) ions and dopant metal ions is substantially free of chloride ions.
Senna teaches the process wherein the electrolyte comprising copper (II) ions and dopant metal ions is substantially free of chloride ions (the electrolyte of Cu-Zn alloy is free of chloride ions, 2.2. Alloy electrodeposition experiments).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Senna to obtain and achieve the process wherein the electrolyte comprising copper (II) ions and dopant metal ions is substantially free of chloride ions as claimed, because pyrophosphate serves as a complexing and buffering agent that replaces the functions of chloride ions by stabilizing Cu and Zn ions and enabling their uniform co-deposition (3.2.1. Chemical composition of the coatings).
Regarding claim 16, Mevellec in view of Liu and Senna teaches the process as claimed in claim 1, but Mevellec in view of Liu does not teach the process wherein the electrolyte comprising copper (II) ions and dopant metal ions further comprises a sulfur salt of copper (II) ions.
Senna teaches the process wherein the electrolyte comprising copper (II) ions and dopant metal ions further comprises a sulfur salt of copper (II) ions (the electrolyte of Cu-Zn alloy is further comprising CuSO4, Table 1).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Senna to obtain and achieve the process wherein the electrolyte comprising copper (II) ions and dopant metal ions further comprises a sulfur salt of copper (II) ions as claimed, because CuSO4 is a known material and widely used as a source of copper ions in electroplating electrolyte. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Regarding claim 18, Mevellec teaches a process for fabricating a semiconductor device (p.13, lines 30-32), said process comprising the steps (the electrochemical process, p.9, line 25-p.10, line 4) of
a) electrodepositing an alloy of copper and of a dopant metal (electrodepositing the alloy of the first metal selected from Cu and the second metal, p.5, lines 4-6)
by bringing a first surface of a metal layer into contact (by bringing the first (conductive) surface of a metallic seed layer, p.7, lines 2-4; p.10, lines 5-6)
with an electrolyte comprising copper (II) ions and dopant metal ions (the electrolyte comprising Cu II ions and metal ions selected from Mn II ions or Zn II ions, p.5, lines 7-8, 10), and then
polarizing said first surface (polarizing the first surface in ramp mode, galvano-static mode, and galvano-pulsed mode, p.9, line 30; p.11, lines 14-15)
for a time sufficient to cover it with the copper-dopant metal alloy (for a period of time sufficient to carry out conformal and complete filling with the alloy of Cu-Mn or Cu-Zn, p.9, lines 30-33), and
b) annealing the alloy to cause it to separate (annealing the alloy deposit of Cu-Mn or Cu-Zn forming two layers, p.12, lines 20-23) and
form a first layer of copper and a second layer comprising the dopant metal and/or an oxide thereof (form the first layer comprising essentially Cu, and the second layer comprising essentially Mn or Zn),
wherein the dopant metal is selected from the group consisting of manganese and zinc (the second metal is selected from Mn or Zn, p.5, lines 4-6),
wherein the electrolyte comprising copper (II) ions and dopant metal ions (the electrolyte comprising the first metal and the second metal, p.2, lines 27-29) comprises a concentration of copper (II) ions between 1 mM and 120 mM, wherein the copper (II) ions are substantially in the form of complexes (copper II ions in a concentration corresponding to approximately 16 mM to 79 mM, based on a Cu 2+ concentration of 1 g/L to 5 g/L, p.2, line 31).
Mevellec does not teach that the semiconductor device is a 3D-NAND flash memory.
Liu teaches a process (FIG. 3E, [0012]) for fabricating a 3D-NAND flash memory (3D memory device is a NAND flash memory device, [0031]), including formation of conductive interconnect structures and bit lines using electroplating/electrodeposition techniques [0059-0060].
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec to obtain and achieve the process for fabricating the 3D-NAND flash memory as claimed, because vertically stacked 3D-NAND memory devices include conductive bit lines and semiconductor interconnect structures (Liu: [0031, 0039-0040]) to which the Cu-Mn/Cu-Zn alloy electrodeposition and annealing process of Mevellec would have been applicable for conformal filling and Mn/Zn interface formation in semiconductor interconnect structures (Mevellec: p.9, lines 30-33; p12, lines 20-23).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Mevellec due to above reason.
Mevellec in view of Liu does not teach the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0.
Senna teaches a process (2.2. Alloy electrodeposition experiments) wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0 (the electrolyte for Cu-Zn alloy electrodeposition is maintained at pH 8.0 (2.1. Cathodic polarization curves).
As taught by Senna, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec in view of Liu to obtain and achieve the process the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0 as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Senna in combination with Mevellec in view of Liu due to above reason.
Claims 1 and 13 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Mevellec (WO 2020/161256) in view of Liu (US 2020/0091164) and Joi et al. (Journal of The Electrochemical Society, 160 (12) D3145-D3148, 2013; hereinafter ‘Joi’).
Regarding claim 1, Mevellec teaches a process for fabricating a semiconductor device (p.13, lines 30-32), said process comprising the steps (the electrochemical process, p.9, line 25-p.10, line 4) of
a) electrodepositing an alloy of copper and of a dopant metal selected from manganese and zinc (electrodepositing the alloy of the first metal selected from Cu and the second metal, p.5, lines 4-5)
by bringing a first surface of a metal layer into contact (by bringing the first (conductive) surface of a metallic seed layer, p.7, lines 2-4; p.10, lines 5-6)
with an electrolyte comprising copper (II) ions and dopant metal ions (the electrolyte comprising Cu II ions and metal ions selected from Mn II ions or Zn II ions, p.5, lines 7-8, 10), and then
polarizing said first surface (polarizing the first surface in ramp mode, galvano-static mode, and galvano-pulsed mode, p.9, line 30; p.11, lines 14-15)
for a time sufficient to cover it with the copper-dopant metal alloy (for a period of time sufficient to carry out conformal and complete filling with the alloy of Cu-Mn or Cu-Zn, p.9, lines 30-33), and
b) annealing the alloy to cause it to separate (annealing the alloy deposit of Cu-Mn or Cu-Zn forming two layers, p.12, lines 20-23) and
form a first layer of copper and a second layer comprising the dopant metal and/or an oxide thereof (form the first layer comprising essentially Cu, and the second layer comprising essentially Mn or Zn),
wherein the dopant metal is selected from the group consisting of manganese and zinc (the second metal is selected from manganese and zinc, p.5, lines 5-6).
Mevellec does not teach that the semiconductor device is a 3D-NAND flash memory.
Liu teaches a process (FIG. 3E, [0012]) for fabricating a 3D-NAND flash memory (3D memory device is a NAND flash memory device, [0031]), including formation of conductive interconnect structures and bit lines using electroplating/electrodeposition techniques [0059-0060].
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec to obtain and achieve the process for fabricating the 3D-NAND flash memory as claimed, because vertically stacked 3D-NAND memory devices include conductive bit lines and semiconductor interconnect structures (Liu: [0031, 0039-0040]) to which the Cu-Mn/Cu-Zn alloy electrodeposition and annealing process of Mevellec would have been applicable for conformal filling and Mn/Zn interface formation in semiconductor interconnect structures (Mevellec: p.9, lines 30-33; p12, lines 20-23).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Mevellec due to above reason.
Mevellec in view of Liu does not teach the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0.
Joi teaches a process (Experimental) wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0 (the electrolyte of Cu-Mn electrodeposition has a 6.5 pH).
As taught by Joi, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec in view of Liu to obtain and achieve the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0 as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Joi in combination with Mevellec in view of Liu due to above reason.
Regarding claim 13, Mevellec in view of Liu and Joi teaches the process as claimed in claim 1, Mevellec in view of Liu does not teach the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.5 and 7.5.
Joi teaches the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.5 and 7.5 (the electrolyte of Cu-Mn electrodeposition has a 6.5 pH).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Joi to obtain and achieve the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.5 and 7.5 as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Claims 4-10 are rejected under 35 U.S.C. 103 as being unpatentable over Mevellec (WO 2020/161256) in view of Liu (US 2020/0091164) and Senna (Journal of Applied Electrochemistry 33: 1155–1161, 2003), and further in view of Kim et al. (US 2012/0012465; hereinafter ‘Kim’).
Regarding claim 4, Mevellec in view of Liu and Senna teaches the process as claimed in claim 1,
wherein the metal layer comprises a second surface (Mevellec: the metallic seed layer comprises a second surface, p.10, lines 5-7)
which is in contact with an insulating area (the second surface in contact with an insulating area comprising silicon dioxide), said
insulating area being made of a dielectric material (the insulating area is made of a dielectric material).
Mevellec in view of Senna does not teach the process, wherein the second surface of the metal layer in contact with the conducting area being made of a contact metal selected from the group consisting of tungsten, molybdenum, cobalt and ruthenium, and the contact metal being intended to connect a copper bit line and a polysilicon channel of the 3D-NAND flash memory.
Liu teaches the process, wherein the contact metal (328, [0059]) being intended to connect (shown in FIG. 3) a copper bit line (33, which include Cu, [0060]) and a polysilicon channel of the 3D-NAND flash memory (202 is part of 200 including polysilicon, and 200 in FIG. 2 corresponds to 326 in FIG. 3E, FIG. 2, [0034]).
Although, Liu does not explicitly teach the process, wherein the second surface of the metal layer in contact with the conducting area being made of a contact metal selected from the group consisting of tungsten, molybdenum, cobalt and ruthenium.
Liu, however, recognizes that the contact metal for interconnect lines and via contacts includes conductive materials such as tungsten and cobalt [0029].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Liu to obtain and achieve the process, wherein the second surface of the metal layer in contact with the conducting area being made of a contact metal selected from the group consisting of tungsten, molybdenum, cobalt and ruthenium, and the contact metal being intended to connect a copper bit line and a polysilicon channel of the 3D-NAND flash memory as claimed, because tungsten and cobalt are well-known materials that are widely used as the contact metal and copper and polysilicon are well-known materials that are widely used as the bit line and the channel in the 3D-NAND flash memory. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Mevellec in view of Liu and Senna does not teach the process, wherein the metal layer comprises a second surface which is in contact with a mixed surface comprising both an insulating area and a conducting area, said insulating area being made of a dielectric material and said conducting area being made of a contact metal.
Kim teaches a process (FIG. 1, [0015]), wherein the metal layer (222 functions as a single seed layer, FIGS. 2 and 3A, [0020-0021]) comprises a second surface (the outer surface of 222)
which is in contact with a mixed surface (the outer surface of 222 is in contact with 210 and 208, [0021]) comprising both an insulating area (210 comprising an insulating area by 212, [0016]) and a conducting area (208 comprising a conductive area by 220), said
insulating area being made of a dielectric material (212 includes a dielectric material) and said
conducting area being made of a contact metal (220 includes a conductive material).
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec in view of Liu and Senna to obtain and achieve the process, wherein the metal layer comprises a second surface which is in contact with a mixed surface comprising both an insulating area and a conducting area, said insulating area being made of a dielectric material and said conducting area being made of a contact metal as claimed, because the seed layer contacts both a dielectric and a metal area, creating a potential difference at their interface, which acts as an electrical entry point where electrodeposition initiates to ensure electrical continuity and void-free bottom-up fill [0020, 0028].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Mevellec in view of Liu and Senna due to above reason.
Regarding claim 5, Mevellec in view of Liu, Senna, and Kim teaches the process as claimed in claim 4, Mevellec in view of Liu and Senna does not teach the process wherein during the step of annealing the alloy the dopant metal migrates to the mixed surface, and in that the second layer comprising the dopant metal and/or an oxide thereof covers at least the insulating area of the mixed surface.
Kim teaches the process wherein during the step of annealing the alloy (annealing 222, FIG. 2, [0027])
the dopant metal migrates to the mixed surface (Mn migrates to the outer surface of 222), and
in that the second layer comprising the dopant metal and/or an oxide thereof covers at least the insulating area of the mixed surface (the oxide layer comprising Mn covers 210).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Kim to obtain and achieve the process wherein during the step of annealing the alloy the dopant metal migrates to the mixed surface, and in that the second layer comprising the dopant metal and/or an oxide thereof covers at least the insulating area of the mixed surface as claimed, because Mn having a strong affinity for oxygen reacts with available oxygen contained in the dielectric material to form a oxide layer at the interface [0027].
Regarding claim 6, Mevellec in view of Liu, Senna, and Kim teaches the process as claimed in claim 5, Mevellec in view of Liu and Senna does not teach the process wherein the second layer comprises an oxide of the dopant metal and functions as a copper diffusion barrier.
Kim teaches the process wherein the second layer comprises an oxide of the dopant metal and functions as a copper diffusion barrier (the oxide layer comprises Mn and function as a Cu diffusion barrier, [0027]).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Kim to obtain and achieve the process wherein the second layer comprises an oxide of the dopant metal and functions as a copper diffusion barrier as claimed, because forming a barrier layer on the opposite surface of the seed layer allows a thinner and lower-resistance barrier/seed structure, thereby improving device performance and process scalability for sub-22 nm nodes [0029].
Regarding claim 7, Mevellec in view of Liu, Senna, and Kim teaches the process as claimed in claim 4, wherein the metal layer is a metal seed layer selected from the group consisting of copper, a copper alloy, and tantalum (Mevellec: the metallic seed layer selected from the group consisting of copper, copper alloy, and tantalum, p.10, lines 7-9), said seed layer having been deposited in contact with the mixed surface of an insulating area and a conducting area, in a step prior to the first electrodeposition step (prior to electrodeposition, the metallic seed layer is already formed to provide a conductive surface for the subsequent electrodeposition process, p.7, lines 2-4).
Regarding claim 8, Mevellec in view of Liu, Senna, and Kim teaches the process as claimed in claim 7, but Mevellec in view of Liu and Senna does not teach the process wherein a portion of the firs surface of the metal seed layer is concave, defining a hollow delimited by the walls and bottom of a trench.
Kim teaches the process wherein a portion of the firs surface of the metal seed layer is concave (the inner surface of 222, FIG. 2, [0020]), defining a hollow delimited by the walls and bottom of a trench (shown in FIG. 2).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Kim to obtain and achieve the process wherein a portion of the firs surface of the metal seed layer is concave, defining a hollow delimited by the walls and bottom of a trench as claimed, because a concave-shaped seed layer is advantageous for vertical interconnect growth , as it helps prevent void formation and ensures a continuous conductive path [0017].
Regarding claim 9, Mevellec in view of Liu, Senna, and Kim teaches the process as claimed in claim 8, but does not explicitly teach the process wherein the trench hollow has an average width at the opening ranging from 15 nm to 700 nm and an average depth ranging from 30 nm to 500 nm.
Kim, however, provides that as the device nodes approach dimensions of approximately 22 nm, the interconnect trench exhibits a height-to-width aspect ratio of at least about 5:1. Accordingly, it would have been understood that the trench opening has a width of about 22 nm and a depth of approximately 110 nm [0003, 0017].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Kim to obtain and achieve the process wherein the trench hollow has an average width at the opening ranging from 15 nm to 700 nm and an average depth ranging from 30 nm to 500 nm as claimed, because it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Alter, 105 USPQ 233.
Regarding claim 10, Mevellec in view of Liu, Senna, and Kim teaches the process as claimed in claim 8, wherein the first step of electrodepositing the copper-dopant metal alloy is performed for a time sufficient to fill the hollow with said alloy (Mevellec: the electrodeposition step is stopped when the alloy deposit covers the flat surface of the substrate, which indicates that the cavities have been completely filled with the alloy, p.9, lines 30-33).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Mevellec (WO 2020/161256) in view of Liu (US 2020/0091164) and Senna (Journal of Applied Electrochemistry 33: 1155–1161, 2003), and further in view of Ceng (CN104630839A).
Regarding claim 17, Mevellec in view of Liu and Senna teaches the process as claimed in claim 1, but does not teach the process wherein the electrolyte comprising copper (II) ions and dopant metal ions further comprises a copper (II) ion complexing agent selected from aliphatic polyamines having 2 to 4 amino groups in a molar concentration such that the ratio between the molar concentration of complexing agent and the molar concentration of copper (II) ions ranges from 1:1 and 3:1.
Ceng teaches a process ([0002]) further comprises a copper (II) ion complexing agent selected from aliphatic polyamines having 2 to 4 amino groups (ethylenediamine is the complexing agent having 2 amino groups, [0013]) in a molar concentration such that the ratio between the molar concentration of complexing agent and the molar concentration of copper (II) ions ranges from 1:1 and 3:1 (the ratio between the molar concentration of complexing agent and the molar concentration of copper (II) ions is 2.91:1, since electrolyte contains 100 g/L of CuSO4·5HO (0.4005 M Cu2+) and 70g/L of ethylenediamine (1.1648 M), [0011]).
As taught by Ceng, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec in view of Liu and Senna to obtain and achieve the process wherein the electrolyte comprising copper (II) ions and dopant metal ions further comprises a copper (II) ion complexing agent selected from aliphatic polyamines having 2 to 4 amino groups in a molar concentration such that the ratio between the molar concentration of complexing agent and the molar concentration of copper (II) ions ranges from 1:1 and 3:1 as claimed, because ethylenediamine is well-known materials that are widely used as the complexing agent for electroplating solution, and it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). Further, it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ceng in combination with Mevellec in view of Liu and Senna due to above reason.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Mevellec (WO 2020/161256) in view of Liu (US 2020/0091164) and Senna (Journal of Applied Electrochemistry 33: 1155–1161, 2003), and further in view Kim et al. (US 2018/0286874; hereinafter ‘Kim’).
Regarding claim 19, Mevellec teaches a process for fabricating a semiconductor device (p.13, lines 30-32), said process comprising the steps (the electrochemical process, p.9, line 25-p.10, line 4) of
a) electrodepositing an alloy of copper and of a dopant metal (electrodepositing the alloy of the first metal selected from Cu and the second metal, p.5, lines 4-6)
by bringing a first surface of a metal layer into contact (by bringing the first (conductive) surface of a metallic seed layer, p.7, lines 2-4; p.10, lines 5-6)
with an electrolyte comprising copper (II) ions and dopant metal ions (the electrolyte comprising Cu II ions and metal ions selected from Mn II ions or Zn II ions, p.5, lines 7-8, 10), and then
polarizing said first surface (polarizing the first surface in ramp mode, galvano-static mode, and galvano-pulsed mode, p.9, line 30; p.11, lines 14-15)
for a time sufficient to cover it with the copper-dopant metal alloy (for a period of time sufficient to carry out conformal and complete filling with the alloy of Cu-Mn or Cu-Zn, p.9, lines 30-33), and
b) annealing the alloy to cause it to separate (annealing the alloy deposit of Cu-Mn or Cu-Zn forming two layers, p.12, lines 20-23) and
form a first layer of copper and a second layer comprising the dopant metal and/or an oxide thereof (form the first layer comprising essentially Cu, and the second layer comprising essentially Mn or Zn),
wherein the dopant metal is selected from the group consisting of manganese and zinc (the second metal is selected from Mn or Zn, p.5, lines 4-6),
wherein the metal layer comprises a second surface which is in contact with a mixed surface comprising both an insulating area (the first conductive surface of the metallic seed layer having a second surface in contact with a dielectric material comprising silicon oxide, p.10, lines 5-7) and a conducting area (the metallic seed layer covering an insulating material and forming conductive metal interconnects and vias connecting different levels of integration, p.7, lines 2-4, p.13, lines 30-32),
said insulating area being made of a dielectric material (the dielectric material comprising silicon dioxide, p.10, lines 5-7) and
said conducting area being made of a contact metal selected from the group consisting of tungsten, molybdenum, cobalt and ruthenium (the metal comprising tungsten, cobalt, and ruthenium, p.10 lines 10-13),
said contact metal being intended to connect a copper bit line and the semiconductor device (conductive metal interconnects and vias connecting different levels of integration in semiconductor devices, p.13, lines 30-32).
Mevellec does not teach that the semiconductor device is a 3D-NAND flash memory.
Liu teaches a process (FIG. 3E, [0012]) for fabricating a 3D-NAND flash memory (3D memory device is a NAND flash memory device, [0031]), including formation of conductive interconnect structures and bit lines using electroplating/electrodeposition techniques [0059-0060].
As taught by Liu, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec to obtain and achieve the process for fabricating the 3D-NAND flash memory as claimed, because vertically stacked 3D-NAND memory devices include conductive bit lines and semiconductor interconnect structures (Liu: [0031, 0039-0040]) to which the Cu-Mn/Cu-Zn alloy electrodeposition and annealing process of Mevellec would have been applicable for conformal filling and Mn/Zn interface formation in semiconductor interconnect structures (Mevellec: p.9, lines 30-33; p12, lines 20-23).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Mevellec due to above reason.
Mevellec in view of Liu does not teach the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0.
Senna teaches a process (2.2. Alloy electrodeposition experiments) wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0 (the electrolyte for Cu-Zn alloy electrodeposition is maintained at pH 8.0 (2.1. Cathodic polarization curves).
As taught by Senna, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec in view of Liu to obtain and achieve the process the process wherein the electrolyte comprising copper (II) ions and dopant metal ions has a pH between 6.0 and 10.0 as claimed, because it has been held that where the criticality of the claimed range is not shown and the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. MPEP §2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Senna in combination with Mevellec in view of Liu due to above reason.
Mevellec in view of Liu and Senna does not teach the process wherein the contact metal is intended to connect a polysilicon channel.
Kim teaches a process for fabricating a 3D-NAND flash memory (100, FIGS. 1 and 5, [0032]), wherein a contact metal is intended to connect a polysilicon channel (a bit line 116 electrically coupled to the conductive channel 110 comprising polysilicon, [0032, 0038]).
As taught by Kim, one of ordinary skill in the art would utilize and modify the above teaching into Mevellec in view of Liu and Senna to obtain and achieve the process for fabricating the 3D-NAND flash memory wherein the contact metal is intended to connect the polysilicon channel as claimed, because 3D-NAND flash memory architectures conventionally utilize conductive interconnect and contact structures electrically connecting bit lines and polysilicon channel structures to facilitate electrical signal transmission and operation of vertically stacked memory strings [0003-0004].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kim in combination with Mevellec in view of Liu and Senna due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Applicant submits that “In contrast, Mevellec teaches away from the present invention because Mevellec describes depositing a copper alloy to fabricate interconnects with an electrolyte that has a pH of "less than 4" (see abstract and 2:13-15 of Mevellec). In fact, Mevellec explicitly recites that using an electrolyte with a pH below 4 stabilizes the metallic copper by increasing the concentration of ions in the electrolyte, limits the corrosion of copper in the copper alloy deposit, increases the deposition rate, and anneals the copper alloy with a high grain size (see 5:32-6:6 of Mevellec). Based thereon, the skilled artisan would be led to believe that an electrolyte having a pH of less than 4 is essential to deposit a desirable copper alloy and would be dissuaded from using an electrolyte with a higher pH.” in page 8.
The examiner respectfully disagrees.
Mevellec does not criticize, discredit, or otherwise discourage all high-pH Cu-Zn alloy electrodeposition systems. Although Mevellec describes advantages associated with acidic electrolytes, a reference does not teach away merely because it expresses a preference for one alternative over another or identifies advantages associated with a particular embodiment.
Moreover, Senna expressly teaches successful Cu-Zn alloy electrodeposition using pyrophosphate-based electrolytes operated at pH 8.0 while evaluating the effects of electrolyte composition, current density, ligands, additives, morphology, alloy composition, and corrosion behavior on the resulting alloy coatings. Senna further teaches that stable and homogeneous Cu-Zn alloy coatings can be achieved under such alkaline or near-neutral electrolyte conditions. Thus, Senna teaches that Cu-Zn alloy electrodeposition was known to successfully operate under electrolyte systems having a pH substantially higher than the acidic Ph range emphasized by Mevellec. Accordingly, one of ordinary skill in the art would have understood that electrolyte pH was a variable that could be adjusted depending on the selected ligand system, electrolyte chemistry, deposition objectives, morphology requirements, corrosion properties, and deposition kinetics.
Applicant submits that “Furthermore, the deposited copper alloy coating of Senna is at least 100 times thicker than the opening dimensions of Mevellec, demonstrating the incompatibility of the electrolytes. Applicant respectfully submits that there is no teaching or suggestion that the electrolyte described in Senna can be used to deposit a thin copper alloy in an electronic substrate with sub-100 nm features and the skilled artisan would be taught away from combining features of the electrolyte in Senna with the electrolyte in Mevellec.” in page 9.
The examiner respectfully disagrees.
Applicant has not provided objective evidence establishing that the electrolyte chemistry of Senna would be inoperable, unsuitable, or incompatible for adaptation to smaller semiconductor interconnect geometries.
Furthermore, FIG. 9 of Senna illustrates SEM coating morphologies using scale bars of approximately 2 µm and 4 µm, thereby demonstrating controllable Cu-Zn alloy deposition behavior at micrometer-scale dimensions. Applicant has not provided objective evidence establishing that such Cu-Zn alloy electrodeposition chemistry would be inoperable or unsuitable for adaptation to smaller semiconductor interconnect geometries. Differences in feature size, coating thickness, substrate material, current density, electrolyte composition, and deposition conditions generally involve optimization of result-effective variables that would have been within the level of ordinary skill in the electroplating and semiconductor fabrication arts. Senna further demonstrates that Cu-Zn alloy electrodeposition chemistries were known to successfully operate at alkaline or near-neutral pH conditions. Accordingly, the resulting combination would merely involve the predictable use of prior art elements according to their established functions.
Applicant further submits that “Firstly, similar to Senna, Joi describes using an electrolyte with a pH of 6.5, which is directly against the teachings of Mevellec (see D3145 of Joi). Secondly, the skilled artisan would be led to believe that Joi cannot be used in semiconductor devices because Joi acknowledges significant shortcomings in its electrolyte. That is, Joi only deposits a copper-manganese alloy on a silicon wafer without any recessed features (such as copper conductor lines or interconnect features). The copper-manganese alloy of Joi cannot "enable 'bottom-up' growth in recessed geometries" and the roughness of the film "must be reduced" (see D3147 of Joi). Based thereon, there is no teaching or suggestion that the copper-manganese alloy can be deposited at a high pH in small semiconductor features as described and claimed by Applicant.” in pages 9-10.
The examiner respectfully disagrees.
Joi is expressly directed to Cu-Mn alloy electrodeposition “for application in interconnect metallization” and discusses semiconductor interconnect scaling, seedless metallization schemes, barrier layers, electromigration resistance, and bottom-up Cu filling in semiconductor interconnect structures. Joi further teaches successful Cu-Mn alloy electrodeposition on Cu-seeded silicon wafers using an electrolyte maintained at Ph 6.5 SEM characterization in Figure 3 further illustrates smooth and adherent Cu-Mn deposits at submicron dimensions, including SEM scale bars of approximately 500 nm and 1 µm. Accordingly, Joi teaches that near-neutral Cu-alloy electrodeposition chemistries were known to be adaptable to semiconductor metallization environments.
Furthermore, Applicant’s arguments relating to recessed geometries and bottom-up filling are not commensurate in scope with the presently claimed invention, as the claims do not recite any particular recessed trench geometry, void-free filling limitation, aspect ratio limitation, or bottom-up growth requirement. Differences relating to morphology optimization, roughness reduction, recessed feature filling behavior, current pulsing conditions, and deposition geometry generally involve optimization of result-effective variables that would have been within the level of ordinary skill in the electroplating and semiconductor fabrication arts. Accordingly, the resulting combination would merely involve the predictable use of prior art elements according to their established functions.
Hence, the claim rejections to claims 1-2, 4-11, and 14-17 are maintained.
Conclusion
Applicant's amendment necessitated the new ground of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/3/26
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