DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the preliminary amendment received on 4/6/2023. Claims 1-7 are pending in this application.
Drawings
2. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “1” (Fig. 2) has been used to designate two separated layers. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
3. The claims are objected because of the following reasons:
Re claim 2, page 19, line 10: delete “wafer” and insert –substrate-- which is prior claimed.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claim 1, lines 11-12, cite “performing a metal evaporation and removing a photoresist to form a double T-shaped gate structure into two passivation layers” is not clear, because the claim does not clearly specify when and where a photoresist is formed & how it is used in any prior process steps. Claim 1, last par., further cites “the double T-shaped gate comprises a gate root, a lower gate cap, and a top gate cap from bottom to top” is not clear, because claim 1 is directed to process claim, and the claim does not clearly specify when and how each gate root, lower gate cap, and top gate cap is formed corresponding to each exposure region. For examination purpose, the photoresist will be considered in at least one performing step(s), and at least one step(s) considered to form each gate root & gate caps.
Claim 2 cites “S2: coating the photoresist on the top passivation layer…; S3:…then removing the photoresist; S4: spin-coating the photoresist on the top passivation layer again…S5:…then removing the photoresist; S6: spin-coating the photoresist…S7:...then removing the photoresist” are not clear. First, claim 1 requires one (1) time to remove a photoresist, claim 2 requires three (3) times in steps S3, S5 & S7 to remove the photoresist, it is not clear which photoresist is removed when reading into claim 1. Second, in S3, the photoresist is removed, it is not clear how the same photoresist formed again in separated steps S4 & S6, they appear to be three different photoresists instead because they formed at three different steps S2, S4 & S6 one after the other. Claim 2, S5 further cites “perming an accurate wet etching” is not clear because of “accurate”. The claim & disclosure do not provide clearly specify/define how accurate the wet etch is or any particular informational explanation to determine “an accurate wet etching”.
Claims 3-7 are rejected as being dependent on claims 1 & 2.
Applicant is suggested to revise and clarify the claims to avoid any further confusions.
For best understanding and examination purpose, the claims will be best considered based on drawings, disclosure, and/or any applicable prior arts.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gu et al. (CN 110707150, English translation attached).
Re claim 1, Gu teaches, under BRI, Figs. 1-11, abstract & pages 1-6, a preparation method of a double-T-shaped gate (112) based on double-layer passivation accurate etching, comprising:
-sequentially growing two passivation layers (102, 103) on an epitaxial structure (101), wherein the two passivation layers (102, 103) comprise a bottom passivation layer (102) and a top passivation layer (103) (Fig. 2);
-performing a first exposure on the top passivation layer (103) and etching the top passivation layer and the bottom passivation layer (102, 103) in a first exposure region from top to bottom to form a gate root region (106) (Figs. 4-5);
-performing a second exposure on the top passivation layer (103) and etching the top passivation layer (103) in a second exposure region to form a lower gate cap region (107) (Fig. 6); and
-performing a third exposure on the top passivation layer (103) to form a top gate cap exposure region (110) and performing a metal evaporation and removing a photoresist (108, 109) to form a double-T-shaped gate structure in the two passivation layers (102, 103) (Figs. 7-11);
wherein the double-T-shaped gate (112) comprises a gate root (bottom part), a lower gate cap (middle part), and a top gate cap (upper part) from bottom to top; a bottom of the gate root is in contact with the epitaxial structure (101), and a sidewall of the gate root is in contact with the bottom passivation layer (102); a bottom of the lower gate cap is in contact with an upper surface of the bottom passivation layer (102), and a sidewall of the lower gate cap is in contact with the top passivation layer (103); a bottom of the top gate cap is in contact with an upper surface of the top passivation layer (103), and a sidewall of the top gate cap is in contact with air.
Note: in contact # physical contact.
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Re claim 3, Gu teaches, Fig. 11, a width of the top cap (upper part of 112) is greater than a width of the lower gate cap (middle part), and the width of the lower gate cap is greater than a width of the gate root (bottom part) .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 2 and 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of Liu et al. (US 2021/0057614).
The teachings of Gu have been discussed above.
Re claim 2, Gu teaches, under BRI & best understand, Figs. 1-11, abstract & pages 1-6, S1: growing the epitaxial structure on an epitaxial substrate (e.g., the substrate is epitaxial material of the epitaxial wafer) and growing the two passivation layers (102, 103) on the epitaxial structure (101) (Fig. 2);
S2: coating the photoresist (resist 104) on the top passivation layer (103) and performing the first exposure to expose the gate root region (106) after development (Fig. 4-5);
S3: performing dry etching (e.g., RIE dry etching) on the gate root region (106), wherein an etching depth of the dry etching is a thickness of the two passivation layers (102, 103), and then removing the photoresist (Fig. 7);
S4: spin-coating the photoresist (resist 108) on the top passivation layer (103) again and performing the second exposure on the top passivation layer to expose the lower gate cap region (107) after development;
S5: performing an accurate wet etching on the lower gate cap region (107), wherein an etching depth of the accurate wet etching (e.g., wet etching process) is a thickness of the top passivation layer;
S6: spin-coating the photoresist (109) on the top passivation layer again and performing the third exposure on the top passivation layer (103) to expose the top gate cap region (110) (Fig. 9);
S7: performing the metal evaporation on the epitaxial wafer and then removing the photoresist (108, 109) to complete preparation of the double-T-shaped gate structure (Figs. 10-11).
Gu does not explicitly teach removing the photoresist in S5; S6: spin-coating the photoresist; S7: removing the photoresist; and S8: selecting an annealing atmosphere and an annealing temperature according to an electrode contact property to complete preparation of the double-T-shaped gate.
Liu teaches, Figs. 10-17, [0116, 0119, 0120], the use of three (3) photoresists (10, 12, 14) formed by spin-coating and removing the photoresists (10, 12, 14) & thermal anneal carried out after removing third photoresist (14).
As taught by Liu, one of ordinary skill in the art would utilize & modify the above teaching into Gu to obtain spin-coating the photoresist again and selecting an annealing atmosphere and an annealing temperature according to an electrode contact property to complete preparation of the double-T-shaped gate as claimed, because these processes are known and widely used in the art to perform etching and complete a device structure. Further, it has been held to be within the general skill of a worker in the art to select a known material (e.g., photoresist) on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Liu in combination with Gu due to above reason.
Re claim 5, in combination cited above, Liu teaches the dry etch in S3 is a plasma etching (e.g., RIE), and an etching atmosphere is a fluorinated gas (e.g., CF4) [0090].
Re claim 6, Gu teaches, Figs. 10-11, a width of the top gate cap exposure region is greater than a width of a lower gate cap exposure region, and the width of the lower gate cap exposure region is greater than a width of a gate root exposure region.
Re claim 7, Gu teaches an etching solution used in the wet etching in S4 is a buffered oxide etch (BOE) solution (page 7, last par.) (see also Liu [0092]).
7. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Gu.
The teachings of Gu have been discussed above.
Re claim 4, Gu teaches the two passivation layers (102, 103) are grown using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD) (page 8, line 9).
Gu does not explicitly teach the top passivation layer is SiO2, the bottom passivation layer is SiN.
Gu does the use of SiO2 and SiN as passivation layers (Fig. 2, page 8, line 9).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ & modify the teaching as taught by Gu to obtain the top passivation layer is SiO2, the bottom passivation layer is SiN as claimed, because it aids in achieving a desired stack of passivation layers, and further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
8. Claims 1, 3 and 4 are, alternatively, rejected under 35 U.S.C. 103 as being unpatentable over Corrion et al. (US 9,202,880) in view of Kong (CN 107331608, English translation attached).
The teachings of Gu have been discussed above.
Re claim 1, Corrion teaches, under BRI, Figs. 1A-B & 2, cols. 4-6, a preparation method of a double-T-shaped gate (32, 34, 36) based on double-layer passivation accurate etching, comprising:
-sequentially growing two passivation layers (26, 28, 30) on an epitaxial structure (16), wherein the two passivation layers comprise a bottom passivation layer (26) and a top passivation layer (28, 30);
-performing a first exposure on the top passivation layer (28, 30) and etching the top passivation layer and the bottom passivation layer (26) in a first exposure region from top to bottom to form a gate root region (gate foot) (step 18);
-performing a second exposure on the top passivation layer (28, 30) and etching the top passivation layer in a second exposure region to form a lower gate cap region (step 16); and
-performing a third exposure on the top passivation layer (28, 30) to form a top gate cap exposure region (steps 18-19) and performing a metal evaporation (step 12) and removing a mask (*) (76) to form a double-T-shaped gate structure (32, 34, 36) in the two passivation layers (26, 28, 30) (step 21);
wherein the double-T-shaped gate (32, 34, 36) comprises a gate root, a lower gate cap, and a top gate cap from bottom to top; a bottom of the gate root is in contact with the epitaxial structure (16), and a sidewall of the gate root is in contact with the bottom passivation layer (26); a bottom of the lower gate cap is in contact with an upper surface of the bottom passivation layer (26), and a sidewall of the lower gate cap is in contact with the top passivation layer (28, 30); a bottom of the top gate cap is in contact with an upper surface of the top passivation layer (28, 30), and a sidewall of the top gate cap is in contact with air (Fig. 1A).
Note: 2nd-3rd steps are considered as interchange steps.
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Corrion does not explicitly teach, in step 4, performing a metal evaporation and removing a photoresist (*).
Kong teaches, under BRI, Figs. 5-6, abstract, performing a metal evaporation and removing a photoresist.
As taught by Kong, one of ordinary skill in the art would utilize & modify the above teaching to obtain steps of performing a metal evaporation and removing a photoresist as claimed, because it aids in achieving gate structure with smaller gate resistance and better performance. Further, it has been held to be within the general skill of a worker in the art to select a known material (e.g., photoresist) on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kong in combination with Corrion due to above reason.
Re claim 3, Corrion teaches, Fig. 1A, a width of the top cap is greater than a width of the lower gate cap, and the width of the lower gate cap is greater than a width of the gate root (see also Kong’s Fig. 6).
Re claim 4, Corrion teaches, col. 4, 6th par., col. 5, 2nd par. & claim 4, the top passivation layer is SiO2, the bottom passivation layer is SiN, and the two passivation layers are grown using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or atomic layer deposition (ALD).
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/27/26