Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Currently, claims 1-20 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mun et al. (Pub. No. US 2019/0259829 A1, herein Mun) in view of Choi (U.S. Pat. No. 6,025,237).
Regarding claim 1, Mun discloses a semiconductor device comprising: a chip having a main surface; a drain region 250 formed at a surface layer portion of the main surface (Mun: Figs. 2b-3 and paragraphs [0030], [0038]-[0039]); a source region 252 formed at the surface layer portion of the main surface at a distance from the drain region (Mun: Figs. 2b-3 and paragraphs [0030], [0034]-[0037]); a channel inversion region formed on a side of the source region between the drain region and the source region in the surface layer portion of the main surface; a drift region 230 formed in a region between the drain region and the channel inversion region in the surface layer portion of the main surface; a gate insulating film 242 having a first portion that covers the channel inversion region on the main surface and a second portion that covers the drift region on the main surface; and a gate electrode 244 having a first electrode portion covering the first portion and a second electrode portion led out from the first electrode portion onto the second portion so as to partially expose the second portion (Mun: Figs. 2b-3 and paragraph [0028]).
Mun does not specifically show wherein the first electrode overlaps a part of the source region.
However, in the same field of endeavor, Choi teaches a semiconductor device, wherein the first electrode 26 overlaps a part of the source region 16 (Choi: Fig. 13 and column 2 lines 3-16) to smooth electric field, improve breakdown voltage, reduce oxide stress and enhance switching performance.
Therefore, given the teachings of Choi, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Mun in view of Choi by employing the first electrode overlapping a part of the source region.
Regarding claim 2, Mun in view of Choi teaches the semiconductor device according to claim 1, wherein the second electrode portion has a side that extends in a facing direction of the drain region and the source region and that partially exposes the second portion (Mun: Figs. 2b-3 and paragraph [0028]).
Regarding claim 3, Mun in view of Choi teaches the semiconductor device according to claim 1, wherein the first electrode portion covers a whole area of the first portion in a plan view (Mun: Figs. 2b-3 and paragraph [0028]).
Regarding claim 4, Mun in view of Choi teaches the semiconductor device according to claim 1, wherein the second electrode portion exposes the second portion at a distance from the first portion in a plan view (Mun: Figs. 2b-3 and paragraph [0028]).
Regarding claim 5, Mun in view of Choi teaches the semiconductor device according to claim 1, wherein the second electrode portion exposes only the second portion with respect to the gate insulating film (Mun: Figs. 2b-3 and paragraph [0028]).
Regarding claim 6, Mun in view of Choi teaches the semiconductor device according to claim 1, wherein the first portion covers a whole area of the channel inversion region in a plan view, and the second portion partially covers the drift region so as to partially expose the drift region in a plan view (Mun: Figs. 2b-3 and paragraphs [0028], [0039]).
Regarding claim 7, Mun in view of Choi teaches the semiconductor device according to claim 1, wherein the second electrode portion exposes a plurality of parts of the second portion (Mun: Figs. 2b-3 and paragraphs [0028], [0039]).
Regarding claim 8, Mun in view of Choi teaches the semiconductor device according to claim 1, wherein the second electrode portion exposes the parts of the second portion at a distance from each other in a line in a plan view (Mun: Figs. 2b-3 and paragraphs [0028], [0039]).
Regarding claim 9, Mun in view of Choi teaches the semiconductor device according to claim 1, further comprising: a field insulating film 246 that covers the drift region on the main surface and that has a thickness differing from a thickness of the gate insulating film (Mun: Figs. 2b-3 and paragraph [0027]).
Regarding claim 10, Mun in view of Choi teaches the semiconductor device according to claim 9, wherein the field insulating film 246 is continuous with the second portion, and the second electrode portion is led out from on the second portion onto the field insulating film, and faces the drift region across the field insulating film (Mun: Figs. 2b-3 and paragraphs [0027]-[0028], [0039]).
Regarding claim 11, Mun in view of Choi teaches the semiconductor device according to claim 10, wherein the second electrode portion partially exposes the field insulating film (Mun: Figs. 2b-3 and paragraphs [0027]-[0028], [0039]).
Regarding claim 12, Mun in view of Choi teaches the semiconductor device according to claim 11, wherein the second electrode portion has a side that extends in a facing direction of the drain region and the source region and that partially exposes the field insulating film (Mun: Figs. 2b-3 and paragraphs [0027]-[0028], [0039]).
Regarding claim 13, Mun in view of Choi teaches the semiconductor device according to claim 11, wherein the second electrode portion exposes a plurality of parts of the field insulating film (Mun: Figs. 2b-3 and paragraphs [0027]-[0028], [0039]).
Regarding claim 14, Mun in view of Choi teaches the semiconductor device according to claim 11, wherein the second electrode portion exposes the parts of the field insulating film in a line in a plan view (Mun: Figs. 2b-3 and paragraphs [0027]-[0028], [0039]).
Regarding claim 15, Mun in view of Choi teaches the semiconductor device according to claim 11, further comprising: a semiconductor region of a first conductivity type formed at a surface layer portion of the main surface; and a drain-well region 238/260/231 of a second conductivity type formed at a surface layer portion of the semiconductor region; wherein the drain region is of the second conductivity type and is formed at a surface layer portion of the drain-well region (Mun: Figs. 2b-3 and paragraphs [0034]-[0039]), the source region 234/236 is of the second conductivity type and is formed at the surface layer portion of the semiconductor region at a distance from the drain-well region, the channel inversion region is formed in a region between the drain-well region and the source region, and the drift region is formed in the drain-well region (Mun: Figs. 2b-3 and paragraphs [0026], [0041]-[0042]).
Regarding claim 16, Mun in view of Choi teaches the semiconductor device according to claim 15, further comprising: source-well region 233 of the first conductivity type formed at the surface layer portion of the semiconductor region at a distance from the drain-well region; wherein the source region is formed at a surface layer portion of the source-well region (Mun: Figs. 2b-3 and paragraphs [0034]-[0039]).
Regarding claim 17, Mun in view of Choi teaches the semiconductor device according to claim 16, further comprising: contact region 254 of the first conductivity type formed at the surface layer portion of the source-well region (Mun: Figs. 2b-3 and paragraph [0037]).
Regarding claim 18, Mun in view of Choi teaches the semiconductor device according to claim 1, further comprising: semiconductor region of a first conductivity type formed at the surface layer portion of the main surface; and source-well region 233 of a second conductivity type formed at the surface layer portion of the semiconductor region; wherein the drain region is of the first conductivity type and is formed at the surface layer portion of the semiconductor region at a distance from the source-well region, the source region 234/236 is of the first conductivity type and is formed at the surface layer portion of the source-well region(Mun: Figs. 2b-3 and paragraphs [0034]-[0039]), the channel inversion region is formed between the semiconductor region and the source region in the surface layer portion of the source-well region, and the drift region is formed in a region between the source-well region and the drain region (Mun: Figs. 2b-3 and paragraphs [0026], [0041]-[0042]).
Regarding claim 19, Mun in view of Choi teaches the semiconductor device according to claim 18, further comprising: a drain-well region of the first conductivity type formed at the surface layer portion of the semiconductor region at a distance from the source-well region; wherein the drain region is formed at the surface layer portion of the drain-well region (Mun: Figs. 2b-3 and paragraphs [0034]-[0039]).
Regarding claim 20, Mun in view of Choi teaches the semiconductor device according to claim 18, further comprising: a contact region 254 of the second conductivity type formed at the surface layer portion of the source-well region (Mun: Figs. 2b-3 and paragraph [0037]).
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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January 10, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813