DETAILED ACTION
This Office Action is in response to RCE filed June 1, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 9 is objected to because of the following informalities: “detecto” should be replaced with “detector” on line 20. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9, 12-14, 16-18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 9, it is not clear what “a third transistor electrode” recited on lines 2425 refers to, because (a) Applicants do not claim a first transistor electrode and a second transistor electrode before claiming “a third transistor electrode” in claim 9, (b) in addition, Applicants claim “a first diode electrode and a second diode electrode” on lines 21-22 and (c) therefore, it is not clear whether Applicants omitted the first and second transistor electrode, or “a third transistor electrode” is related to “a first diode electrode and a second diode electrode” since (a) Applicants do not specifically claim what the transistor is constituted of, what type of a transistor the claimed transistor is, or how the transistor is structured, and (b) two diodes can be coupled together to form a transistor.
(2) Further regarding claim 9, it is not clear what the limitation “an exposed surface of the buffer layer, the active layer, the first electrode layer and the absorption layer” recited on lines 25-26 suggests, because (a) it is not clear whether the limitation suggests (i) an exposed surface of the buffer layer, an exposed surface of the active layer, an exposed surface of the first electrode layer and an exposed surface of the absorption layer, or (ii) an exposed surface of the buffer layer, and the active layer, the first electrode layer and the absorption layer, and (b) depending on which interpretation should be used, the claimed ray detector may have different configurations or arrangements of the claimed component layers.
Claims 12-14, 16-18 and 20 depend on claim 9, and therefore, claims 12-14, 16-18 and 20 are also indefinite.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 12-14, 16-18 and 20, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Katoh et al. (WO 2006/129427)
Regarding claim 9, Katoh et al. disclose a ray detector (Figs. 1-3 and Title), comprising: a substrate (20) ([0029], see bottommost part of page 5 of Translation), wherein a first surface (top surface) of the substrate comprises a first region (region of Fig. 2) and a second region (region of Fig. 3); and an active layer (25; silicon film) ([0030]-[0031]) of a thin film transistor (Fig. 2) in the first region, which would be on a portion of the buffer layer in the first region when there is a buffer layer disposed on the first surface of the substrate as discussed below, an absorption layer (layer between glass substrate 20 and first interlayer insulating film 12 in Fig. 3) of a photodiode (Fig. 3) on a surface, which is distal to the substrate when there is the buffer layer disposed on the first surface of the substrate as discussed below, in the second region, which is of a portion of the buffer layer in the second region when there is the buffer layer disposed on the first surface of the substrate as discussed below; wherein the active layer (25 in Fig. 2) of the thin film transistor and the absorption layer (layer between glass substrate 20 and first interlayer insulating film 12 in Fig. 3) of the photodiode are in a same layer; wherein the absorption layer of the photodiode comprises a first doped region (n+ regions in Fig. 3) and a second doped region (p+ regions in Fig. 3), because (a) a “region” does not necessarily suggest a continuous or contiguous region, and (b) therefore, the plurality of n+ regions or p+ regions can be referred to as the first and second doped region, respectively, the first doped region comprises at least one convex portion (portion indicated by one of two arrows at bottom, see illustration below) and at least one concave portion (portion indicated by one of two arrows adjacent 15a or 15b, see illustration below) arranged parallel to a plane where the substrate is located, see Fig. 3(b), because (a) as discussed previously under 35 USC 112(b) rejections in the Non Final Office Action mailed September 22, 2025, the limitations “concave” and “convex” portion may not be well-defined, (b) also, a portion, which Merriam-Webster dictionary defines as “an often limited part of a whole”, which does not necessarily suggest that a portion forms a boundary or an outermost edge, and (c) therefore, the portions of the n+ doped regions that look similar to Applicants’ concave and convex portion can be referred to as the claimed “at least one convex portion” and “at least one concave portion” since a “portion” does not necessarily suggest that the “portion” is surrounded and in contact with distinct layers or materials,
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the second doped region comprises at least one convex portion (portion indicated by one of three arrows at top, see illustration below) and at least one concave portion (portion indicated by one of three arrows adjacent 14a-14c, see illustration below) arranged parallel to the plane where the substrate is located, see Fig. 3(b), because (a) as discussed under 35 USC 112(b) rejections in the Non Final Office Action mailed September 22, 2025, the limitations “concave” and “convex” portion may not be well-defined, (b) also, a portion, which Merriam-Webster dictionary defines as “an often limited part of a whole”, which does not necessarily suggest that a portion forms a boundary or an outermost edge, and (c) therefore, the portions of the p+ doped regions that look similar to Applicants’ concave and convex portion can be referred to as the claimed “at least one convex portion” and “at least one concave portion” since a “portion” does not necessarily suggest that the “portion” is surrounded and in contact with distinct layers or materials,
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each convex portion of the first doped region is located in a corresponding concave portion of the second doped region when the device structure shown in Fig. 3 is viewed from the side because Applicants do not specifically claim the perspective with which the claim limitation is met, and each convex portion of the second doped region is embedded in a corresponding concave portion of the first doped region when the device structure shown in Fig. 3 is viewed from the side because Applicants do not specifically claim the perspective with which the claim limitation is met; wherein the ray detector further comprises a first electrode layer (two or more of 14a-14c, 15a and 15b, or 16a-16c, 17a and 17b in Fig. 3) on a surface of the absorption layer distal to the substrate, wherein the first electrode layer comprises a first diode electrode (one of 14a-14c, 15a and 15b, or 16a-16c, 17a and 17b) and a second diode electrode (another of 14a-14c, 15a and 15b, or 16a-16c, 17a and 17b) of the photodiode, the first diode electrode is stacked on the first doped region, because the preposition “on” does not necessarily suggest “directly on”, and the second diode electrode is stacked on the second doped region, because the preposition “on” does not necessarily suggest “directly on”; and wherein the ray detector further comprises an insulating layer (31 in Fig. 2, which corresponds to 12 in Fig. 3) and a third transistor electrode (26 in Fig. 2), wherein the insulating layer covers an exposed surface of the active layer (25; silicon film), the first electrode layer (two or more of 14a-14c, 15a and 15b, or 16a-16c, 17a and 17b) and the absorption layer (layer between glass substrate 20 and first interlayer insulating film 12 in Fig. 3), because this limitation is indefinite as discussed above under 35 USC 112(b) rejections; and the third transistor electrode is on a surface, which is distal to the substrate, of a portion of the insulating layer (31/12) in the first region (region of Fig. 2).
Katoh et al. differ from the claimed invention by not comprising a buffer layer on the first surface of the substrate, and the insulating layer covers an exposed surface of the buffer layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the ray detector disclosed by Katoh et al. can comprise a buffer layer on the first surface of the substrate, because (a) a buffer layer has been commonly employed in forming a thin film transistor on a glass substrate, which is disclosed by Katoh et al., to reduce diffusion of unwanted impurities from the glass substrate into a semiconductor channel layer of the thin film transistor, which would deteriorate the quality of the active layer and the performance of the thin film transistor, and (b) it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use, In re Leshin, 125 USPQ 416. In this case, the insulating layer (31/12) would cover an exposed surface of the not-shown buffer layer.
Regarding claim 12, Katoh et al. further disclose that the first doped region ((one of) n+ regions) and the second doped region ((one of p+) regions) are doped with different dopants, respectively.
Regarding claim 13, Katoh et al. differ from the claimed invention by not showing that the active layer comprises a nanowire; and on a side of the active layer distal to the substrate there are a transition layer and a first electrode layer stacked sequentially, the transition layer comprises a first transition electrode and a second transition electrode, the first electrode layer comprises a first transistor electrode and a second transistor electrode, the first transition electrode is sandwiched between the first transistor electrode and a source region of the nanowire, and the second transition electrode is sandwiched between the second transistor electrode and a drain region of the nanowire.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the active layer can comprise a nanowire, because (a) Applicants do not specifically claim what “a nanowire” is formed of, and what the length, width and height of the nanowire are, and (b) a nanowire has been commonly formed as a channel layer or active layer material of a thin film transistor since the nanowire would confine charge carriers more effectively, which would improve performance of the thin film transistor and also would improve yield of thin film transistors. In this case, on a side of the active layer (25 in Fig. 2) distal to the substrate (20) there are a transition layer (composite layer of 27 and 28) and a first electrode layer (composite layer of 29 and 30) stacked sequentially, the transition layer comprises a first transition electrode (27 or 28) and a second transition electrode (28 or 27), the first electrode layer comprises a first transistor electrode (29 or 30) and a second transistor electrode (30 or 29), the first transition electrode is sandwiched between the first transistor electrode and a source region (22 or 24) of the nanowire, and the second transition electrode is sandwiched between the second transistor electrode and a drain region (24 or 22) of the nanowire.
Regarding claims 14, Katoh et al. further comprise a sacrificial layer (not-shown interface layer of 25 and 27/28) between the transition layer (composite layer of 27 and 28) and the active layer (25), because (a) Applicants do not specifically claim what the “sacrificial layer” refers to, what it does, and what it is formed of, (b) Applicants’ sacrificial layer 41 in Fig. 27 of current application remains in the final product of the claimed ray detector, and therefore, the term “sacrificial layer” does not necessarily suggest that the “sacrificial layer” is removed during a manufacturing process and thus is not present in the claimed ray detector, and (c) therefore, the inherently formed but not-shown interface layer of 25 and 27/28 can be referred to as “a sacrificial layer” since (i) the not-shown interface layer is inherently formed to firmly bond the active layer 25 and the element 27/28, and without the interface layer there would be no bonding between the active layer 25 and the element 27/28, and (ii) the not-shown interface layer is formed by intermixing of elements constituting the active layer 25 and the element 27/28, which may be referred to as being “sacrificial” since portions of the active layer 25 and the element 27/28 are altered during the manufacturing process.
Regarding claims 16-18 and 20, Katoh et al. further comprise for the ray detector according to claim 9 a dielectric layer (32 in Fig,. 2, which corresponds to 13 in Fig. 3) covering an exposed surface of the insulating layer (31/12) and the third transistor electrode (26) (claim 16), further comprising leads (27, 28, 14a-14c, 15a and 15b), which penetrate through the dielectric layer (32/13) and the insulating layer along a thickness direction of the dielectric layer and the insulating layer (31/12), and are respectively electrically connected to the first diode electrode (one of 16a-16c, 17a and 17b) and the second diode electrode (another of 16a-16c, 17a and 17b) (claim 17), wherein the substrate (20; glass substrate) comprises one of a glass-based substrate and a silicon-based substrate (claim 18), and further comprising an anode layer (one of 16a-16c, 17a and 17b), wherein the anode layer comprises a first lead electrode (one of 14a-14c, 15a and 15b) and a second lead electrode (another of 14a-14c, 15a and 15b), and the leads are electrically connected to the first lead electrode and the second lead electrode, respectively (claim 20).
Response to Arguments
Applicants’ arguments with respect to claim 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huang et al. (US 10,784,305)
Huang et al. (CN 113571536)
Huang et al. (CN 113764439)
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 August 18, 2026
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