DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Majhi (US 2020/0312839) in view of Kim (US 2018/0197736).
Regarding claim 1, Majhi discloses a monolithic three-dimensional (3D) integrated circuit comprising: a semiconductor substrate (Fig.1, numeral 101); a first semiconductor device (181) formed on the semiconductor substrate (101); a dielectric layer (126) configured to cover the semiconductor substrate (101) and the first semiconductor device (181); a wiring structure (125) formed in the dielectric layer (126), (128); and a second semiconductor device ([0029]) formed on the dielectric layer (126). (128) and including a seed layer (160) and a crystallized semiconductor layer (144) ([0034]) on the seed layer (160), wherein the crystallized semiconductor layer is formed by heat treatment of a preliminary semiconductor layer on the seed layer at a temperature of 450°C or less (note: “wherein the crystallized semiconductor layer is formed by heat treatment of a preliminary semiconductor layer on the seed layer at a temperature of 450°C or less” is a product-by-process limitation. And according to MPEP 2113, I, “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). In the present case, because Majhi discloses a crystallized semiconductor layer (144), this limitation is considered to be met).
Majhi does not disclose a seed layer including a two-dimensional (2D) semiconductor material.
Kim however discloses a seed layer (120) including a two-dimensional (2D) semiconductor material ([0047]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Majhi with WO’577 to have a seed layer including a two-dimensional (2D) semiconductor material for the purpose of improving lattice constant mismatch growth (Kim, [0047]).
Regarding claim 2, Kim discloses wherein the 2D semiconductor material includes at least one a carbon-containing material ([0047]).
Regarding claim 3, Majhi discloses wherein the crystallized semiconductor layer (144) includes a semiconductor material having higher charge mobility than that of a semiconductor material constituting the semiconductor substrate (101) ([0023]; [0333]).
Regarding claim 4, Majhi discloses wherein the crystallized semiconductor layer 9144) includes at least one of germanium, a compound semiconductor material containing the germanium, and a chalcogen material ([0033]).
Regarding claim 5, Majhi discloses wherein the semiconductor substrate includes silicon ([0023]).
Claim(s) 6-13 are rejected under 35 U.S.C. 103 as being unpatentable over Majhi in view of Kim and Evans (US 2006/0134892).
Regarding claim 6, Majhi discloses a method of manufacturing a monolithic 3D integrated circuit, the method comprising: forming a first semiconductor device on a semiconductor substrate (Fig.1, numeral 101); forming a dielectric layer (126), (128) covering the semiconductor substrate (101) and the first semiconductor device and a wiring structure (125) in the dielectric layer (126), (128); forming a seed structure (160) on the dielectric layer (126), (128); and forming a crystallized semiconductor layer (144) on the seed structure (160).
Majhi does not disclose (1) a seed layer including a two-dimensional (2D) semiconductor material; (2) wherein the crystallized semiconductor layer is formed by heat treatment of a preliminary semiconductor layer on the seed layer at a temperature of 450°C or less.
Regarding element (1), Kim however discloses a seed layer (120) including a two-dimensional (2D) semiconductor material ([0047]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Majhi with Kim to have a seed layer including a two-dimensional (2D) semiconductor material for the purpose for the purpose of improving lattice constant mismatch growth (WO’577, [0047]).
Regarding element (2), Majhi however discloses wherein the crystallized semiconductor layer (InGaAS) is formed by heat treatment of a preliminary semiconductor layer on the seed layer at a temperature below 500°C ([0034])). And Evans discloses that heat treatment at a temperature of 450°C or less increases resistivity of INGaAS ([0104]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Majhi with Evans to adjust the temperature of a heat treatment of a preliminary semiconductor layer to be in the claimed range for the purpose of optimization the properties of the crystallized semiconductor layer (Evans, [0103]-[0106]).
Regarding claim 7, Kim discloses wherein the forming of the seed structure comprises: transferring the seed structure formed on the growth substrate onto the dielectric layer or directly forming the seed structure on the dielectric layer ([0053]; [0054]).
Regarding claim 8, Majhi discloses wherein the seed structure (160) includes a plurality of island- like structures (Fig.1).
Majhi does not disclose that the seed layer is 2D semiconductor material.
WO’577 discloses wherein the seed structure includes the 2D semiconductor material ([0049]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Majhi with Kim to have the seed layer as 2D semiconductor material for the purpose of improving of improving lattice constant mismatch growth (Kim, [0047]).
Regarding claim 9, Kim discloses wherein the 2D semiconductor material includes at least one of a carbon-containing material ([0047]).
Regarding claim 10, Majhi discloses, wherein the crystallized semiconductor layer includes a semiconductor material having higher charge mobility than that of a semiconductor material constituting the semiconductor substrate 101) ([0023]; [0333]).
Regarding claim 11, Majhi discloses wherein the crystallized semiconductor layer includes at least one of germanium, a compound semiconductor material containing the germanium, and a chalcogen material ([0033]).
Regarding claim 12, Majhi does not explicitly disclose wherein the forming of the crystallized semiconductor layer is performed through heat treatment at a temperature of 450 °C or less.
Majhi however discloses that forming of the crystallized semiconductor layer is performed through heat treatment at a temperature below 500 C. Majhi further discloses that heat treatment temperature should be sufficient for transition from amorphous to crystalline state ([0022]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to adjust the temperature of forming crystallized semiconductor material to be in the claimed range for the purpose of optimizing the crystallization process.
Regarding claim 13, Majhi discloses wherein the semiconductor substrate includes silicon ([0023]).
Response to Arguments
Applicant's arguments filed 12/12/2025 have been fully considered but they are not persuasive.
Applicant’s arguments that Majhi in view of Kim does not disclose the limitaiton of amended claim 1 such as “wherein the crystallized semiconductor layer is formed by heat treatment of a preliminary semiconductor layer on the seed layer at a temperature of 450°C or less” are not persuasive because this limitation is a product-by-process limitation. And according to MPEP 2113, I, “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). In the present case, because Majhi discloses a crystallized semiconductor layer (144), this limitation is considered to be met.
Applicant’s arguments with respect to claim(s) 6-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891