The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8,15-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (2021/0020704).Regarding claims 1 and 19, Kim teaches in figures 2-8 and related text a display apparatus comprising a display substrate, comprising a first display area (DA3 and partial area of DA1) and a second display area DA1 (see figure 3), wherein the second display area is at least partially surrounded by the first display area,
the first display area (DA3 and partial area of DA1) is configured to perform image display and comprises a plurality of first light emitting devices, a plurality of first circuit units and at least one second circuit unit (see also figure 2),
the second display area DA1 is configured to perform image display and transmitting light and comprises a plurality of second light emitting devices (see also figure 2);
a first circuit unit comprises a first pixel drive circuit PX (see also figure 3), the first pixel drive circuit comprises at least a first anode electrode connected with a first light emitting device and a compensation capacitor plate Cst connected with the first anode electrode (see figure 5), the compensation capacitor plate is configured to form a compensation capacitance;
the second circuit unit comprises a second pixel drive circuit, the second pixel drive circuit at least comprises a second anode electrode, and the second anode electrode is connected with a second light emitting device through an anode connection line (see figure 6 which comprises a second anode electrode connected a second light emitting device).
Kim does not explicitly state that the circuits depicted in figures 2-8 are used in one device. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use the circuits depicted in figures 2-8 in one device, in Kim’s device, in order to operate the device in its intended use.
Regarding claim 2, Kim teaches in figure 7 and related text that the first anode electrode, the second anode electrode and the compensation capacitor plate are disposed in a same layer.
Regarding the claimed limitations of “synchronously formed through a same patterning process”, these are process limitations which would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
The formation of the compensation capacitor plate a by forming the compensation capacitor plate by synchronously formed through a same patterning process, this does not produce a structure which is different from a structure which is formed not by same patterning process.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding claim 3, Kim teaches in figure 6 and related text that the first anode electrode and the compensation capacitor plate are interconnected to be of an integral structure.
Regarding claim 4, Kim teaches in figure 3 and related text that the at least one second circuit unit comprises a power connection line 161 extending along a first direction and a first power supply line 160 extending along a second direction, the first power supply line is connected with the power connection line, the first direction and the second direction are intersected.
Kim does not explicitly state that the first power supply line is connected with the power connection line through a via.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to connect the first power supply line with the power connection line through a via, in Kim’s device, in order to reduce the size of the device by forming a conventional 3D structure.
Regarding claim 5, Kim teaches in figure 3 and related text that the first circuit unit comprises a power connection line 161 extending along the first direction, and at least one first circuit unit is not provided with the first power supply line.
Regarding claim 6, the combined device of Kim teaches in figure 7 and related text (see the rejection of claim 2 above) that the compensation capacitor plate and the first power supply line are disposed in a same layer and are synchronously formed through the same patterning process.
Regarding claim 7, Kim teaches in figures 2-8 and related text that the first circuit unit and the second circuit unit each comprises a storage capacitor (see figures 3 and 5, since each pixel comprises a storage capacitor), the storage capacitor comprises a first plate and a second plate, an orthographic projection of the second plate on a base substrate is at least partially overlapped with an orthographic projection of the first plate on the base substrate (see figure 8); the second plate of the first circuit unit is connected with the second plate of the first circuit unit adjacent in the first direction through a plate connection line to form the power connection line; or, the second plate of the first circuit unit is connected with the second plate of the second circuit unit adjacent in the first direction through a plate connection line to form the power connection line; or, the second plate of the second circuit unit is connected with the second plate of the second circuit unit adjacent in the first direction through a plate connection line to form the power connection line.
Regarding claim 8, Kim teaches in figure 8 and related text that an orthographic projection of the compensation capacitor plate on the base substrate is at least partially overlapped with an orthographic projection of the second plate of the first circuit unit on the base substrate.
Regarding claim 15, Kim teaches in figures 2-8 and related text that a first end of the anode connection line is connected with the second anode electrode, and a second end of the anode connection line is extended to the second display area and is connected with a second anode of the second light emitting device.
Kim does not explicitly state that a first end of the anode connection line is connected with the second anode electrode through a via hole.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to connect a first end of the anode connection line is connected with the second anode electrode through a via hole, in Kim’s device, in order to reduce the size of the device by forming a conventional 3D structure.
Regarding claim 16, Kim teaches in figures 2-8 and related text that the in a plane perpendicular to the display substrate, the first display area DA1 a comprises a first substrate structure layer 100 (see figure 2) disposed on a base substrate 175 and a first light emitting structure layer 200 disposed on a side of the first substrate structure layer away from the base substrate, the first substrate structure layer comprises the plurality of first circuit units and the at least one second circuit unit 200, and the first light emitting structure layer comprises the plurality of first light emitting devices OLD;
the second display area (DA3 and partial area of DA1) comprises a second substrate structure layer disposed on the base substrate and a second light emitting structure layer disposed on a side of the second substrate structure layer away from the base substrate, the second substrate structure layer comprises a plurality of insulation layers, and the second light emitting structure layer comprises the plurality of second light emitting devices.
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (2021/0020704) in view of Osame (2007/0164967).
Regarding claim 9, Kim teaches substantially the entire claimed structure, as applied to claim 1 above, including the first pixel drive circuit and the second pixel drive circuit each further comprises (see figure 6) a first transistor, a second transistor, and a third transistor, a gate electrode of the first transistor is connected (at least electrically connected) with a second scan signal line SL, a first electrode of the first transistor is connected with a first initial signal line DL, a second electrode of the first transistor is connected with a first electrode of the second transistor and a gate electrode of the third transistor, respectively, a gate electrode of the second transistor is connected with a first scan signal line SL-1, and a second electrode of the second transistor is connected with a second electrode of the third transistor; an orthographic projection of the compensation capacitor plate Cst on the base substrate is at least partially overlapped with an orthographic projection of the second electrode of the first transistor T1 of the first pixel drive circuit on the base substrate (see figure 8).
Kim does not explicitly state using the first transistor as a reset transistor, the second transistor as a compensation transistor, and the third transistor as a drive transistor.
Osame teaches in figure 1A and related text that pixel circuit 100 comprises a first transistor as a reset transistor 102, the second transistor 103 as a compensation transistor, and the third transistor as a drive transistor 104.
Osame and Kim are analogous art because they are directed to pixel circuits and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use the first transistor as a reset transistor, the second transistor as a compensation transistor, and the third transistor as a drive transistor, as taught by Osame, in Kim’s device, in order to be able to operate the device in its intended use because it is well known in the art that a pixel comprises a reset transistor, a compensation transistor, and a drive transistor.
Regarding claim 10, Kim teaches in figure 8 and related text that the orthographic projection of the compensation capacitor plate Cst on the base substrate is at least partially overlapped with an orthographic projection of the first electrode of the first transistor T1 of the first pixel drive circuit on the base substrate.
Regarding claim 11, Kim teaches in figure 6 and related text that the first pixel drive circuit and the second pixel drive circuit each further comprises a fourth transistor as a data writing transistor T2 (connected to data line DL) and a fifth transistor T1 as a light emitting control transistor, a gate electrode of the fourth transistor is connected with the first scan signal line, a first electrode of the fourth transistor is connected with a data signal line, a second electrode of the fourth transistor is connected with a first electrode of the third transistor, a gate electrode of the fifth transistor is connected with a light emitting control line, a first electrode of the fifth transistor is connected with a second plate of a storage capacitor Cst, and a second electrode of the fifth transistor is connected with a first electrode of the third transistor; the orthographic projection of the compensation capacitor plate on the base substrate is at least partially overlapped with an orthographic projection of the first electrode of the fifth transistor of the first pixel drive circuit on the base substrate.
Regarding claim 12, Kim teaches in figure 6 and related text that the first pixel drive circuit and the second pixel drive circuit (since both circuits are identical) each further comprises a sixth transistor as a light emitting control transistor, a gate electrode of the sixth transistor is connected with a light emitting control line, a first electrode of the sixth transistor is connected with the second electrode of the third transistor, the first anode electrode is connected with a second electrode of the sixth transistor of the first circuit unit through a via hole (see the modified structure of claim 3 above), and the second anode electrode is connected with a second electrode of the sixth transistor of the second circuit unit through a via hole (see the modified structure of claim 3 above).
Regarding claim 13, Kim teaches in figure 6 and related text that the first pixel drive circuit and the second pixel drive circuit each further comprises a seventh transistor as a reset transistor (as taught by Osame), a gate electrode of the seventh transistor is connected with the second scan signal line, a first electrode of the seventh transistor is connected with a second initial signal line, and a second electrode of the seventh transistor is connected with the second electrode of the sixth transistor.
Regarding claim 14, Kim and Osame teach substantially the entire claimed structure, as applied to the claims above, except having the first pixel drive circuit and the second pixel drive circuit each further comprises a shield electrode connected with the first initial signal line, and the orthographic projection of the compensation capacitor plate on the base substrate is at least partially overlapped with an orthographic projection of the shield electrode of the first pixel drive circuit on the base substrate.
Kim teaches in paragraph [0088] using a shield electrode.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form in each of the first pixel drive circuit and the second pixel drive circuit a shield electrode connected with the first initial signal line, and the orthographic projection of the compensation capacitor plate on the base substrate is at least partially overlapped with an orthographic projection of the shield electrode of the first pixel drive circuit on the base substrate, in prior art’s device in order to provide better electrical protection to the device. It is noted that it is well known in the art to connect the black matrix to a signal line and to further overlap the compensation capacitor plate with an orthographic projection of the shield electrode in order to reduce the parasitic capacitance of the device.
Response to Arguments
1. Applicants argue that “As shown in FIG. 2 of Kim, DA1 includes PA and TA and further as shown in FIG. 3, DA3 and partial DA1 do not have any circuit unit to connect with the light emitting devices in another partial DA1.
1. Figure 2 of Kim depicts that DA1 includes at least two light emitting devices TFT such that one area of DA1 includes one light emitting device and another area of DA1 includes another light emitting device.
2. Applicants argue that “the pixel PXa is not connected to any circuit unit in DA3 or another partial DA1”.
2. Figures 1 and 3 of Kim clearly depict that the various pixels PXa, PXc and PXm are respectively located in DA1, DAc and DAm areas and thus are connected to respective circuit units in DA3 or another partial DA1.
3. Applicants argue that “In addition, even if FIG. 5 of Kim discloses a Cst, however Kim does not disclose that the Cst is used for compensation, therefore Kim does not disclose "compensation capacitor" of claim 1”.
3. The name "compensation capacitor" does not provide specific function of the capacitor since Cst can compensate for various electrical situations.
4. Applicants argue that “Furthermore, Kim does not disclose "first anode electrode" and "second anode electrode" and also does not disclose the connection structure of the above components”.
4. As recited in the rejection, figure 5 depicts the connection structure of the "first anode electrode" and "second anode electrode" of transistors T1 and T2.
Kim is not required to recite the names "first anode electrode" and "second anode electrode" since it is known in the art that transistors comprise anodes.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
2/6/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800