DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application and preliminary amendment filed 4/27/2023 and IDS filed on 11/19/2024. Claims 1-10 are pending, wherein claims 5,7-8 have been amended.
Information Disclosure Statement
The information disclosure statement filed 11/19/2024 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language, wherein all references have been considered except for the “International Search Report and Written Opinion of the International Searching Authority for international Application No.PCT/CN2022/096633 date of mailing 20 July 2022“, which is in Chinese and is only partially translated in English and does NOT provide for the concise explanation of the relevance as noted above. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Khasgiwala et al. (US Patent Application Publication No. 2022/0404878 A1).
As per claim 1, Fig. 9 illustrates the elements of the claim, comprising:
automatically adding at least one of an environmental stabilization system used for implementing temperature compensation and an environmental stabilization system used for implementing electromagnetic shielding (step 908, adds or applies EM (Electromagnetic) shielding material (i.e., for implementing electromagnetic shielding compensation), and thermal material (i.e., for implementing temperature compensation); wherein since this method add materials to the electronic device, it is reasonably understood to one of ordinary skilled in the art that the circuit/chip design and verification process has been completed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2,4-5,7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandra (US Patent No. 7,472,363 B1) in view of Khasgiwala et al. (US Patent Application Publication No. 2022/0404878 A1).
As per claim 1, Chandra teaches the chip design method/system for EDA software (i.e., thermal-aware design automatization suite—see Fig. 4B ) on the basis of a chip (i.e., design data) having a design and verification of a main function thereof completed as illustrated in Fig. 4E (i.e.., as shown in Fig. 4W, the temperature or thermal aware design after the place and route and verification processes are completed, in an interactive loop that allows for repair and modification of the thermally significant structures to equalize temperature variations across the chip (see abstract) by automatically adding at least one of environmental stabilization system used for implementing temperature compensation (i.e., adding/modifying thermal structures). However, Chandra failed to teach implementing environmental stabilization used for implementing electromagnetic shielding. Khasgiwala et al. teach the need for implementing EM shielding as well as thermal protections by adding EM materials and thermal materials to the completed design (see Fig. 9; paragraphs [0023]). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing data of the invention to further incorporate the teachings of Khasgiwala et al. into the method/system of Chandra because such incorporation would further allow for the method/system of Chandra to also take into consideration electromagnetic interference that are also cause malfunction of the electronic circuit as taught by Khasgiwala et al..
As per claim 2, Chandra in view of Khasgiwala et al. teach all of the elements of claim 1, from which the claim depends, as discussed in the rejection of claim 1 above, wherein Chandra further teach:
the preconfiguring at least one function module corresponding to temperature compensation for the chip design; and selecting to add temperature compensation and inputting at least one temperature-related parameter (see col. 4, lines 31-63, i.e., at least one function module was preselected or preconfigured in order to allow for selection of interchangeable components, structures or other design resources to be substituted, wherein the selecting to add temperature compensation is performed to improve temperature distribution under various conditions or temperature-related parameters such as unanticipated localized heating due to increased IR-drops, slower transitions, and longer delays);
automatically calculating a heat generation power required for temperature compensation based on the temperature-related parameter which is required for the environment and adding the function module corresponding to the temperature compensation, for which the schematic diagram and a layout is drawn (see Fig. 5, block 210 perform the thermal analysis and repair which includes calculating heat/thermal generation power using temperature aware power analysis (211) required for temperature compensation, from which schematic diagram and layout are produced through the design processes on the left of side of Fig. 5).
As per claim 4, Chandra in view of Khasgiwala et al. teach all of the elements of claim 2, from which the claim depends, as discussed in the rejection of claim 2 above, wherein Khasgiwala et al. further teach the temperature-related parameter which comprises a lower limit of temperature stability point, a chip operating environment temperature, a package heat dissipation speed, and an estimated chip heat generation power (paragraph [0042]—predetermined thermal threshold would include lower limit of temperature stability point; paragraph [0043]—estimated chip heat generation power, i.e., thermal energy; [0093]—package heat dissipation, i.e., dissipation properties; [0053]—thermal energy of typical operating environment). Chandra also make use of lower limit of temperature stability, operating environment temperature and package heat dissipation speed (col. 13, lines 15-23, i.e., absolute or gradient operating temperatures for chip or package).
As per claim 5, Chandra in view of Khasgiwala et al. teach all of the elements of claim 2, from which the claim depends, as discussed in the rejection of claim 2 above, wherein Chandra also make use of the function module corresponds to temperature compensation comprising: heating control circuit and a heating circuit based on a silicon substrate and resistors, the number, distribution and wiring size of the resistors in the heating circuit are calculated by the EDA software development platform based on a heat generation power of each resistor, and the frame size and coordinates of the completed chip design. (col. 9, lines 33-44, heating elements; claim 19, heating element comprising resistor, on silicon substrate—Fig. 4C; abstract—number, distribution, location or coordinates—abstract; wiring size or width—col. 4, lines 53-63).
As per claim 7, Chandra in view of Khasgiwala et al. teach all of the elements of claim 2, from which the claim depends, as discussed in the rejection of claim 2 above, wherein Chandra further teaches the removal the frame of the completed chip design as part of the hot spot removal analysis which includes differential voltage drop information (i.e., a safe voltage difference between a peripheral heating circuit and a circuit within the frame that has been removed) (see col. 15, lines 15-36; col. 12, lines 4-16), for which the steps as discussed in the rejection of claim 2 apply as discussed above.
As per claim 8, Chandra in view of Khasgiwala et al. teach all of the elements of claim 2, from which the claim depends, as discussed in the rejection of claim 2 above, wherein Chandra also teaches using maximum size of the chip packaging (see col. 18, lines 52-66) as part of the thermal analysis involving steps 12-13 as discussed in the rejections of claim 2 above, from which the claim depends.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandra (US Patent No. 7,472,363 B1) in view of Khasgiwala et al. (US Patent Application Publication No. 2022/0404878 A1) and Chen et al. (US Patent Application Publication No. 2009/0195953 A1).
As per claim 6, Chandra in view of Khasgiwala et al. teach all of the elements of claim 5, from which the claim depends, as discussed in the rejection of claim 5 above, including the adjustment set by the EDA software tool as discussed in the rejection of claim 5 above, but failed to teach that the particular structure of the heating circuit which comprises a second temperature detection circuit for controlling on-off of the power source section, a first temperature detection circuit for driving and controlling the heating current-limiting module, and a positive temperature coefficient resistor and a negative temperature coefficient resistor which are respectively connected with the first and second temperature detection circuits via signal communication and configured to measure the temperature of the chip, and switching thresholds of output control signals of the first and second temperature detection circuits. Such a heating controlling circuit is taught by Chen et al. as part of the over-current protection circuit (see abstract; Figs. 3-4, paragraph [0008]). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of the invention to further incorporate the teachings of Chen et al. into the method/system of Chandra in view of Khasgiwala et al. because such incorporation would further allow for over-current protection due to heating as taught by Chen et al. while benefitting from the design/analysis process of Chandra in view of Khasgiwala et al..
Allowable Subject Matter
Claims 3,9-10 are objected to as being dependent upon a rejected base claim, but would be allowable if claim 3 is rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As per claims 3,9-10, claim 3, from which the respective claims depend, further recites the combination of inventive steps S23 of automatically calculating, by the EDA software development platform, a width and a thickness of a covering metal layer based on the inputted environmental parameter related to selected electromagnetic field intensity as well as a frame size and coordinates of a completed chip design, calling the function module corresponding to electromagnetic shielding to be added to the completed chip design based on the calculated width and thickness of the covering metal layer; from which the corresponding schematic diagram and a layout are drawn, as claimed, which the prior arts made of record failed to teach or suggest as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a process; (2) under Step 2A, Prong One, the claims are not directed to mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations since no expressed equation or formula is recited in the claims; nor are the claims directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits; nor are the claims directed to certain methods of organizing human activity.
Conclusion
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/PHALLAKA KIK/Primary Examiner, Art Unit 2851 March 20, 2026