DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, lines 3-5 of amended claim 1 recite the phrases “a surface”, “one surface” and “the other surface” which creates a lack of clarity as to which structural surfaces are being referred to in the related limitations and so renders the claim indefinite. Claim 4 recites the same phrases and so similarly is indefinite. Additionally, the phrase “the other surface” of claims 1 and 4 lacks antecedent basis. Claims 1 and 4 will, however, be examined as best understood. Further, claims 2 and 5-6 depend from claims 1 and 4 and so are also rejected for their dependency upon rejected claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0224964 A1 to Passek et al. (hereinafter “Passek” – previously cited reference) in further view of EP 1150339 A1 to Watatani (hereinafter “Watatani” – previously cited reference).
Regarding claim 1, as best understood, Passek discloses a substrate, wherein an edge part of the substrate has
a surface sloping from one surface (edge region 34 having surface sloping from top and bottom surfaces of wafer 3; Fig. 5; paragraphs [0073]-[0074]); and
a surface with curvature from the point where the sloping surface ends from one surface to the point where the sloping surface ends from the other surface (terminal edge 6 of edge region 34 having surface with curvature from point where surface sloping from top and bottom surfaces of wafer 3 ends; Fig. 5; paragraph [0074]); and
a root mean square height Sq of the surface sloping from one surface, as measured by the laser microscopy, is 0.15 µm or less; and
a root mean square height Sq of the surface with curvature, as measured by the laser microscopy, is 0.15 µm or less (substrate wafer 3 having a surface roughness at an entire edge region 34 of 0.1-1.5 nm RMS capable of being measured by laser microscopy; abstract; Fig. 5; paragraphs [0008], [0012], [0014], [0050]-[0051], [0073]-[0074]).
Passek fails to disclose an indium phosphide substrate.
However, Watatani discloses an indium phosphide substrate (method of manufacturing InP wafer W including a process of chamfering an outer edge 1 of the wafer; Fig. 1; paragraphs [0007]-[0012]).
Passek and Watatani are both considered to be analogous to the claimed invention because they are in the same field of wafers having specific surface roughness values. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Passek to incorporate the teaching of Watatani in order to potentially provide a substrate with high electron mobility, superior optoelectronic integration, and high breakdown voltage.
Regarding claim 2, Passek in view of Watatani discloses the indium phosphide substrate according to claim 1. Passek further discloses wherein the root mean square height Sq of the surface sloping from one surface, as measured by the laser microscopy, is 0.07 µm or less (substrate wafer 3 having a surface roughness at an entire edge region 34 of 0.1-1.5 nm RMS; abstract).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Watatani in further view of JP 2012174935 A to Takamizawa et al. (hereinafter “Takamizawa” – previously cited reference).
Regarding claim 4, Watatani discloses a method for manufacturing an indium phosphide substrate, comprising
a process of chamfering an outer edge part of an indium phosphide wafer (method of manufacturing InP wafer W including a process of chamfering an outer edge 1 of the wafer; Fig. 1; paragraphs [0007]-[0012]) so that an edge part of the substrate has
a surface sloping from one surface; and
a surface with curvature from the point where the sloping surface ends from one surface to the point where the sloping surface ends from the other surface (chamfered portion 1 having surface sloping from top and bottom surfaces of wafer W and having terminal edge surface with curvature from point where surface sloping from top and bottom surfaces of wafer W ends; Fig. 1; paragraphs [0012], [0027]),
a process of polishing the entire surface of the edge part of the indium phosphide wafer after the chamfering (polishing is performed on the InP wafer W after chamfering with #1500 grain size; paragraphs [0017]-[0019]), and
a process of etching the indium phosphide wafer after polishing the edge part of the indium phosphide wafer (etching is performed on polished chamfered outer edge 1 of InP wafer W; paragraphs [0022]-[0023]).
Watatani fails to disclose chamfering with a #4000 grade polishing film.
However, Takamizawa discloses chamfering with a #4000 grade polishing film (beveled portion of a substrate is ground by using a tape polishing apparatus in which #3000 or even finer, higher-count abrasive grains are electrodeposited; paragraph [0043]).
Watatani and Takamizawa are both considered to be analogous to the claimed invention because they are in the same field of wafer fabrication processes using fine polishing techniques. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Watatani to incorporate the teaching of Takamizawa in order to potentially provide a substrate surface roughness on the order of nanometers which minimizes surface irregularities critical to grow epitaxial layers thereupon. Further, such smoother surfaces enhance performance of devices like lasers and photodetectors which may utilize InP wafers.
Regarding claim 5, Watatani in view of Takamizawa disclose the method for manufacturing an indium phosphide substrate according to claim 4. Watatani further discloses further comprising a process of polishing at least one surface of the indium phosphide wafer between the process of chamfering the outer edge part of the indium phosphide wafer and the process of polishing the entire surface of the edge part of the indium phosphide wafer after the chamfering (polishing is iteratively performed after the chamfering process; paragraph [0023]).
Watatani fails to disclose chamfering with a #4000 grade polishing film.
However, Takamizawa discloses chamfering with a #4000 grade polishing film (beveled portion of a substrate is ground by using a tape polishing apparatus in which #3000 or even finer, higher-count abrasive grains are electrodeposited; paragraph [0043]).
Watatani and Takamizawa are both considered to be analogous to the claimed invention because they are in the same field of wafer fabrication processes using fine polishing techniques. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Watatani to incorporate the teaching of Takamizawa in order to potentially provide a substrate surface roughness on the order of nanometers which minimizes surface irregularities critical to grow epitaxial layers thereupon. Further, such smoother surfaces enhance performance of devices like lasers and photodetectors which may utilize InP wafers.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Watatani as modified by Takamizawa in further view of Passek.
Regarding claim 6, Watatani in view of Takamizawa disclose a semiconductor epitaxial wafer, comprising the indium phosphide substrate according to claim 1 (InP wafer W cut from crystal ingot using cleavage; paragraph [0008]).
Watatani fails to disclose an epitaxial crystal layer on a main surface of the substrate.
However, Passek discloses an epitaxial crystal layer on a main surface of the substrate (wafer to be coated with an epitaxial layer on all surfaces; abstract).
Watatani and Passek are both considered to be analogous to the claimed invention because they are in the same field of wafer fabrication processes using fine polishing techniques. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Watatani to incorporate the teaching of Passek in order to potentially provide precise control of material properties of the resulting device such as bandgap, doping, and thickness which further allows monolithic integration of multiple device types such as lasers, detectors, waveguides and transistors on a single chip.
Response to Arguments
Applicant's arguments filed December 29, 2025 have been fully considered. Applicant presents substantive amendments to claim 1 and 4 and corresponding arguments. Applicant asserts that Passek does not disclose “a shape in which both and inclined surface and a curved surface coexist,” but this language does not appear in claims 1 and 4. The associated language in claims 1 and 4 reads “a surface sloping from one surface” and “a surface with curvature from the point where the sloping surface ends from one surface to the point where the sloping surface ends from the other surface” which collectively is broader than “a shape in which both and inclined surface and a curved surface coexist.” If Applicant wishes this narrower interpretation to be the construction of claims 1 and 4, then such language should be amended into claims 1 and 4. The current language is disclosed by Passek and Watatani given that each reference discloses a surface sloping from top and bottom surfaces of a wafer and a surface with curvature extending from the sloping surface. Applicant appears to assert that “the sloping surface” should be construed narrowly as a flat surface with a uniform upward or downward slope. However, Examiner is required to utilize the broadest reasonable interpretation of the claim language which is read on by the disclosure of Passek and Watatani in that at every point along a curved surface there exists a slope tangent to that curve, providing a variable slope along the curved surface, which satisfies the associated limitations amended into claims 1 and 4.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818