DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 02/05/2026 was incomplete as it did not contain a response to the Restriction Requirement mailed 01/27/2026. A subsequent telephone call was made to Svetlana Short on 03/18/2026. An election of Group I, claims 1-14 was made without traverse in the telephone conversation on 03/18/2026.
Claims 15-35 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claims 1-14 have been fully considered in Examination.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 02/13/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
[0013] of the instant application is objected to because it discloses that “the passivation layer directly contacts at least a portion of the sidewall and the additional sidewall”, however, is it unclear what “the sidewall” and “the additional sidewall” refer to because there are multiple sidewall and additional sidewall elements introduced. The instant application fails to demonstrate how ‘the passivation layer directly contacts at least a portion of the sidewall (of the patterned metallic electrode) and the additional sidewall (of the source/drain electrode)’, as the pertinent sidewalls of these electrodes are covered by the respective sidewall barrier layers. [0013] of the instant application should be amended to clarify the statement “the passivation layer directly contacts at least a portion of the sidewall and the additional sidewall” in a manner consistent with the 35 U.S.C. 112(b) rejection of claim 10 below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "wherein the passivation layer directly contacts at least a portion of the sidewall and the additional sidewall" in lines 3-4. Claim 10 is rendered indefinite because it is not clear “the sidewall” and “the additional sidewall” refer to the claimed sidewalls of the patterned metallic electrode and source/drain electrode, respectively, or “the sidewall barrier layer” and ”the additional sidewall barrier layer”, respectively, or yet another pair of ‘sidewalls’. It is emphasized that the instant application fails to demonstrate how ‘the passivation layer directly contacts at least a portion of the sidewall (of the patterned metallic electrode) and the additional sidewall (of the source/drain electrode)’. Therefore, for the purposes of Examination, "wherein the passivation layer directly contacts at least a portion of the sidewall and the additional sidewall" has been interpreted by Examiner as --- "wherein the passivation layer directly contacts at least a portion of the sidewall barrier layer and the additional sidewall barrier layer" --- however, this edit may be altered if Applicant intends otherwise.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 6-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (U.S. PG Pub No US2015/0171154A1).
Regarding claim 1, Kang teaches a semiconductor device (1) fig. 4 [0065] comprising:
a substrate (110) fig. 4 [0071] including a device surface (top of 110, hosting transistor area [0069]);
a patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085] disposed on (supported by) the substrate (110), the patterned metallic electrode (216a-2) being formed of copper [0078], the patterned metallic electrode (216a-2) comprising a lower surface (bottom of 216a-2) proximate to (closest to) the substrate (110), an upper surface (top of 216a-2), and a sidewall (right sidewall of 216a-2) extending between the lower surface (bottom of 216a-2) and the upper surface (top of 216a-2); and
a sidewall barrier layer (left 240) fig. 4 [0085-0086] extending (directly) over the sidewall (right sidewall of 216a-2).
Regarding claim 6, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 1. Kang also teaches further comprising an oxide-containing passivation layer (119) fig. 4 [0082] (phenol-group polymer of 119 contains oxygen [0082]) disposed on (supported by) the patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085], the oxide-containing passivation layer (119) directly contacting at least a portion of the sidewall barrier layer (left 240) fig. 4 [0085-0086].
Regarding claim 7, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 1. Kang also teaches further comprising:
a gate electrode (212) fig. 4 [0070] disposed on (supported by) the substrate (110) fig. 4 [0071];
a dielectric layer (113) fig. 4 [0073] disposed on the gate electrode (212);
a semiconductor layer (214) fig. 4 [0074] disposed on the dielectric layer (113);
a source electrode (216a-2) fig. 4 [0078] disposed on a first portion (left half) of the semiconductor layer (214); and
a drain electrode (216b-2) fig. 4 [0078] disposed on a second portion (right half) of the semiconductor layer (214), wherein:
the source electrode (216a-2) and the drain electrode (216b-2) overlap the gate electrode (212) in a (vertical) direction extending perpendicular to the device surface (top of 110) at first (left portion of 212 overlapped by 216a-2) and second (right portion of 212 overlapped by 216b-2) gate overlap regions; and
the patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085] is the source electrode (216a-2) [0078] such that the sidewall barrier layer (left 240) fig. 4 [0085-0086] directly contacts the source electrode (216a-2) [0078] and/or the drain electrode (216b-2) [0078].
Regarding claim 8, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 7. Kang also teaches wherein the other of the drain electrode (216b-2) fig. 4 [0078] that is not the patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085] comprises a lower surface (bottom of 216b-2) proximate to (closest to) the substrate (110) fig. 4 [0071], an upper surface (top of 216b-2), and an additional sidewall (left sidewall of 216b-2) extending between the lower surface (bottom of 216b-2) and the upper surface (top of 216b-2), the semiconductor device (1) further comprising an additional sidewall barrier layer (right 240) fig. 4 [0085-0086] disposed locally over the additional sidewall (left sidewall of 216b-2).
Regarding claim 9, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 8. Kang also teaches wherein lengths of the first (left portion of 212 overlapped by 216a-2) and second (right portion of 212 overlapped by 216b-2) gate overlap regions differ from one another by less than or equal to l 0 nm (216a-2 and 216b-2 are shown disposed symmetrically about the center of gate 212 such that length of the first, left portion of 212 overlapped by 216a-2 is assumed to be substantially identical to the length of the second, right portion of 212 overlapped by 216b-2, such that their difference is ~ 0nm < 10nm).
Regarding claim 10, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 8. Kang also teaches further comprising a passivation layer (119) fig. 4 [0082] disposed on (supported by) the source electrode (216a2) fig. 4 [0077, 0081, 0085] and the drain electrode (216b-2) fig. 4 [0078], the passivation layer (119) containing an oxide (phenol-group polymer of 119 contains oxygen [0082]), wherein the passivation layer (119) directly contacts at least a portion of the sidewall barrier layer (left 240) fig. 4 [0085-0086] and the additional sidewall barrier layer (right 240) fig. 4 [0085-0086].
Regarding claim 11, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 10. Kang also teaches further comprising an additional metallic layer (216-a3/216-b3) fig. 4 [0079] (formed of molybdenum) disposed on (supported by) the source electrode (216a-2) fig. 4 [0078] and the drain electrode (216b-2) fig. 4 [0078].
Regarding claim 12, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 8. Kang also teaches further comprising a copper barrier layer (upper, copper layer of 212 multilayer) fig. 4 [0072] disposed locally over the gate electrode (lower layer of 212 multilayer) fig. 4 [0072], the copper barrier layer (upper 212 layer) [0072] directly contacting the gate electrode (lower 212 layer) [0072] (212 may represent a multi-layered / bilayer stack of two copper layers [0072], with an upper copper sublayer of 212 directly stacked on the lower gate electrode sublayer of 212).
Regarding claim 13, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 1. Kang also teaches wherein the patterned metallic electrode (216a2) fig. 4 [0077, 0078, 0081, 0085] is a component (source/electrode [0070, 0078]) of a thin film transistor (21 of TR1) fig. 4 [0069-0070].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-5 rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2015/0171154A1), as applied in claim 1 above, in view of Okamoto (U.S. PG Pub No US2011/0315966A1).
Regarding claim 2, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 1. However, Kang does not explicitly disclose wherein the sidewall barrier layer (left 240) fig. 4 [0085-0086] comprises a magnesium oxide barrier layer (may be formed as same material as 241 [0086]; 241/240 may both be formed of magnesium, however, magnesium oxide not explicitly mentioned).
Okamoto teaches a semiconductor device (10) fig. 5 [0130] wherein the sidewall barrier layer (18) fig. 5 [0131] comprises a magnesium oxide [0131] barrier layer (18) fig. 5 [0131].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the sidewall barrier layer of Kang to comprise a thin magnesium oxide layer [0131] in order to trap oxygen and other radicals [0131] produced by the device electrodes [0131], thereby protecting adjacent layers from damage [0131], as taught by Okamoto.
Regarding claim 3, Kang in view of Okamoto teaches the semiconductor device (1) fig. 4 [0065] of claim 1. Kang in view of Okamoto (with reference to Okamoto) also teaches wherein the sidewall barrier layer (18) fig. 5 [0131] comprises a thickness of greater than or equal to 1nm and less than or equal to 5 nm) (0.1-3nm, which overlaps with 1-5nm from 1-3 nm) [0131].
While Okamoto discloses a slightly different range of thicknesses (0.1nm-3nm [0131 Okamoto]) than the claimed range of 1-5nm, these ranges overlap. Therefore, in the absence of criticality of the claimed range, one of ordinary skill in the art would consider these ranges sufficiently similar such that the claimed range for the thickness of the magnesium oxide layer is obvious over the teachings of Okamoto. (See MPEP 2144.05, I).
Regarding claim 4, Kang in view of Okamoto teaches the semiconductor device (1) fig. 4 [0065] of claim 2. Kang also teaches further comprising:
a first barrier layer (216a-1) fig. 4 [0078] contacting the lower surface (bottom of 216a-2) and disposed (vertically) between the patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085] and the substrate (110) fig. 4 [0071]; and
a second barrier layer (216a-3) fig. 4 [0078] contacting the upper surface (top of 216a-2), wherein neither the first barrier layer (216a-1) nor the second barrier layer (216a-3) directly contacts the sidewall (right sidewall of 216a-2).
Regarding claim 5, Kang in view of Okamoto teaches the semiconductor device (1) fig. 4 [0065] of claim 4. Kang also teaches wherein the sidewall barrier layer (left 240) fig. 4 [0085-0086] is disposed between (extending in the space vertically between) the first barrier layer (216a-1) fig. 4 [0078] and the second barrier layer (216a-3) fig. 4 [0078] directly on the sidewall (right sidewall of 216a-2).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2015/0171154A1), as applied in claim 11 above, in view of Shi (U.S. PG Pub No US2018/0239485A1).
Regarding claim 14, Kang teaches the semiconductor device (1) fig. 4 [0065] of claim 11. However, Kang does not explicitly disclose wherein the thin film transistor (21 of TR1) fig. 4 [0069-0070] is a component of a touch panel display (touch panel not disclosed).
Shi teaches a semiconductor device [see fig. 6, 0071] wherein the thin film transistor (comprising 7’ and 10’) fig. 6 [0071] is a component of a touch panel display (display comprising 4 and 7) fig. 6 [0070-0071].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the display of Kang such that the thin film transistor integrated with touch panel display circuitry [0070-0071] of Shi in order to enhance user appeal of the display by providing touch capacity [0003, 0073] while offering lowered contact resistance and reduced display and touch control defects [0074-0075] over traditional touch panel circuitry, as taught by Shi.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are all considered relevant to the present disclosure because they all feature transistor structures with patterned electrodes having barrier layers on their sidewalls.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 04/01/2026
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