DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
The Amendments filed June 25th, 2026, in response to the Non-Final Office Action mailed 04/06/2026 are noted. Applicants’ amendment(s) to the Specification have overcome the objection(s) to the Specification previously set forth in the Non-Final Office Action mailed 04/06/2026, so the objection(s) to the Specification has been withdrawn.
Applicant’s amendment(s) to the claims have overcome the 35 U.S.C. § 112 rejection(s)
previously set forth in the Non-Final Office Action mailed 04/06/2026, so the 35 U.S.C. § 112
rejection(s) have been withdrawn.
Applicants’ amendments to the claims are noted.
3. Claim 2 is now canceled; Claims 1 and 3-35 remain pending in the application; Claims 15-35 are now withdrawn.
4. Claims 1 and 2-14 have been fully considered in examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/21/2026 was filed after the mailing date of the Non-Final Office Action on 08/21/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 is rendered indefinite because it depends on claim 2, which was canceled. Therefore, the scope of claim 3 is unclear. For the purposes of Examination, Examiner has interpreted claim 3 as depending upon claim 1.
Claim 4 is rendered indefinite because it depends on claim 2, which was canceled. Therefore, the scope of claim 4 is unclear. For the purposes of Examination, Examiner has interpreted claim 4 as depending upon claim 1. Claim 5 is also rejected by virtue of its dependency on claim 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 4-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2015/0171154A1) (of record) in view of Ryu (U.S. PG Pub No US2016/0211281A1).
Regarding claim 1, Kang teaches a semiconductor device (1) fig. 4 [0065] comprising:
a substrate (110) fig. 4 [0071] including a device surface (top of 110, hosting transistor area [0069]);
a patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085] disposed on (supported by) the substrate (110), the patterned metallic electrode (216a-2) being formed of copper [0078], the patterned metallic electrode (216a-2) comprising a lower surface (bottom of 216a-2) proximate to (closest to) the substrate (110), an upper surface (top of 216a-2), and a sidewall (right sidewall of 216a-2) extending between the lower surface (bottom of 216a-2) and the upper surface (top of 216a-2); and
a sidewall barrier layer (left 240) fig. 4 [0085-0086] extending (directly) over the sidewall (right sidewall of 216a-2).
However, Kang does not explicitly disclose the sidewall barrier layer (left 240) fig. 4 [0085] comprising manganese oxide (may be formed of same material as 241 [0086] – may be metal oxide [0093], but manganese not explicitly disclose) [0093].
Ryu teaches a semiconductor device [see fig. 2, 0044, 0065-0067] comprising the sidewall barrier layer (108) fig. 2 [0066] comprising manganese oxide [0066].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Kang such that the metal oxide barrier layer is composed of a metal oxide such as manganese oxide [0066] because of the art recognized suitability of manganese oxide as the barrier layer of the spacer of a thin film transistor [0066], as taught by Ryu. However, such a modification reflects material substitutions for the same purpose – i.e, as a metal oxide material for the sidewall spacer in a thin film transistor. (See MPEP 2144.06, II).
Regarding claim 4, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 1. Kang also teaches further comprising:
a first barrier layer (216a-1) fig. 4 [0078] contacting the lower surface (bottom of 216a-2) and disposed (vertically) between the patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085] and the substrate (110) fig. 4 [0071]; and
a second barrier layer (216a-3) fig. 4 [0078] contacting the upper surface (top of 216a-2), wherein neither the first barrier layer (216a-1) nor the second barrier layer (216a-3) directly contacts the sidewall (right sidewall of 216a-2).
Regarding claim 5, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 4. Kang also teaches wherein the sidewall barrier layer (left 240) fig. 4 [0085-0086] is disposed between (extending in the space vertically between) the first barrier layer (216a-1) fig. 4 [0078] and the second barrier layer (216a-3) fig. 4 [0078] directly on the sidewall (right sidewall of 216a-2).
Regarding claim 6, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 1. Kang also teaches further comprising an oxide-containing passivation layer (119) fig. 4 [0082] (phenol-group polymer of 119 contains oxygen [0082]) disposed on (supported by) the patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085], the oxide-containing passivation layer (119) directly contacting at least a portion of the sidewall barrier layer (left 240) fig. 4 [0085-0086].
Regarding claim 7, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 1. Kang also teaches further comprising:
a gate electrode (212) fig. 4 [0070] disposed on (supported by) the substrate (110) fig. 4 [0071];
a dielectric layer (113) fig. 4 [0073] disposed on the gate electrode (212);
a semiconductor layer (214) fig. 4 [0074] disposed on the dielectric layer (113);
a source electrode (216a-2) fig. 4 [0078] disposed on a first portion (left half) of the semiconductor layer (214); and
a drain electrode (216b-2) fig. 4 [0078] disposed on a second portion (right half) of the semiconductor layer (214), wherein:
the source electrode (216a-2) and the drain electrode (216b-2) overlap the gate electrode (212) in a (vertical) direction extending perpendicular to the device surface (top of 110) at first (left portion of 212 overlapped by 216a-2) and second (right portion of 212 overlapped by 216b-2) gate overlap regions; and
the patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085] is the source electrode (216a-2) [0078] such that the sidewall barrier layer (left 240) fig. 4 [0085-0086] directly contacts the source electrode (216a-2) [0078] and/or the drain electrode (216b-2) [0078].
Regarding claim 8, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 7. Kang also teaches wherein the other of the drain electrode (216b-2) fig. 4 [0078] that is not the patterned metallic electrode (216a2) fig. 4 [0077, 0081, 0085] comprises a lower surface (bottom of 216b-2) proximate to (closest to) the substrate (110) fig. 4 [0071], an upper surface (top of 216b-2), and an additional sidewall (left sidewall of 216b-2) extending between the lower surface (bottom of 216b-2) and the upper surface (top of 216b-2), the semiconductor device (1) further comprising an additional sidewall barrier layer (right 240) fig. 4 [0085-0086] disposed locally over the additional sidewall (left sidewall of 216b-2).
Regarding claim 9, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 8. Kang also teaches wherein lengths of the first (left portion of 212 overlapped by 216a-2) and second (right portion of 212 overlapped by 216b-2) gate overlap regions differ from one another by less than or equal to l 0 nm (216a-2 and 216b-2 are shown disposed symmetrically about the center of gate 212 such that length of the first, left portion of 212 overlapped by 216a-2 is assumed to be substantially identical to the length of the second, right portion of 212 overlapped by 216b-2, such that their difference is ~ 0nm < 10nm).
Regarding claim 10, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 8. Kang also teaches further comprising a passivation layer (119) fig. 4 [0082] disposed on (supported by) the source electrode (216a2) fig. 4 [0077, 0081, 0085] and the drain electrode (216b-2) fig. 4 [0078], the passivation layer (119) containing an oxide (phenol-group polymer of 119 contains oxygen [0082]), wherein the passivation layer (119) directly contacts at least a portion of the sidewall barrier layer (left 240) fig. 4 [0085-0086] and the additional sidewall barrier layer (right 240) fig. 4 [0085-0086].
Regarding claim 11, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 10. Kang also teaches further comprising an additional metallic layer (216-a3/216-b3) fig. 4 [0079] (formed of molybdenum) disposed on (supported by) the source electrode (216a-2) fig. 4 [0078] and the drain electrode (216b-2) fig. 4 [0078].
Regarding claim 12, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 8. Kang also teaches further comprising a copper barrier layer (upper, copper layer of 212 multilayer) fig. 4 [0072] disposed locally over the gate electrode (lower layer of 212 multilayer) fig. 4 [0072], the copper barrier layer (upper 212 layer) [0072] directly contacting the gate electrode (lower 212 layer) [0072] (212 may represent a multi-layered / bilayer stack of two copper layers [0072], with an upper copper sublayer of 212 directly stacked on the lower gate electrode sublayer of 212).
Regarding claim 13, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 1. Kang also teaches wherein the patterned metallic electrode (216a2) fig. 4 [0077, 0078, 0081, 0085] is a component (source/electrode [0070, 0078]) of a thin film transistor (21 of TR1) fig. 4 [0069-0070].
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2015/0171154A1) (of record) modified by Ryu (U.S. PG Pub No US2016/0211281A1), as applied in claim 1 above, and further in view of Okamoto (U.S. PG Pub No US2011/0315966A1) (of record).
Regarding claim 3, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 1. However, Kang does not explicitly disclose wherein the sidewall barrier layer (left 240) fig. 4 [0085-0086] comprises a thickness of greater than or equal to 1nm and less than or equal to 5 nm (thickness of 240 not explicitly disclosed).
Okamoto teaches a semiconductor device (10) fig. 5 [0130] wherein the sidewall barrier layer comprises a thickness of greater than or equal to 1nm and less than or equal to 5 nm) (0.1-3nm, which overlaps with 1-5nm from 1-3 nm) [0131].
While Okamoto discloses a slightly different range of thicknesses (0.1nm-3nm [0131 Okamoto]) than the claimed range of 1-5 nm, these ranges overlap. Therefore, in the absence of criticality of the claimed range, one of ordinary skill in the art would consider these ranges sufficiently similar such that the claimed range for the thickness of the metal oxide layer is obvious over the teachings of Okamoto. (See MPEP 2144.05, I).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the sidewall barrier layer of Kang to comprise a thin metal oxide layer [0131] in order to ensure appropriate thickness for the trapping oxygen and other radicals [0131] produced by the device electrodes [0131], thereby protecting adjacent layers from damage [0131], as taught by Okamoto.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kang (U.S. PG Pub No US2015/0171154A1) (of record) modified by Ryu (U.S. PG Pub No US2016/0211281A1), as applied in claim 13 above, and further in view of Shi (U.S. PG Pub No US2018/0239485A1) (of record).
Regarding claim 14, Kang in view of Ryu teaches the semiconductor device (1) fig. 4 [0065] of claim 13. However, Kang does not explicitly disclose wherein the thin film transistor (21 of TR1) fig. 4 [0069-0070] is a component of a touch panel display (touch panel not disclosed).
Shi teaches a semiconductor device [see fig. 6, 0071] wherein the thin film transistor (comprising 7’ and 10’) fig. 6 [0071] is a component of a touch panel display (display comprising 4 and 7) fig. 6 [0070-0071].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the display of Kang such that the thin film transistor integrated with touch panel display circuitry [0070-0071] of Shi in order to enhance user appeal of the display by providing touch capacity [0003, 0073] while offering lowered contact resistance and reduced display and touch control defects [0074-0075] over traditional touch panel circuitry, as taught by Shi.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are all considered relevant to the present disclosure because they all feature transistor structures with patterned electrodes having barrier layers on their sidewalls.
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 09/17/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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