Attorney Docket Number: PWWUS210049-MO
Filing Date: 05/08/2023
Claimed Priority Dates: 11/01/2021 (371 of PCT/CN2021/127968)
11/06/2020 (CN 202011233504X)
Inventors: Tan et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the election filed on 01/26/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Elections/Restrictions
Applicant’s election without traverse of Invention II, reading on a method of making a device, and with traverse of Species 1, reading on the first embodiment described in figures 1 and 3-17, in the reply filed on 01/26/2026, is acknowledged. Regarding Applicant’s election with traverse, because Applicant did not distinctly and specifically point out or indicate any supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Applicant indicated that claims 6-8 and 10-11 read on the elected species. The examiner agrees. Accordingly, claims 1-5, 9, and 12 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected invention and/or species, there being no allowable generic or linking claim.
Initial Remarks
For all non-U.S.-reference paragraph and line citations, please refer to the original versions of these documents, which are attached to this Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 10-11 are rejected under 35 U.S.C. 112(b) for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 recites the limitations “forming a first trench gate layer over the semi-insulating resistive-field-plate layer and electrically connected to the semi-insulating resistive-field-plate layer” and “wherein the semi-insulating resistive-field-plate layer… constitute the semi-insulating resistive-field-plate structure”. No “semi-insulating resistive-field-plate layer” has been sufficiently previously recited in the claim or in any parental claim. Accordingly, there is insufficient antecedent basis for these limitations in the claim.
Claim 11 recites the limitations “forming the first trench gate layer over the semi-insulating resistive-field-plate layer”, “filling a first doped polysilicon material in the trench over the semi-insulating resistive-field-plate layer”, and “wherein the first doped polysilicon material at least covers the top surface of the semi-insulating resistive-field-plate layer”. No “semi-insulating resistive-field-plate layer” has been sufficiently previously recited in the claim or in any parental claim. Accordingly, there is insufficient antecedent basis for these limitations in the claim.
Claims 10 and 11 depend from claim 8 and thus inherit the deficiencies identified supra.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 6 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duan I (CN 107437566A).
Regarding claim 6, Duan I (see, e.g., fig. 1 and pars.0025-0036 and 0055-0068) shows all aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate comprising:
providing a substrate 7 and forming an epitaxial layer 8 on the substrate (see, e.g., pars.0026-0027 and 0056-0057);
forming a MOS channel region 9, a MOS source region 11, and a MOS channel contact region 10 within a top portion of the epitaxial layer (see, e.g., pars.0028, 0033, 0045-0046, 0051, 0058, and 0063);
forming a trench in the epitaxial layer, wherein the trench vertically extends through the MOS source region, the MOS channel region, and the epitaxial layer to the substrate (see, e.g., pars.0029 and 0059);
sequentially forming a semi-insulating resistive-field-plate structure 2/(regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014, 0034, 0052, 0064-0065) and a trench gate structure 2/4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014, 0034, 0052, 0064-0065) in the trench along a bottom-to-top direction of the trench, wherein the semi-insulating resistive-field-plate structure is electrically connected to the trench gate structure, and an end of the semi-insulating resistive-field-plate away from the trench gate structure is electrically connected to the substrate (see, e.g., pars.0014, 0030-0031, 0034, 0060-0061, 0064);
forming a source electrode 1 or (not shown – see, e.g., par.0067), a gate electrode 4 or (not shown – see, e.g., par.0067), and a drain electrode 6 (see, e.g., pars.0010-0011, 0014, and 0067-0068)
wherein:
the trench gate structure 2/4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014, 0034, 0052, 0064-0065) and the semi-insulating resistive-field-plate structure 2/(regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014, 0034, 0052, 0064-0065) share an isolation dielectric layer 2
Claim 6 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Duan II (CN 107046062A).
Regarding claim 6, Duan II (see, e.g., fig. 1 and pars.0026-0037 and 0057-0069) shows all aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate comprising:
providing a substrate 7 and forming an epitaxial layer 8 on the substrate (see, e.g., pars.0027-0028 and 0057-0058);
forming a MOS channel region 9, a MOS source region 11, and a MOS channel contact region 10 within a top portion of the epitaxial layer (see, e.g., pars.0029, 0034, 0046-0047, 0052, 0059, and 0064);
forming a trench in the epitaxial layer, wherein the trench vertically extends through the MOS source region, the MOS channel region, and the epitaxial layer to the substrate (see, e.g., pars.0030 and 0060);
sequentially forming a semi-insulating resistive-field-plate structure 2/(regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) and a trench gate structure 2/4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) in the trench along a bottom-to-top direction of the trench, wherein the semi-insulating resistive-field-plate structure is electrically connected to the trench gate structure, and an end of the semi-insulating resistive-field-plate away from the trench gate structure is electrically connected to the substrate (see, e.g., pars.0014-0015, 0031-0032, 0035, 0061-0062, and 0065);
forming a source electrode 1 or (not shown – see, e.g., par.0068), a gate electrode 4 or (not shown – see, e.g., par.0068), and a drain electrode 6 (see, e.g., pars.0010-0011, 0014-0015, and 0068-0069)
wherein:
the trench gate structure 2/4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) and the semi-insulating resistive-field-plate structure 2/(regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) share an isolation dielectric layer 2
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Duan I in view of Ng (EP 1170803A2) and Disney (US 2013/0032895).
Regarding claim 7, Duan I (see, e.g., fig. 1 and pars.0025-0036 and 0055-0068) shows most aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate according to claim 6 (see paragraph 11 above), wherein the step of forming the MOS channel region 9, the MOS source region 11, and the MOS channel contact region 10 within the top portion of the epitaxial layer 8 (see, e.g., pars.0028, 0033, 0045-0046, 0051, 0057-0058, and 0063) comprises:
forming the MOS channel region 9 within the top portion of the epitaxial layer by a first ion implantation (see, e.g., pars.0028 and 0057-0058);
forming the MOS source region 11 disposed over the MOS channel region by a second ion implantation (see, e.g., pars.0033, 0051, and 0063); and
forming the MOS channel contact region 10 by a third ion implantation (see, e.g., pars.0033, 0051, and 0063), wherein the MOS channel contact region is in contact with the MOS channel region
Regarding claim 7, Duan I shows most aspects of the instant invention. Furthermore, Duan I (see, e.g., pars.0008, 0028, 0045-0046, and 0058) teaches that Duan I’s MOS channel region is a doped region of Duan I’s epitaxial layer and that Duan I’s MOS channel region may be formed by a first ion implantation. However, Duan I fails to explicitly specify that Duan I’s MOS channel region may be formed by a first ion implantation and a first ion diffusion. Ng, in the same field of endeavor and in a similar device to Duan I, teaches that conventional processes for forming channel layers including both a first ion implantation and a first ion diffusion processes (see, e.g., Ng: par.0046/ll.1-2). Furthermore, Disney, also in the same field of endeavor and in a similar device to Duan I, teaches that performing a first ion diffusion after a first ion implantation step can aid in smoothing out the lateral doping profile of doped regions in a semiconductor transistor device (see, e.g., Disney: par.0043/ll.19-24).
Ng and Disney are evidence showing that one of ordinary skill in the art would appreciate that a MOS channel region formed by a first ion implantation and a first ion diffusion would be equivalent to a MOS channel region formed by a first ion implantation, and that such differences would result in no unexpected changes in the performance of the device of Duan I. That is, the MOS channel region formation methods of both Ng or Disney and Duan I would yield the predictable result of providing a suitable methodology for forming appropriate channel regions capable of supporting other conductivity-type structures in a transistor/MOS device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a MOS channel region formed by a first ion implantation and a first ion diffusion, as taught by Ng and Disney, or a MOS channel region formed by a first ion implantation, as taught by Duan I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable methodology for forming appropriate channel regions capable of supporting other conductivity-type structures in a transistor/MOS device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Disney is evidence that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have a MOS channel region formed by a first ion implantation and a first ion diffusion, as taught by Disney, so as employ a process facilitating smoothing out the lateral doping profile of a doped channel region in a semiconductor transistor device.
Claims 8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Duan I in view of Verma (US 2014/0021534).
Regarding claim 8, Duan I (see, e.g., fig. 1 and pars.0025-0036 and 0055-0068) shows most aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate according to claim 6 (see paragraph 11 above), wherein the step of sequentially forming the semi-insulating resistive-field-plate structure 2/(regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014, 0034, 0052, 0064-0065) and the trench gate structure 2/4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014, 0034, 0052, 0064-0065) in the trench along the bottom-to-top direction of the trench comprises:
forming an isolation dielectric layer 2 on a sidewall of the trench (see, e.g., pars.0030 and 0060);
filling the trench (see, e.g., pars.0031 and 0061) to form a semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014, 0034, 0052, 0064-0065), wherein the semi-insulating resistive field-layer-plate layer has a top surface and the MOS channel region 9 has a bottom surface;
forming a first trench gate layer 4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014, 0034, 0052, 0064-0065) over the semi-insulating resistive-field-plate layer and electrically connected to the semi-insulating resistive-field-plate layer (see, e.g., pars.0014, 0030-0031, 0034, 0060-0061, and 0064);
wherein:
the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014, 0034, 0052, 0064-0065) and the isolation dielectric layer 2 constitute the semi-insulating resistive-field plate structure 2/(regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014, 0034, 0052, 0064-0065), and the first trench gate layer 4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014, 0034, 0052, 0064-0065) and the isolation dielectric layer constitute the trench gate structure 2/4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014, 0034, 0052, 0064-0065)
Regarding claim 8, Duan I shows most aspects of the instant invention. Duan I (see, e.g., fig. 1) further shows that Duan I’s semi-insulating resistive-field-plate layer directly contacts both Duan I’s isolation dielectric layer and substrate. However, Duan I fails to specify that forming Duan I’s isolation dielectric layer comprises oxidating a bottom and a sidewall of the trench and etching and removing part of the isolation dielectric layer at the bottom of the trench. Furthermore, Duan I (see, e.g., fig. 1) shows that a top surface of Duan I’s resistive-field-plate layer is aligned with a bottom surface of Duan I’s MOS channel region, and fails to specify that a top surface of the semi-insulating resistive-field-plate layer is lower than a bottom surface of Duan I’s MOS channel region. Verma, in the same field of endeavor and in a similar device to Duan I, teaches a methodology for sequentially forming a semi-insulating resistive-field-plate structure 132/140b and a trench gate structure 132/140a along a bottom-to-top direction of a trench 564/568, wherein forming an isolation dielectric layer 132 comprises oxidating a bottom and a sidewall of the trench and etching and removing part of the isolation dielectric layer at the bottom of the trench, and wherein the trench is filled to form a semi-insulating resistive-field-plate layer 140b, whereby a top surface of the semi-insulating resistive-field-plate layer is lower than a bottom surface of an MOS channel region (in the substrate under the gate between S/D regions 350/360) (see, e.g., Verma: figs. 5a-5r and pars.0026/ll.1-6, 0041/ll.10-11, 0049, 0058/ll.8-9, 0082/ll.1-8, 0084, 0095/ll.13-14, and 0128).
Verma is evidence showing that one of ordinary skill in the art would appreciate that a process for forming an isolation dielectric layer comprising oxidating a bottom and a sidewall of a trench and etching and removing part of the isolation dielectric layer at the bottom of the trench would be equivalent to another process equally resulting in forming an isolation dielectric layer filling a trench and substantially absent from the bottom of the trench, and that such differences would result in no unexpected changes in the performance of the device of Duan I. That is, the isolation dielectric layer formation processes of both Duan I and Verma would yield the predictable result of providing suitable methodologies for forming trench-based isolation dielectric layers capable of supporting semi-insulating resistive-field-plate and/or trench gate structures wherein the isolation dielectric layer is substantially absent from the bottom of the trench.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ either a process for forming an isolation dielectric layer comprising oxidating a bottom and a sidewall of a trench and etching and removing part of the isolation dielectric layer at the bottom of the trench, as taught by Verma, or another process equally resulting in forming an isolation dielectric layer filling a trench and substantially absent from the bottom of the trench, as taught by Duan I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable methodologies for forming trench-based isolation dielectric layers capable of supporting semi-insulating resistive-field-plate and/or trench gate structures wherein the isolation dielectric layer is substantially absent from the bottom of the trench. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Verma is evidence showing that one of ordinary skill in the art would appreciate that a top surface of a semi-insulating resistive-field-plate layer being lower than a bottom surface of a MOS channel region would be equivalent to a top surface of a semi-insulating resistive-field-plate layer aligning with a bottom surface of a MOS channel region, and that such differences would result in no unexpected changes in the performance of the device of Duan I. That is, the MOS channel region and semi-insulating resistive-field-plate layer arrangements of both Duan I and Verma would yield the predictable result of providing suitably formed and positioned MOS channel regions and semi-insulating resistive-field-plate layers capable of controlling current flow, reducing electric-field crowding, and enhancing breakdown voltage in a transistor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a top surface of a semi-insulating resistive-field-plate layer lower than a bottom surface of a MOS channel region, as taught by Verma, or a top surface of a semi-insulating resistive-field-plate layer aligned with a bottom surface of a MOS channel region, as taught by Duan I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably formed and positioned MOS channel regions and semi-insulating resistive-field-plate layers capable of controlling current flow, reducing electric-field crowding, and enhancing breakdown voltage in a transistor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
With regards to other language recited in claim 8, see the comments stated above in paragraph 6.
Regarding claim 10, Duan I/Verma (see, e.g., Duan I: fig. 1 and pars.0025-0036 and 0055-0068) shows most aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate according to claim 8 (see paragraphs 11 and 22-28 above), wherein the step of forming the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., see, e.g., pars.0014, 0034, 0052, 0064-0065) comprises:
filling the trench with a semi-insulating polysilicon material (see, e.g., pars.0014, 0031, and 0061)
wherein:
a top surface of the semi-insulating polysilicon material filled in the trench is the top surface of the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014, 0034, 0052, 0064-0065)
Duan I shows most aspects of the instant invention. Furthermore, Duan I (see, e.g., pars.0014, 0029, and 0059) teaches that etching and removal processes may be incorporated into Duan I’s methodology. Furthermore, Duan I (see, e.g., fig. 1) shows that a top surface of Duan I’s resistive-field-plate layer is aligned with a bottom surface of Duan I’s MOS channel region. However, Duan I fails to specify that forming Duan I’s semi-insulating resistive-field-plate layer comprises etching and removing a part of the semi-insulating polysilicon material filled in the trench so that a top surface of the remaining polysilicon material filled in the trench is below the bottom surface of the MOS channel region. Furthermore, Duan I fails to specify that a top surface of remaining semi-insulating resistive-field-plate layer filled in the trench is lower than a bottom surface of Duan I’s MOS channel region.
Verma, in the same field of endeavor and in a similar device to Duan I, teaches a methodology for forming a semi-insulating resistive-field-plate layer structure 140b in a trench 564/568 comprising: filling the trench with a semi-insulating polysilicon material 140, etching and removing a part of the semi-insulating polysilicon material filled in the trench so that a top surface of remaining semi-insulating polysilicon material (i.e., top of 140b) filled in the trench is below the bottom surface of a MOS channel region (in the substrate under the gate between S/D regions 350/360), wherein the top surface of the remaining semi-insulating polysilicon material (i.e., top of 140b) filled in the trench is the top surface of the semi-insulating resistive-field-plate layer 140b (see, e.g., Verma: figs. 5a-5r and pars.0026/ll.1-6, 0041/ll.10-11, 0049, 0058/ll.8-9, 0095/ll.9-11, 0095/ll.13-14, 0096/ll.5-6, and 0128).
Verma is evidence showing that one of ordinary skill in the art would appreciate that forming a resistive-field-plate layer by etching and removing a part of semi-insulating polysilicon material filled in the trench so that a top surface of remaining semi-insulating polysilicon material filled in the trench is below the bottom surface of a MOS channel region and such that the top surface of the remaining semi-insulating polysilicon material filled in the trench is the top surface of the semi-insulating resistive-field-plate layer would be equivalent to forming a resistive-field-plate layer by another methodology such that a top surface of the semi-insulating polysilicon material filled in a trench is aligned with the bottom surface of a MOS channel region and the top surface of semi-insulating polysilicon filled in the trench is the top surface of a semi-insulating resistive-field-plate layer, and that such differences would result in no unexpected changes in the performance of the device of Duan I. That is, the MOS channel region and semi-insulating resistive-field-plate layer formations and arrangements of both Duan I and Verma would yield the predictable result of providing suitably formed and positioned MOS channel regions and semi-insulating resistive-field-plate layers capable of controlling current flow, reducing electric-field crowding, and enhancing breakdown voltage in a transistor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ either forming a resistive-field-plate layer by etching and removing a part of semi-insulating polysilicon material filled in the trench so that a top surface of remaining semi-insulating polysilicon material filled in the trench is below the bottom surface of a MOS channel region and such that the top surface of the remaining semi-insulating polysilicon material filled in the trench is the top surface of the semi-insulating resistive-field-plate layer, as taught by Verma, or forming a resistive-field-plate layer by another methodology such that a top surface of the semi-insulating polysilicon material filled in a trench is aligned with the bottom surface of a MOS channel region and the top surface of the semi-insulating polysilicon filled in the trench is the top surface of a semi-insulating resistive-field-plate layer, as taught by Duan I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably formed and positioned MOS channel regions and semi-insulating resistive-field-plate layers capable of controlling current flow, reducing electric-field crowding, and enhancing breakdown voltage in a transistor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
With regards to other language recited in claim 10, see the comments stated above in paragraphs 6-8.
Regarding claim 11, Duan I/Verma (see, e.g., Duan I: fig. 1 and pars.0025-0036 and 0055-0068) shows most aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate according to claim 8 (see paragraphs 11 and 22-28 above), wherein the step of forming the first trench gate layer (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014, 0034, 0052, 0064-0065) over the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014, 0034, 0052, 0064-0065) comprises:
filling a first doped polysilicon material in the trench over the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., see, e.g., pars.0014, 0034, 0052, 0064-0065) wherein the first doped polysilicon material at least covers the top surface of the semi-insulating resistive-field-plate layer (see, e.g., pars.0014, 0034, 0051, and 0064-0065)
Duan I shows most aspects of the instant invention. Furthermore, Duan I (see, e.g., pars.0014, 0029, 0034, 0051, 0059, and 0064-0065) teaches that etching and removal processes may be incorporated into Duan I’s methodology and that Duan I’s first trench gate layer comprises a first doped polysilicon material. However, Duan I fails to specify that the polysilicon material is etched to form the first trench gate layer. Verma, in the same field of endeavor and in a similar device to Duan I, teaches a methodology for forming a polysilicon first trench gate layer 140a over and covering a top surface of a polysilicon semi-insulating resistive-field-plate layer 140b in a trench 564/568, wherein polysilicon material 140 filled in the trench over semi-insulating resistive-field--plate layer is etched to form the first trench gate layer 140a (see, e.g., Verma: figs. 5a-5r and pars.0026/ll.1-6, 0041/ll.10-11, 0049, 0095/ll.9-11, 0095/ll.13-14, 0096/ll.5-6, and 0128).
Verma is evidence showing that one of ordinary skill in the art would appreciate that etching polysilicon material to form a first trench gate layer would be equivalent to a trench gate layer formed by another methodology, and that such differences would result in no unexpected changes in the performance of the device of Duan I. That is, the trench gate layer formation processes of both Duan I and Verma would yield the predictable result of suitably creating functional trench gate layers positioned in a trench above semi-insulating polysilicon resistive-field-plate layers and capable of interaction and integration with gate-focused elements (e.g., electrodes) in transistor/MOS devices.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ either etching polysilicon material to form a first trench gate layer, as taught by Verma, or forming a trench gate layer through another methodology, as taught by Duan I, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of suitably creating functional trench gate layers positioned in a trench above semi-insulating polysilicon resistive-field-plate layers and capable of interaction and integration with gate-focused elements (e.g., electrodes) in transistor/MOS devices. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
With regards to other language recited in claim 11, see the comments stated above in paragraphs 6-8.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Duan II in view of Ng and Disney.
Regarding claim 7, Duan II (see, e.g., fig. 1 and pars.0026-0037 and 0057-0069) shows most aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate according to claim 6 (see paragraph 13 above), wherein the step of forming the MOS channel region 9, the MOS source region 11, and the MOS channel contact region 10 within the top portion of the epitaxial layer 8 (see, e.g., pars.0029, 0034, 0046-0047, 0052, 0059, and 0064) comprises:
forming the MOS channel region 9 within the top portion of the epitaxial layer by a first ion implantation or a first ion diffusion (see, e.g., pars.0029 and 0058-0059);
forming the MOS source region 11 disposed over the MOS channel region by a second ion implantation (see, e.g., pars.0034, 0052, and 0064); and
forming the MOS channel contact region 10 by a third ion implantation (see, e.g., pars.0034, 0052, and 0064), wherein the MOS channel contact region is in contact with the MOS channel region
Regarding claim 7, Duan II shows most aspects of the instant invention. Furthermore, Duan II (see, e.g., pars.0008, 0029, 0046-0047, and 0058-0059) teaches that Duan II’s MOS channel region is a doped region of Duan II’s epitaxial layer and that Duan II’s MOS channel region may be formed by a first ion implantation or a first ion diffusion. However, Duan II fails to explicitly specify that Duan II’s MOS channel region may be formed by a first ion implantation and a first ion diffusion. Ng, in the same field of endeavor and in a similar device to Duan II, teaches that conventional processes for forming channel layers including both a first ion implantation and a first ion diffusion (see, e.g., Ng: par.0046/ll.1-2). Furthermore, Disney, also in the same field of endeavor and in a similar device to Duan II, teaches that performing a first ion diffusion after a first ion implantation step can aid in smoothing out the lateral doping profile of doped regions in a semiconductor transistor device (see, e.g., Disney: par.0043/ll.19-24).
Ng and Disney are evidence showing that one of ordinary skill in the art would appreciate that a MOS channel region formed by a first ion implantation and a first ion diffusion would be equivalent to a MOS channel region formed by a first ion implantation or a first ion diffusion, and that such differences would result in no unexpected changes in the performance of the device of Duan II. That is, the MOS channel region formation methods of both Ng or Disney and Duan II would yield the predictable result of providing a suitable methodology for forming appropriate channel regions capable of supporting other conductivity-type structures in a transistor/MOS device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a MOS channel region formed by a first ion implantation and a first ion diffusion, as taught by Ng and Disney, or a MOS channel region formed by a first ion implantation or a first ion diffusion, as taught by Duan II, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable methodology for forming appropriate channel regions capable of supporting other conductivity-type structures in a transistor/MOS device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Disney is evidence that at the time of filing the invention one of ordinary skill in the art would find particular incentive to have a MOS channel region formed by a first ion implantation and a first ion diffusion, as taught by Disney, so as employ a process facilitating smoothing out the lateral doping profile of a doped channel region in a semiconductor transistor device.
Claims 8 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Duan II in view of Verma.
Regarding claim 8, Duan II (see, e.g., fig. 1 and pars.0026-0037 and 0057-0069) shows most aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate according to claim 6 (see paragraph 13 above), wherein the step of sequentially forming the semi-insulating resistive-field-plate structure 2/(regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) and the trench gate structure 2/4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) in the trench along the bottom-to-top direction of the trench comprises:
forming an isolation dielectric layer 2 on a sidewall of the trench (see, e.g., pars.0031 and 0061);
filling the trench (see, e.g., pars.0032 and 0062) to form a semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066), wherein the semi-insulating resistive field-layer-plate layer has a top surface and the MOS channel region 9 has a bottom surface;
forming a first trench gate layer 4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) over the semi-insulating resistive-field-plate layer and electrically connected to the semi-insulating resistive-field-plate layer (see, e.g., pars.0014-0015, 0031-0032, 0035, 0061-0062, and 0065);
wherein:
the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) and the isolation dielectric layer 2 constitute the semi-insulating resistive-field plate structure 2/(regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066), and the first trench gate layer 4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) and the isolation dielectric layer constitute the trench gate structure 2/4 and/or (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066)
Regarding claim 8, Duan II shows most aspects of the instant invention. Duan II (see, e.g., fig. 1) further shows that Duan II’s semi-insulating resistive-field-plate layer directly contacts both Duan II’s isolation dielectric layer and substrate. However, Duan II fails to specify that forming Duan II’s isolation dielectric layer comprises oxidating a bottom and a sidewall of the trench and etching and removing part of the isolation dielectric layer at the bottom of the trench. Furthermore, Duan II (see, e.g., fig. 1) shows that a top surface of Duan II’s resistive-field-plate layer is aligned with a bottom surface of Duan II’s MOS channel region, and fails to specify that a top surface of the semi-insulating resistive-field-plate layer is lower than a bottom surface of Duan II’s MOS channel region. Verma, in the same field of endeavor and in a similar device to Duan II, teaches a methodology for sequentially forming a semi-insulating resistive-field-plate structure 132/140b and a trench gate structure 132/140a along a bottom-to-top direction of a trench 564/568, wherein forming an isolation dielectric layer 132 comprises oxidating a bottom and a sidewall of the trench and etching and removing part of the isolation dielectric layer at the bottom of the trench, and wherein the trench is filled to form a semi-insulating resistive-field-plate layer 140b, whereby a top surface of the semi-insulating resistive-field-plate layer is lower than a bottom surface of an MOS channel region (in the substrate under the gate between S/D regions 350/360) (see, e.g., Verma: figs. 5a-5r and pars.0026/ll.1-6, 0041/ll.10-11, 0049, 0058/ll.8-9, 0082/ll.1-8, 0084, 0095/ll.13-14, and 0128).
Verma is evidence showing that one of ordinary skill in the art would appreciate that a process for forming an isolation dielectric layer comprising oxidating a bottom and a sidewall of a trench and etching and removing part of the isolation dielectric layer at the bottom of the trench would be equivalent to another process equally resulting in forming an isolation dielectric layer filling a trench and substantially absent from the bottom of the trench, and that such differences would result in no unexpected changes in the performance of the device of Duan II. That is, the isolation dielectric layer formation processes of both Duan II and Verma would yield the predictable result of providing suitable methodologies for forming trench-based isolation dielectric layers capable of supporting semi-insulating resistive-field-plate and/or trench gate structures wherein the isolation dielectric layer is substantially absent from the bottom of the trench.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ either a process for forming an isolation dielectric layer comprising oxidating a bottom and a sidewall of a trench and etching and removing part of the isolation dielectric layer at the bottom of the trench, as taught by Verma, or another process equally resulting in forming an isolation dielectric layer filling a trench and substantially absent from the bottom of the trench, as taught by Duan II, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitable methodologies for forming trench-based isolation dielectric layers capable of supporting semi-insulating resistive-field-plate and/or trench gate structures wherein the isolation dielectric layer is substantially absent from the bottom of the trench. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Furthermore, Verma is evidence showing that one of ordinary skill in the art would appreciate that a top surface of a semi-insulating resistive-field-plate layer being lower than a bottom surface of a MOS channel region would be equivalent to a top surface of a semi-insulating resistive-field-plate layer aligning with a bottom surface of a MOS channel region, and that such differences would result in no unexpected changes in the performance of the device of Duan II. That is, the MOS channel region and semi-insulating resistive-field-plate layer arrangements of both Duan II and Verma would yield the predictable result of providing suitably formed and positioned MOS channel regions and semi-insulating resistive-field-plate layers capable of controlling current flow, reducing electric-field crowding, and enhancing breakdown voltage in a transistor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a top surface of a semi-insulating resistive-field-plate layer lower than a bottom surface of a MOS channel region, as taught by Verma, or a top surface of a semi-insulating resistive-field-plate layer aligned with a bottom surface of a MOS channel region, as taught by Duan II, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably formed and positioned MOS channel regions and semi-insulating resistive-field-plate layers capable of controlling current flow, reducing electric-field crowding, and enhancing breakdown voltage in a transistor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
With regards to other language recited in claim 8, see the comments stated above in paragraph 6.
Regarding claim 10, Duan II/Verma (see, e.g., Duan II: fig. 1 and pars.0026-0037 and 0057-0069) shows most aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate according to claim 8 (see paragraphs 13 and 47-53 above), wherein the step of forming the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) comprises:
filling the trench with a semi-insulating polysilicon material (see, e.g., pars.0016, 0032, and 0062)
wherein:
a top surface of the semi-insulating polysilicon material filled in the trench is the top surface of the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066)
Duan II shows most aspects of the instant invention. Furthermore, Duan II (see, e.g., pars.0014, 0030, and 0060) teaches that etching and removal processes may be incorporated into Duan II’s methodology. Furthermore, Duan II (see, e.g., fig. 1) shows that a top surface of Duan II’s resistive-field-plate layer is aligned with a bottom surface of Duan II’s MOS channel region. However, Duan II fails to specify that forming Duan II’s semi-insulating resistive-field-plate layer comprises etching and removing a part of the semi-insulating polysilicon material filled in the trench, so that a top surface of the remaining polysilicon material filled in the trench is below the bottom surface of the MOS channel region. Furthermore, Duan II fails to specify that a top surface of remaining semi-insulating resistive-field-plate layer filled in the trench is lower than a bottom surface of Duan II’s MOS channel region.
Verma, in the same field of endeavor and in a similar device to Duan II, teaches a methodology for forming a semi-insulating resistive-field-plate layer structure 140b in a trench 564/568 comprising: filling the trench with a semi-insulating polysilicon material 140, etching and removing a part of the semi-insulating polysilicon material filled in the trench so that a top surface of remaining semi-insulating polysilicon material (i.e., top of 140b) filled in the trench is below the bottom surface of a MOS channel region (in the substrate under the gate between S/D regions 350/360), wherein the top surface of the remaining semi-insulating polysilicon material (i.e., top of 140b) filled in the trench is the top surface of the semi-insulating resistive-field-plate layer 140b (see, e.g., Verma: figs. 5a-5r and pars.0026/ll.1-6, 0041/ll.10-11, 0049, 0058/ll.8-9, 0095/ll.9-11, 0095/ll.13-14, 0096/ll.5-6, and 0128).
Verma is evidence showing that one of ordinary skill in the art would appreciate that forming a resistive-field-plate layer by etching and removing a part of semi-insulating polysilicon material filled in the trench so that a top surface of remaining semi-insulating polysilicon material filled in the trench is below the bottom surface of a MOS channel region and such that the top surface of the remaining semi-insulating polysilicon material filled in the trench is the top surface of the semi-insulating resistive-field-plate layer would be equivalent to forming a resistive-field-plate layer by another methodology such that a top surface of the semi-insulating polysilicon material filled in a trench is aligned with the bottom surface of a MOS channel region and the top surface of semi-insulating polysilicon filled in the trench is the top surface of a semi-insulating resistive-field-plate layer, and that such differences would result in no unexpected changes in the performance of the device of Duan II. That is, the MOS channel region and semi-insulating resistive-field-plate layer formations and arrangements of both Duan II and Verma would yield the predictable result of providing suitably formed and positioned MOS channel regions and semi-insulating resistive-field-plate layers capable of controlling current flow, reducing electric-field crowding, and enhancing breakdown voltage in a transistor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ either forming a resistive-field-plate layer by etching and removing a part of semi-insulating polysilicon material filled in the trench so that a top surface of remaining semi-insulating polysilicon material filled in the trench is below the bottom surface of a MOS channel region and such that the top surface of the remaining semi-insulating polysilicon material filled in the trench is the top surface of the semi-insulating resistive-field-plate layer, as taught by Verma, or forming a resistive-field-plate layer by another methodology such that a top surface of the semi-insulating polysilicon material filled in a trench is aligned with the bottom surface of a MOS channel region and the top surface of the semi-insulating polysilicon filled in the trench is the top surface of a semi-insulating resistive-field-plate layer, as taught by Duan II, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing suitably formed and positioned MOS channel regions and semi-insulating resistive-field-plate layers capable of controlling current flow, reducing electric-field crowding, and enhancing breakdown voltage in a transistor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
With regards to other language recited in claim 10, see the comments stated above in paragraphs 6-8.
Regarding claim 11, Duan II/Verma (see, e.g., Duan II: fig. 1 and pars.0026-0037 and 0057-0069) shows most aspects of the instant invention, including a preparation method of a shared-dielectric MOSFET device with a resistive-field-plate according to claim 8 (see paragraphs 13 and 47-53 above), wherein the step of forming the first trench gate layer (heavily doped regions of 3 longitudinally corresponding to 9 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) over the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066) comprises:
filling a first doped polysilicon material in the trench over the semi-insulating resistive-field-plate layer (regions of 3 longitudinally corresponding to 8 – see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066), wherein the first doped polysilicon material at least covers the top surface of the semi-insulating resistive-field-plate layer (see, e.g., pars.0014-0016, 0035, 0052, and 0065-0066)
Duan II shows most aspects of the instant invention. Furthermore, Duan II (see, e.g., pars.0014-0016, 0030, 0035, 0052, 0060, and 0065-0066) teaches that etching and removal processes may be incorporated into Duan II’s methodology and that Duan II’s first trench gate layer comprises a first doped polysilicon material. However, Duan II fails to specify that the polysilicon material is etched to form the first trench gate layer. Verma, in the same field of endeavor and in a similar device to Duan II, teaches a methodology for forming a polysilicon first trench gate layer 140a over and covering a top surface of a polysilicon semi-insulating resistive-field-plate layer 140b in a trench 564/568, wherein polysilicon material 140 filled in the trench over semi-insulating resistive-field--plate layer is etched to form the first trench gate layer 140a (see, e.g., Verma: figs. 5a-5r and pars.0026/ll.1-6, 0041/ll.10-11, 0049, 0095/ll.9-11, 0095/ll.13-14, 0096/ll.5-6, and 0128).
Verma is evidence showing that one of ordinary skill in the art would appreciate that etching polysilicon material to form a first trench gate layer would be equivalent to a trench gate layer formed by another methodology, and that such differences would result in no unexpected changes in the performance of the device of Duan II. That is, the trench gate layer formation processes of both Duan II and Verma would yield the predictable result of suitably creating functional trench gate layers positioned in a trench above semi-insulating polysilicon resistive-field-plate layers and capable of interaction and integration with gate-focused elements (e.g., electrodes) in transistor/MOS devices.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to employ either etching polysilicon material to form a first trench gate layer, as taught by Verma, or forming a trench gate layer through another methodology, as taught by Duan II, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of suitably creating functional trench gate layers positioned in a trench above semi-insulating polysilicon resistive-field-plate layers and capable of interaction and integration with gate-focused elements (e.g., electrodes) in transistor/MOS devices. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
With regards to other language recited in claim 11, see the comments stated above in paragraphs 6-8.
Conclusion
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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