Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 18, 2023, and July 2, 2023, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
Claims 4, 6, 7 are objected to under 37 CFR 1.75(c) as being in improper form because a multiple dependent claim cannot depend from a multiple dependent claim. See MPEP § 608.01(n). Accordingly, the claims 4, 6 and 7 will be treated as per the earlier amended claims filed on 5/18/2023 which corrected this problem.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 7 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable over Jung et al.(2021/0407897)
Regarding claim 1 Jung et al. discloses a multilayer substrate(fig 3), wherein the multilayer substrate includes a core layer(fig 3, 111) and a build-up layer(fig 3, 113), the build-up layer is stacked on one surface of the core layer and constitutes a first surface of the multilayer substrate, the multilayer substrate is provided with a via conductor that penetrates through the core layer and the build-up layer in a thickness direction(fig 3, V5a, V7, the via conductor includes a filled via and a conformal via electrically connected to the filled via, and at least part of the filled via overlaps the conformal via when viewed in the thickness direction and the filled via is positioned towards the first surface relative to the conformal via(fig 3).
Regarding claim 2 Jung et al. discloses wherein the conformal via(fig 3, V5a) penetrates through at least part of the core layer(fig 3, 111) and the filled via(fig 3, V7) penetrates through the build-up layer(fig 3, 111).
Regarding claim 7 Jung et al. discloses wherein the filled via includes a conductor that fills a via hole provided in part of an insulator of the multilayer substrate and the filled via is oriented with a part along a bottom of the via hole positioned towards the conformal via, and the conformal via includes a conductor located along a side and a bottom of a via hole provided in another part of the insulator, and the conformal via is oriented with a part along the bottom positioned towards the filled via(fig 3, para 0049, 0051).
Claims 1, 7 are rejected under 35 U.S.C. 102(a)(2) as being unpatentable over Ito (JP 2004265967 A)
Regarding Claim 1 – Ito teaches a printed wiring board (Fig 1c) comprising: a multilayer substrate (Fig 1c; 200; Ito states “multilayer printed wiring board 200”), wherein the multilayer substrate includes a core layer (Fig 6g; 40 including resin layer 11; Ito states “a double-sided wiring board 40 in which the first wiring layer 21a, the second wiring layer 22a… are formed on both surfaces of the insulating resin layer 11 is obtained”) and a build-up layer (Fig 1c; 50 or 60; Ito states “double-sided wiring board 40, the buildup layer 50… and the buildup layer 60 are formed symmetrically with respect to the insulating resin layer 11”), the build-up layer is stacked on one surface of the core layer and constitutes a first surface of the multilayer substrate (Fig 1c, 50; Ito states “the build-up layer 50 in which the third wiring layer 24a and the conformal via 33 are formed on one side”), the multilayer substrate is provided with a via conductor that penetrates through the core layer and the build-up layer in a thickness direction (Fig 1c; 33, 34; Ito states “The third wiring layer 24a is electrically connected by a conformal via 33, and the second wiring layer 22a and the fourth wiring layer 25a are electrically connected by a filled via 34”; see also Fig 3d; 31; Ito states “The filled via 31 is formed in the conductor layer 22 and the via hole 41”; Fig 4h; Ito states “via hole 42 is formed at a predetermined position of the insulating resin layer 12 by laser processing or the like”; Fig 4j; Ito states “conformal via 32 is formed in the conductor layer 23 and the via hole 42”), the via conductor includes a filled via and a conformal via electrically connected to the filled via (Fig 1c; 33, 34; Ito states “The third wiring layer 24a is electrically connected by a conformal via 33, and the second wiring layer 22a and the fourth wiring layer 25a are electrically connected by a filled via 34” 33 and 34 (via 31) form one continuous stacked via conductor through the core and build-up, thus the conformal via is electrically connected to the filled via), and at least part of the filled via overlaps the conformal via when viewed in the thickness direction and the filled via is positioned towards the first surface relative to the conformal via (Fig 1c shows 33 and 34 stacked in the thickness direction; Ito states “the build-up layer 50… on one side” and “built-up layer 60 in which filled vias 34 are formed”; first surface corresponding to the outer surface carrying filled via 34 (build-up layer 60)).
Regarding Claim 7 – Ito teaches the printed wiring board according to claim 1, wherein the filled via includes a conductor that fills a via hole provided in part of an insulator of the multilayer substrate and the filled via is oriented with a part along a bottom of the via hole positioned towards the conformal via (Fig 3b; Ito states “laser-processed to form a via hole 41” in “the insulating resin layer 11”; Fig 3d; Ito states “filled via 31 is formed in the conductor layer 22 and the via hole 41”; Figs 6h-6j; Ito states “Via holes 43 and via holes 44 are formed” and “conformal via 33 is formed in the conductor layer 24 and via hole 43 having a thickness of 10 to 15 μm, and the filled via 34 is formed in the conductor layer 25 and via hole 44 having a thickness of 10 to 15 μm”; In Fig 1c, filled vias 31 and 34 are shown as conductors filling the via holes in the insulating resin layers so that the bottom portions of the filled vias face toward the opposed conformal vias across the insulating resin layer 11), and the conformal via includes a conductor located along a side and a bottom of a via hole provided in another part of the insulator, and the conformal via is oriented with a part along the bottom positioned towards the filled via (Fig 4h; Ito states “via hole 42 is formed at a predetermined position of the insulating resin layer 12 by laser processing or the like”; Fig 4j; Ito states “conformal via 32 is formed in the conductor layer 23 and the via hole 42”; Fig 6j; Ito states “conformal via 33 is formed in the conductor layer 24 and via hole 43 having a thickness of 10 to 15 μm”; in Figs 4j and 6j, the conformal vias 32 and 33 are shown as plated conductors lining the sidewalls and bottom of the vias holes, and in Fig 1c, the bottoms of the conformal vias are oriented toward the filled vias across the insulating resin layer 11 in Ito’s symmetrical stack).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (JP 2004265967 A)
Regarding Claim 2 – Ito teaches the printed wiring board according to claim 1, wherein the conformal via penetrates through at least part of the core layer (Fig 1b; Ito states “with an insulating resin layer 11 interposed therebetween… the conformal via 31a are formed” and “the first wiring layer 21a… the second wiring layer 22a are electrically connected by a conformal via 31a” with 21a/22a on opposite sides of layer 11 (the internal layer)) and the filled via penetrates through the build-up layer (Fig 1c; Ito states “the first wiring layer 21a is composed of a fourth wiring layer 25a, lands 25b, and a built-up layer 60 in which filled vias 34 are formed”; and Fig 6j; Ito states “the filled via 34 is formed in the conductor layer 25 and via hole 44… on the insulating resin layer 14”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the printed wiring board according to claim 1, wherein the conformal via penetrates through at least part of the core layer of Ito with the filled via penetrates through the build-up layer as taught by another embodiment of Ito because Ito states “a four-layer printed wiring board structure having a symmetrical structure in which the buildup layer 50 and the buildup layer 60 are formed symmetrically with respect to the insulating resin layer 11 is formed” and “repeating the insulating resin layer, wiring layer, and conformal via or filled via forming step as many times as necessary”.
Regarding Claim 3 – Ito teaches the printed wiring board according to claim 1, wherein a width of the filled via is equal to a width of the conformal via when viewed in the thickness direction (Ito teaches both filled and conformal vias are formed in laser processed via holes and plated in the same build-up flow; Fig 3b; Ito states “laser-processed to form a via hole 41” in “the insulating resin layer 11”; Fig 3d; Ito states “The filled via 31 is formed in the conductor layer 22 and the via hole 41”; Fig 4h; Ito states “a via hole 42 is formed at a predetermined position of the insulating resin layer 12 by laser processing or the like”; Fig 4j; Ito states “conformal via 32 is formed in the conductor layer 23 and the via hole 42”; Fig 6j; Ito states “conformal via 33 is formed in the conductor layer 24 and via hole 43 having a thickness of 10 to 15 μm, and the filled via 34 is formed in the conductor layer 25 and via hole 44 having a thickness of 10 to 15 μm”; see also Fig 1c; Ito states “a four-layer printed wiring board structure having a symmetrical structure in which the buildup layer 50 and the buildup layer 60 are formed symmetrically with respect to the insulating resin layer 11 is formed”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided a width of the filled via is equal to a width of the conformal via when viewed in the thickness direction in Ito’s printed wiring board according to claim 1 to ensure alignment/stacking tolerance given Ito’s symmetrical architecture and the fact that both vias are formed by identical laser plating to the same thickness (10 to 15 μm).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (JP 2004265967 A) in view of Inagaki et al. (US 20060244134 A1)
Regarding Claim 4 – Ito teaches the printed wiring board according to claim 1, but fails to disclose wherein the multilayer substrate includes a through hole that penetrates through the multilayer substrate in the thickness direction and a through-hole conductor is provided on an inner wall of the through hole, the build-up layer includes a surface layer conductor constituting part of the first surface, the surface layer conductor is electrically connected to the through-hole conductor, and when a thickness of the through-hole conductor is t1 and a thickness of the surface layer conductor is t2, t1/t2 is greater than or equal to 0.7 and less than or equal to 1.0.
Inagaki teaches the multilayer substrate includes a through hole (Fig 2C; 36α) that penetrates through the multilayer substrate (Fig 1A; 30) in the thickness direction (Figs 2C-2E, 20A; Inagaki [0134] states “Pass-through holes 36α for through holes… are formed to penetrate the front and rear surfaces of the substrate”; Inagaki [0296] states “A through hole passage 36 was made by drilling this multilayer core substrate 30”) and a through-hole conductor is provided on an inner wall of the through hole (Figs 2D-2E; Inagaki [0135] states “form plated films 22 in the respective pass-through holes 36α for the through holes and roughen the surfaces of the plated films 22”; Inagaki [0144] states “the land surfaces and inner walls of the through holes 36 are subjected to etching”), the build-up layer includes a surface layer conductor constituting part of the first surface (Figs 5-9; Inagaki [0120] states “Interlayer resin insulating layers 50 on which via holes 60 and conductor circuits 58 are formed… are arranged on the conductor layers 34P and 34E on the surfaces”; Inagaki [0158] states “solder resist composition 70 is coated on each surface… forming opening portions 71”; Inagaki [0160] states “external terminals are formed by conducting reflow” at the surface pads exposed by 71), the surface layer conductor is electrically connected to the through-hole conductor (Figs 3A-3B, 20A; Inagaki [0138] states “Cover plated members 25 may be formed right on the through holes 36… Thereafter, outer layer conductor circuits 34, 34P and 34E are formed”; Inagaki [0301] states “the land surface of the through hole 36 were etched”), and when a thickness of the through-hole conductor is t1 and a thickness of the surface layer conductor is t2, t1/t2 is greater than or equal to 0.7 and less than or equal to 1.0 (t1 (copper plating on the inner wall); Inagaki [0136] states “thicknesses of the plated metals are preferably 5 to 30 μm”; t2 (surface-layer conductor); Inagaki [0138] states “thickness of the conductive layer on the multilayer core substrate is 15 μm”; Inagaki [0156] states “the upper conductor circuits 58… thickness of 20 μm”; Inagaki [0299] states “copper thickness on the front and rear surfaces… set to 25 μm”; these disclosed ranges overlap so that person skilled in the art would select values with t1/t2 within 0.7-1.0 (e.g. 15/20, 20/20, 20/25)).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the device of Ito with the multilayer substrate includes a through hole that penetrates through the multilayer substrate in the thickness direction and a through-hole conductor is provided on an inner wall of the through hole, the build-up layer includes a surface layer conductor constituting part of the first surface, the surface layer conductor is electrically connected to the through-hole conductor, and when a thickness of the through-hole conductor is t1 and a thickness of the surface layer conductor is t2, t1/t2 is greater than or equal to 0.7 and less than or equal to 1.0 as taught by Inagaki to reduce voltage drop and ensure reliable startup because Inagaki [0286] states “the voltage drop… operation decreases so that shortage of power becomes unlikely to occur… even if the IC chip… is mounted, malfunction… is not induced”.
Regarding Claim 5 – Ito in view of Inagaki teaches the printed wiring board according to claim 4, wherein the surface layer conductor is electrically connected to the via conductor (Figs 5B-5D, 6B-6C; Inagaki [0120] quoted above; Inagaki [0150] states “electroless copper… formed on the entire roughened surfaces… including the inner walls of the via hole openings 50a”; Inagaki [0155] states “thus forming independent conductor circuits 58 and via holes 60”).
Regarding Claim 6 – Ito in view of Inagaki teaches the printed wiring board according to claim 4, wherein the build-up layer has a higher volume percentage of conductor than the core layer (Figs 5-7, 8, 18-21; Inagaki [0124] discloses build-up/interlayer resin film “thickness of 50 μm” with upper conductor circuits 58 [0156] “formed to have a thickness of 20 μm” yielding ~ 20/50= 40% metal fraction in the build-up; For the core Inagaki [0292] discloses an insulation substrate “0.6 mm thick” with surface copper on each side [0299] “set to 25 μm” yielding ~ (25+25)/600= 8% metal fraction in the core. Thus, the build-up layer’s conductor volume percentage is higher than that of the core layer; see also Inagaki [0285] noting conductor volume increases with thicker conductors).
Conclusion
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/ADITYA SHARMA/ Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/ Supervisory Patent Examiner, Art Unit 2847