DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s argument, see Remark, filed 12/15/2025, with respect to the amended limitation “the air gap is in direct contact with the source/drain doped layer” have been fully considered and are persuasive. The 35 USC 102 and 103 rejections of the claims have been withdrawn. However, upon further consideration, a new ground of rejection is made incorporating US 20240194764 A1 Wang et al.
Applicant's arguments filed 12/15/2025 have been fully considered but they are not persuasive. Applicant argues Tak does not teach “an oxide layer is formed between the first gate dielectric layer formed on the bottom surface of the first metal gate and a top semiconductor layer of the plurality of semiconductor layers”. The Examiner respectfully disagrees although it is not illustrated, this limitation is explicitly disclosed in paragraph 0081 as an “interfacial layer” wherein “The interfacial layer may cure an interface defect between the upper surface 104 of the plurality of fin type active areas FA and surfaces of the plurality of nanosheets N1, N2, and N3 and the high dielectric layer” in combination with layer 145 (comprising the high dielectric layer and the interfacial layer) illustrated in fig. 1B, See below for full rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 20170110554 A1 Tak et al hereafter “Tak, and further in view of US 20240194764 A1 Wang et al hereafter “Wang”
Claim 1 Tak teaches A fabrication method of a semiconductor structure, comprising:
forming a plurality of semiconductor layers (NSS fig. 1B on a substrate (comprising 102 fig. 1B) along a vertical direction (Z fig. 1B) with respect to the substrate [sufficiently illustrated fig. 1B];
forming a gate structure (comprising at least 150, 145, and 104 fig. 1B) around the plurality of semiconductor layers, wherein:
the gate structure includes a first metal gate (150M fig. 1B) and a plurality of second metal gates (150S fig. 1B) [sufficiently disclosed as comprising “metal” Paragraph 0082],
the first metal gate is formed over the plurality of semiconductor layers along the vertical direction [sufficiently illustrated fig. 1B], one of the plurality of second metal gates is formed between a bottom semiconductor layer of the plurality of semiconductor layers and the substrate [sufficiently illustrated fig. 1B], and each of other second metal gates of the plurality of second metal gates is formed between adjacent semiconductor layers, [sufficiently illustrated fig. 1B],
the gate structure further includes a first gate dielectric layer (“the High dielectric layer” of 145 contacting 150M and N3 fig. 1B, Sufficiently Disclosed paragraph 0081) formed on sidewalls and a bottom surface of the first metal gate [sufficiently illustrated fig. 1B], and a second gate dielectric layer [“the High dielectric layer” of 145 contacting 150S and N2 and/or N1 fig. 1B, sufficiently disclosed paragraph 0081] formed around each of the plurality of second metal gates, and
an oxide layer [“the interfacial layer” of 145 contacting 150M and N3, sufficiently disclosed paragraph 0081 which further discloses it as “ a silicon oxide layer, a silicon oxynitride layer, or a combination thereof”] is formed between the first gate dielectric layer formed on the bottom surface of the first metal gate and a top semiconductor layer (N3 fig. 1B, disclosed paragraph 0081) of the plurality of semiconductor layers [“The interfacial layer may cure an interface defect between the upper surface 104 of the plurality of fin type active areas FA and surfaces of the plurality of nanosheets N1, N2, and N3 and the high dielectric layer” paragraph 0081].
forming a recess (the recess filled with 140 and 104 fig. 1B) on each side (at least an +X and a -X side) of the second gate dielectric layer along a direction (X fig. 1B) parallel to the substrate [best illustrated fig. 1B];
forming an isolation layer (140 fig. 1B) inside the recess, the isolation layer being formed at least on the second gate dielectric layer [best illustrated fig. 1B met under broadest reasonable interpretation wherein “On” is used as “a function word to indicate position in close proximity with” and/or “a function word to indicate position in or in contact with an outer surface” [Merriam-Webster]]; and
forming a source/drain doped layer (162 fig. 1B, sufficiently disclosed as at least Silicon doped with Ge paragraph 0084 “SiGe” under broadest reasonable interpretation) on two sides of the plurality of semiconductor layers and the gate structure along the direction parallel to the substrate [best illustrated fig. 1B], wherein the source/drain doped layer and the isolation layer enclose an air gap [embodiments is sufficiently disclosed AS1 fig. 16B and AS2 fig. 16D].
a step of removing (illustrated Fig. 22) an oxide layer (D152 labeled fig. 20) formed between a bottom surface of a dummy gate (D154 labeled fig. 20) and a top semiconductor layer of the plurality of semiconductor layers;
Tak does not teach an embodiment wherein the air gap is in direct contact with the source/drain doped layer.
Wang teaches a source/drain layer (50 fig. 2B) and an isolation layer (comprising 33 and 35 fig. 2B) enclosing an air gap (37 fig. 2B) wherein the air gap is in direct contact with the source/drain doped layer [sufficiently illustrated fig. 2B].
It would be obvious to one of ordinary skill in the art to substitute the airgap and insulation layer structure Tak teaches with the airgap and insulation structure Wang teaches such that “the air gap is in direct contact with the source/drain doped layer” to achieve the overall effective dielectric constant of an interspacer structure that Wang teaches [disclosed Paragraph 0026] and/or substituting equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case a spacer and/or an isolating structure adjacent to a gate.
Claim 2 Tak in view of Wang teach as shown above the method according to claim 1, wherein forming the plurality of semiconductor layers includes:
providing the substrate [sufficiently illustrated fig. 1B]; and
forming a fin (FA fig. 1B) protruding from the substrate [sufficiently illustrated fig. 1B], wherein:
the fin includes a plurality of stacked structures (comprising at least NSS fig. 1B ) which are stacked over each other along the vertical direction [sufficiently illustrated fig. 1B]; and
each stacked structure includes one of the plurality of semiconductor layers [sufficiently illustrated fig. 1B].
Claim 3 Tak in view of Wang teach as shown above teaches as shown above the method according to claim 2, wherein:
the isolation is formed by an atomic layer deposition process [“ALD” sufficiently disclosed, Paragraphs 166, and/or 0170, and/or 0174].
Claim 4 Tak in view of Wang teach as shown above the method according to claim 1, wherein:
the recess is formed between adjacent semiconductor layers [sufficiently illustrated fig. 1]; and
portions of the adjacent semiconductor layers form sidewalls of the recess [sufficiently illustrated fig. 1].
Claim 5 Tak in view of Wang teach as shown above the method according to claim 4, wherein:
the isolation layer is further formed on the sidewalls of the recess [sufficiently illustrated fig. 1B in view of the embodiments as illustrated fig. 16B and 16D of Tak and in view of the modification of Wang fig. 2B].
Claim 6 Tak in view of Wang teach as shown above the method according to claim 5, wherein:
a cross-section of the isolation layer in the direction parallel to the substrate is U-shaped [met by the modification made in view of Wang fig. 2B explicitly disclosed paragraph 0026 Wang “U-shaped (90 degree rotation)”].
Claim 7 Tak in view of Wang teach as shown above the method according to claim 1, wherein: along the extension direction of the fin, a depth of the auxiliary recess is greater than 0nm [sufficiently illustrated fig. 14 and 16B-D]
Tak does not explicitly teach the depth is between 2 nm to 8 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the depth of the recess such that the depth “is between 2 nm to 8 nm” as a part of routine optimization of the capacitance between the sub-gate portions of the gates present in spaces between the nanosheets and the source/drain region and/or effective switching capacitance[sufficiently disclosed paragraph 0113, See MPEP 2144.05 II].
Claim 8 Tak in view of Wang teaches as shown above the method according to claim 1, wherein: a material of the isolation layer is SiOCN [disclosed Paragraph 0090].
Claim 9 Tak in view of Wang teaches as shown above the method according to claim 1, wherein:
the first dielectric gate layer is a first high-k gate dielectric layer [Tak sufficiently discloses in “high dielectric layer” Paragraph 0081 and/or sufficiently discloses High-k dielectric materials for the layer such as “hafnium oxide, hafnium oxynitride, hafnium silicon oxide”, “zirconium oxide”, “aluminum oxide” paragraph 0081 ].
Claim 10 Tak in view of Wang teaches the method according to claim 9, wherein the second dielectric gate layer is a second high-k gate dielectric layer [sufficiently disclosed as “High dielectric” paragraph 0081 and/or as High-K dielectric materials “hafnium oxide, hafnium oxynitride, hafnium silicon oxide”, “zirconium oxide, zirconium silicon oxide”, “aluminum oxide” paragraph 0081].
Claim 11 Tak in view of Wang teaches the method according to claim 1, wherein:
the recess is formed between the bottom semiconductor layer and the substrate [sufficiently illustrated Fig. 1A-1C, under broadest reasonable interpretation the recess as claimed has a portion formed between the bottom semiconductor layer and the substrate filled with element 104]; and
portions of the bottom semiconductor layer and the substrate form sidewalls of the recess [sufficiently illustrated fig. 1A-1C met under broadest reasonable interpretation portions of the bottom semiconductor layer and the substrate, and middle semiconductor layer and the top semiconductor layer form sidewalls of the recess].
Claim 12 Tak in view of Wang teach as shown above the method according to claim 11,
Tak in view of Wang teach the isolation layer is further formed on the sidewalls of the recess [met in view of broadest reasonable interpretation wherein the sidewalls may additionally comprise the middle semiconductor layer and the top semiconductor layer as shown above for claim 11]
Alternative if the application intended to claim and/or implied the isolation layer is formed between the bottom semiconductor layer and the substrate which the instant application does not currently claim with the explicit language of the claim, Wang teaches a similar isolation layer (35 fig. 1A) with an embodiment of an airgap (fig. 2B) that is formed between the bottom semiconductor layer and the substrate [sufficiently illustrated fig. 1A].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tak in view of Wang in further view of Wang such that ~the isolation layer is formed between the bottom semiconductor layer and the substrate~ to as duplication of parts is prima facie type obviousness [see MPEP 2144.04 VI. B.] and/or to achieve the same amount of dielectric isolation between the bottom semiconductor layer and the substrate as between adjacent semiconductor layers.
the isolation layer is further formed on the sidewalls of the recess forming a padding oxide layer on a top of the substrate, the top and the sidewall of the fin.
Claim 13 Tak teaches A semiconductor structure, comprising:
a plurality of semiconductor layers (NSS fig. 1B) on a substrate (102 fig. 1B) along a vertical direction (Z fig. 1B) with respect to the substrate;
a gate structure (150 fig. 1B) around the plurality of semiconductor layers, wherein:
the gate structure includes a first metal gate (150M fig. 1B, disclosed as metal paragraph 0082) and a plurality of second metal gates (150s fig. 1B paragraph 0082 “metal”),
the first metal gate is formed over the plurality of semiconductor layers along the vertical direction [sufficiently illustrated fig. 1B], one of the plurality of second metal gates is formed between a bottom semiconductor layer (N1 fig. 1B) of the plurality of semiconductor layers and the substrate, and each of other second metal gates of the plurality of second metal gates is formed between adjacent semiconductor layers [sufficiently illustrated fig. 1B],
the gate structure further includes a first gate dielectric layer [“high dielectric” of 145 contacting 150M and N3 fig. 1A-1C, sufficiently disclosed paragraph 0081) formed on sidewalls and a bottom surface of the first metal gate [sufficiently illustrated with 145 fig. 1B in view of Paragraph 0081], and a second gate dielectric layer [“high dielectric” of 145 contacting 150S and N2 and/or N3 fig. 1A-1C, sufficiently disclosed paragraph 0081) formed around each of the plurality of second metal gates [sufficiently illustrated with 145 fig. 1B in view of Paragraph 0081], and
an oxide layer [“interfacial layer” of 145 contacting 150 and N3 fig. 1B, disclosed paragraph 0081, also disclosed as “a silicon oxide layer, a silicon oxynitride layer, or a combination thereof” Paragraph 0081] is located between the first gate dielectric layer formed on the bottom surface of the first metal gate and a top semiconductor layer of the plurality of semiconductor layers [sufficiently disclosed The interfacial layer may cure an interface defect between the upper surface 104 of the plurality of fin type active areas FA and surfaces of the plurality of nanosheets N1, N2, and N3 and the high dielectric layer in view of 145 contacting 150 and N3 fig. 1B];
a recess (the recess filed with 140 and 104 fig. 1B) on each side of the second gate dielectric layer along a direction (X fig. 1B) parallel to the substrate;
an isolation layer (comprising 140 fig. 1B) inside the recess, the isolation layer being at least on the second gate dielectric layer [sufficiently illustrated fig. 1B]; and
a source/drain doped layer (162 fig. 1B sufficiently disclosed as Ge doped Si paragraph 0084 in “SiGe” under broadest reasonable interptatoin) on two sides of the plurality of semiconductor layers and the gate structure along the direction parallel to the substrate, wherein the source/drain doped layer and the isolation layer enclose an air gap (AS1 and/or AS2 sufficiently disclosed between fig. 1B and fig. 2A and/or 2C),
Tak does not teach the air gap is in direct contact with the source/drain doped layer.
Wang teaches a source/drain layer (50 fig. 2B) and an isolation layer (comprising 33 and 35 fig. 2B) enclosing an air gap (37 fig. 2B) wherein the air gap is in direct contact with the source/drain doped layer [sufficiently illustrated fig. 2B].
It would be obvious to one of ordinary skill in the art to substitute the airgap and insulation layer structure Tak teaches with the airgap and insulation structure Wang teaches such that “the air gap is in direct contact with the source/drain doped layer” to achieve the overall effective dielectric constant of an interspacer structure that Wang teaches [disclosed Paragraph 0026] and/or substituting equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06] in this case a spacer and/or an isolating structure adjacent to a gate.
Claim 14 Tak in view of Wang teaches as shown above the structure according to claim 13, wherein:
the recess is formed between adjacent semiconductor layers [sufficiently illustrated fig. 1B];
portions of the adjacent semiconductor layers form sidewalls of the recess [sufficiently illustrated fig. 1B]; and
the isolation layer is further formed on the sidewalls of the recess[sufficiently illustrated fig. 1B].
Claim 15 Tak teaches the structure according to claim 13, wherein: along the
The direction parallel to the substrate, a depth of the auxiliary recess is greater than 0nm [sufficently illustrated fig. 14 and 16B-D].
Tak does not explicitly teach the depth is between about 2 nm to about 8 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the depth of the recess such that the depth “is between about 2 nm to about 8 nm” as a part of routine optimization of the capacitance between the sub-gate portions of the gates present in spaces between the nanosheets and the source/drain region and/or effective switching capacitance[sufficiently disclosed paragraph 0113, See MPEP 2144.05 II].
Claim 16 Tak in view of Wang teach as shown above the structure according to claim 13, wherein:
a material of the isolation layer is SiOCN [Paragraph 0090 “SiOCN”].
Claim 17 Tak in view of Wang teaches the method according to claim 13, wherein:
the recess is formed between the bottom semiconductor layer and the substrate [sufficiently illustrated Fig. 1A-1C, under broadest reasonable interpretation the recess as claimed has a portion formed between the bottom semiconductor layer and the substrate filled with element 104]; and
portions of the bottom semiconductor layer and the substrate form sidewalls of the recess [sufficiently illustrated fig. 1A-1C met under broadest reasonable interpretation portions of the bottom semiconductor layer and the substrate, and middle semiconductor layer and the top semiconductor layer form sidewalls of the recess].
the isolation layer is further formed on the sidewalls of the recess [met in view of broadest reasonable interpretation wherein the sidewalls may additionally comprise the middle semiconductor layer and the top semiconductor layer as shown above for claim 11]
Alternative if the application intended to claim and/or implied the isolation layer is formed between the bottom semiconductor layer and the substrate which the instant application does not currently claim with the explicit language of the claim, Wang teaches a similar isolation layer (35 fig. 1A) with an embodiment of an airgap (fig. 2B) that is formed between the bottom semiconductor layer and the substrate [sufficiently illustrated fig. 1A].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Tak in view of Wang in further view of Wang such that ~the isolation layer is formed between the bottom semiconductor layer and the substrate~ to as duplication of parts is prima facie type obviousness [see MPEP 2144.04 VI. B.] and/or to achieve the same amount of dielectric isolation between the bottom semiconductor layer and the substrate as between adjacent semiconductor layers.
the isolation layer is further formed on the sidewalls of the recess forming a padding oxide layer on a top of the substrate, the top and the sidewall of the fin.
Claim 18 Tak in view of Wang teach as shown above the method according to claim 17, wherein:
a cross-section of the isolation layer in the direction parallel to the substrate is U-shaped [met by the modification made in view of Wang fig. 2B explicitly disclosed paragraph 0026 Wang “U-shaped (90 degree rotation)”].
Claim 19 Tak in view of Wang teach as shown above the structure according to claim 13, further comprising: a spacer (comprising 134 and/or 136 fig. 1B) formed on sidewalls of the first gate dielectric layer [sufficiently illustrated fig. 1B in view of the “high dielectric” Paragraph 0081].
Claim 20 Tak in view of Wang teach as shown above the structure according to claim 19, further comprising:
a dielectric layer (comprising 138 and/or 172 and/or 138 fig. 1B) covering sidewalls and a top surface of the source/drain doped layer and sidewalls of the spacer [ sufficiently illustrated fig. 1B].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210036127 A1 Lin teaches “an oxide layer is formed between the first gate dielectric layer formed on the bottom surface of the first metal gate and a top semiconductor layer of the plurality of semiconductor layers” provides the benefit of reduction and/or avoidance of undesirable depolarization of the gate dielectric layer [Paragraph 0057 Lin] and enable the gate dielectric layers to operate in a negative capacitance regime for improved device performance [Paragraph 0055 Lin].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893