DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 4 November 2025. The references cited on the PTOL 1449 form have been considered.
Claim Objections
Claim 16 is objected to because of the following informalities:
Referring to claim 16, it appears that the instance of “providing” at line 4 was inadvertently missed to be removed in the previous amendment, similar to the removal of the preceding instance at line 2, because claim 1 already recites the antecedent active positive step of “providing a substrate wafer.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 7 and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “wherein producing the layer sequence comprises creating the second semiconductor region by epitaxial growth on the third semiconductor region”
The applicant’s disclosure describes the second semiconductor region (14) epitaxially grown on the third semiconductor region (16) with respect to the embodiment depicted in Fig. 1-2B (102; page 12, lines 13-14) and the embodiment depicted in Fig. 3-4B (203; page 13, lines 6-8).
The embodiment depicted in Fig. 5-6B and the embodiment depicted in Fig. 7-8C do not provide for epitaxial growth of the second semiconductor region (14) on the third semiconductor region (16). The second semiconductor region (14) is formed as part of the substrate wafer (10) in these embodiments (Fig. 5-6B; page 13, line 29 to page 14, line 5 and Fig. 7-8C; page 14, lines 27-29).
Claim 7 then recites “creating the third semiconductor region by a rear-side introduction of a doping into the substrate wafer.” Claim 8 includes the limitations and does not cure the deficiencies of claim 7, and further includes limitations particular to embodiments exclusive of embodiments defined by claim 1.
The applicant’s disclosure describes creating the third semiconductor region (16) by rear-side doping into the substrate wafer (10) with respect to the embodiment depicted in Fig. 5-6B (page 13, line 29 to page 14, line 5) and the embodiment depicted in Fig. 7-8C (page 15, lines 10-16).
The embodiments described and depicted in Fig. 1-2B and Fig. 3-4B do not provide for rear-side doping of the substrate wafer (10) to create the third semiconductor region (16). The third semiconductor region (16) is formed by the initial substrate wafer (10) itself (Fig. 2A; page 12, lines 9-11), epitaxially grown on the substrate wafer (10) (Fig. 4A; page 13, lines 2-4), or front-side doping of the substrate wafer (10) (Fig. 4A; page 13, lines 20-22) in these embodiments.
There is no written description support of the combination of “wherein producing the layer sequence comprises creating the second semiconductor region by epitaxial growth on the third semiconductor region” and “creating the third semiconductor region by a rear-side introduction of a doping into the substrate wafer” together in a single embodiment.
It is noted that the recitation of “wherein producing the layer sequence comprises creating the second semiconductor region by epitaxial growth on the third semiconductor region” added to claim 1 was derived from previous claim 6 (now cancelled); and claims 7 and 8 did not depend from previous claim 6.
Allowable Subject Matter
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Claims 1-5, 9-15, 17 and 18 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 1, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method of producing a photodiode comprising wherein producing the layer sequence comprises creating the second semiconductor region by epitaxial growth on the third semiconductor region; partly removing the layer sequence from a side of the substrate wafer to form an adjoining rear-side third semiconductor layer of the second conductivity type having a higher doping concentration in comparison with the second semiconductor layer, such that the third semiconductor region is reduced to a thickness of the third semiconductor layer; wherein a ratio of the thickness of the third semiconductor layer to a thickness of the layer sequence is not more than 0.25 in combination with all of the limitations of Claim 1. Claims 2-5, 9, 10, 13-18 include the limitations of claim 1.
Regarding Claim 11, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the method of producing a photodiode comprising removing the layer sequence from a rear side of the substrate wafer by backside grinding until the second semiconductor region is reduced in thickness; producing, after the backside qrinding, a third semiconductor region forming a third semiconductor layer by a rear-side introduction of a doping into the second semiconductor region, by diffusion or ion implantation, wherein the third semiconductor layer is an adjoining rear-side third semiconductor layer of the second conductivity type having a higher doping concentration in comparison with the second semiconductor layer; and locally heating the third semi-conductor region wherein the first and second semiconductor layers define a p-n-junction, and the third semiconductor layer defines a back surface field, and wherein a ratio of a thickness of the third semiconductor layer to a thickness of the layer sequence is not more than 0.25 in combination with all of the limitations of Claim 11. Claim 12 includes the limitations of claim 11.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896