DETAILED ACTION
The Amendment filed on November 6, 2025, responding to the Office action mailed on August 6, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Applicant’s amendments to the Claims have overcome the objections to drawings, as previously set forth in the Non-Final Office action mailed on August 6, 2025. Accordingly, all previous drawings objections are hereby withdrawn.
Response to Arguments
Applicant argues “Economikos is cited as disclosing a gate structure”. Economikos teaches the gate dielectric layer 410 and work function layer 420 are conformally deposited on the top and sidewall surfaces of the channel regions 122 and are etched back in the gate openings 460. Hence, they anticipate the amended independent Claims 1 and 12 regarding to a work function layer and a gate dielectric layer.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 10 is rejected under 35 U.S.C. 112(a), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The amended Claim 10 contains “a top surface and/or the bottom of the first region is higher than top surfaces of the fin structure”. The originally filed Specification and the originally filed Drawings only teach a top surface of the first region is higher than or coplanar/flush with the top surfaces of the fin structures.
The applicant may cancel the claim, amend the claim, or demonstrate explicit support for the claimed subject matter in the original disclosure (e.g., by citing specific excerpts from Specification or features in Drawings related to the claimed embodiment, as originally filed). A broad statement alleging support for the claimed subject matter will be considered non-persuasive.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors.
Claims 3, 4, 10, 12, 18, and 25 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "the gate opening" in line 2. There is insufficient antecedent basis for this limitation in the claim. It is unclear if “the gate opening” is referring to “gate openings” or “each gate opening” in its independent Claim 1.
Claim 3 recites the limitation "the surface" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the size" in the phrase “the size of the second region” in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the fin structures" in line 3. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "top surfaces" in lines 2-3. It is unclear how it relates to “a top surface” in line 5 of Claim 9.
Claim 12 recites the limitation "each second region" in line 8. It is unclear if it is related to “an initial second region” in line 6.
Claim 12 recites the limitation "a second region" in line 9. It is unclear how it relates to “an initial second region” in line 6 and “each second region” in line 8.
Claim 12 recites the limitation "each gate opening" in line 13. It is unclear how it relates to “initial gate openings” in line 5 and “a gate opening” in lines 8-9.
Claim 18 recites the limitation "the initial gate opening" in line 4. There is insufficient antecedent basis for this limitation in the claim. It is unclear if it is referring to “initial gate openings” in line 5 of Claim 12 or “each initial gate opening” in lines 5-6 of Claim 12.
Claim 25 recites the limitation "each gate opening" in line 2. It is unclear how it relates to “initial gate openings” in line 5 of Claim 12 and “a gate opening” in lines 8-9 of Claim 12.
Claim 25 recites the limitation "third regions" in line 2. It is unclear how it relates to “a third region” in line 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Economikos et al. (Economikos hereinafter) (US 2019/0378722) in view of Bih et al. (Bih hereinafter) (US 2018/0102418).
Regarding Claims 1, 3, 5-10:
Economikos (see FIGs. 1-5, 9, 10) teaches {1} a semiconductor structure, comprising: a substrate 100; and a dielectric layer 320/200 on the substrate, the dielectric layer containing gate openings 460, a gate layer 470 including a first gate portion in each first region and a second gate portion in a corresponding second region; a work function layer enveloping the first gate portion from bottom of the first region, wherein a top of the work function layer 420 is under a bottom of the second gate portion; and a gate dielectric layer 410 enveloping the work function layer from the bottom of the first region and under the bottom of the second gate portion; {3} the gate opening further includes a third region on the second region, the third region has a third projection on the substrate, an area of the third projection is larger than the area of the second projection, and the second projection and the first projection are located within the third projection; {5} a barrier layer 490 in each third region; {6} the barrier layer is made of a material including a dielectric material, and the dielectric material includes silicon nitride; {7} the gate dielectric layer is on sidewall surfaces and bottom surfaces of each first region, and the work function layer on the gate dielectric layer, wherein the gate layer is on the work function layer; {8} source/drain doped layers 300 in the substrate at two sides of each gate layer; {9} he substrate includes a base substrate 100 and a fin structure 120 on the base substrate; source/drain doped layers 300 are formed in the fin structure, wherein the source/drain doped layers include a topmost portion higher than a top surface of the fin structure; and {10} a top surface and/or the bottom of the first region is higher than top surfaces of the fin structures.
Economikos (see ¶ [0042], [0045], [0047]-[0049], [0058], [0060]) teaches “suitable spacer layer 200 and conformal liner material include oxides, nitrides, and oxynitrides, such as silicon dioxide, silicon nitride, silicon oxynitride, and low dielectric constant (low-k) materials such as amorphous carbon, SiOC, SiOCN, SiBCN, as well as a low-k dielectric material”; “interlayer dielectric 320 may include any dielectric material including, for example, oxides, nitrides, or oxynitrides … silicon dioxide”; “subsequent formation of a gate stack over the top and sidewall surfaces of the channel regions 122 of fin 120. The gate stack includes a conformal gate dielectric 410 formed directly over the exposed top and sidewall surfaces of the fin 120, and a work function metal layer 420 formed over the gate dielectric layer 410”; “gate dielectric thickness may range from 1 nm to 10 nm”; “work function metal layer thickness may range from 2 nm to 12 nm”; “the gate conductor layer 470 is etched selectively … to form openings that are backfilled to form a gate cap 490”; “the gate cap 490 may include a nitride material such as silicon nitride or silicon oxynitride (SiON)”.
However, Economikos does not explicitly teach {1} each gate opening includes a first region and a second region on the first region, the first region has a first projection on the substrate, the second region has a second projection on the substrate, an area of the second projection is larger than an area of the first projection, and the first projection is located within the second projection.
Bih (see Fig. 7 and ¶ [0017], [0045]-[0046]) teaches variety of profiles of the metal gate electrodes; “due to the scaling down of semiconductor devices, critical dimensions (e.g., a width of the gate) have become increasingly small, while an aspect ratio (e.g., a ratio between the height of the gate and the width of the gate) may increase … may lead to an ‘overhang’ situation”, “profile 403 is shaped similar to two combined rectangles where an upper rectangle is wider than a bottom rectangle … profile 404 is shaped similar to three combined rectangles where an upper rectangle is wider than a middle rectangle, which is wider than a bottom rectangle” and “all the profiles 400-405, they have the common factor that the lateral dimension at the top is greater than or equal to the lateral dimension at the bottom … to allow for easy filling to form void-free metal gate electrodes … by tuning the process recipes or process parameters of the etching process”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Economikos to further include the teaching of Bih to form 2 different widths of the gate conductor layer and form the middle width of the gate conductor layer at the top of the work function layer and the gate dielectric layer where the aspect ratio is higher to prevent voids formation.
Regarding Claims 2 and 4:
Economikos does not explicitly teach the width of the gate openings. However, it would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Economikos to further include the teaching of Bih to select appropriate three different width of the gate openings in order to prevent voids formation when the gate openings are filled with metal material as the semiconductor technology moves to below 5-nanometer manufacturing.
The differences in the ranges of different width of the gate openings will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such the ranges of different widths of the gate openings are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the ranges of different width of the gate openings, it would have been obvious to one of ordinary skill in the art to use the instant claims to form the different widths of the gate openings to prevent voids formation when the gate openings are filled with metal material as the semiconductor technology moves to below 5-nanometer manufacturing.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934, 1936s (Fed. Cir. 1990).
Claims 12, 14, 15, 17-20, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Bih et al. (Bih hereinafter) (US 2018/0102418) in view of Economikos et al. (Economikos hereinafter) (US 2019/0378722).
Regarding to Claims 12, 14, 15, 17-20, and 25:
Bih (see Figs. 1-7) teaches {12} a method for forming a semiconductor structure, comprising: providing a substrate 40; forming dummy gate structures 80B on the substrate; forming a dielectric layer 190/220 on sidewalls of the dummy gate structures; removing the dummy gate structures to form initial gate openings, wherein: each initial gate opening includes a first region and an initial second region on the first region, and the first region has a first projection on the substrate; removing a portion of the dielectric layer on sidewalls of each second region to form a gate opening, wherein: the gate opening includes the first region and a second region on the first region, the first region has a first projection on the substrate, the second region has a second projection on the substrate, an area of the second projection is larger than an area of the first projection, and the first projection is located within the second projection; forming an initial gate layer 290/291 in each gate opening, wherein the initial gate layer includes a first gate portion in each first region and a second gate portion in a corresponding second region; and {14} the second region is formed by: forming a sacrificial layer in each first region; and after forming the second region, removing the sacrificial layer.
Bih (see Fig. 7 and ¶ [0017], [0045]-[0047]) teaches variety of profiles of the metal gate electrodes; “due to the scaling down of semiconductor devices, critical dimensions (e.g., a width of the gate) have become increasingly small, while an aspect ratio (e.g., a ratio between the height of the gate and the width of the gate) may increase … may lead to an ‘overhang’ situation”, “profile 403 is shaped similar to two combined rectangles where an upper rectangle is wider than a bottom rectangle … profile 404 is shaped similar to three combined rectangles where an upper rectangle is wider than a middle rectangle, which is wider than a bottom rectangle” and “all the profiles 400-405, they have the common factor that the lateral dimension at the top is greater than or equal to the lateral dimension at the bottom … to allow for easy filling to form void-free metal gate electrodes … by tuning the process recipes or process parameters of the etching process”; and “the aspects of the present disclosure may apply to both ‘2-dimensional’ planar devices or ‘3-dimensional’ FinFET devices”.
However Bih does not explicitly teach {12} forming a work function layer enveloping the first gate portion from bottom of the first region, wherein a top of the work function layer is under a bottom of the second gate portion; and forming a gate dielectric layer enveloping the work function layer from the bottom of the first region and under the bottom of the second gate portion; {14} using sacrificial layer as a mask to etch the dielectric layer on sidewalls of the initial second region, to form the second region; {15} the sacrificial layer is formed by an etching back process; {17} the dielectric layer on the sidewalls of the initial second region is etched by an isotropic dry etching method; {18} before forming the sacrificial layer in the first region, further comprising: forming an initial gate dielectric layer on sidewall surfaces and bottom surface of the initial gate opening and an initial work function layer on the initial gate dielectric layer, wherein the sacrificial layer is located on the initial work function layer; {19} before using the sacrificial layer as the mask to etch the dielectric layer on the sidewalls of the initial second region, further comprising: using the sacrificial layer as a mask to remove the initial gate dielectric layer and the initial function layer on the sidewalls of the initial second region, to form the gate dielectric layer and the work function layer on sidewall surfaces and bottom surfaces of the first region, wherein the second region exposes a top surface of the gate dielectric layer and a top surface of the work function layer; {20} the initial gate dielectric layer and the initial function layer on the sidewalls of the initial second region are removed by a wet etching method; and {25} each gate opening further includes a third region on the corresponding second region, and the third region is formed by: removing a portion of the initial gate layer to form the gate layer and transition third regions in the dielectric layer, wherein sidewalls of the transition third regions expose the dielectric layer; and etching the dielectric layer exposed by the sidewalls of the transition third regions to form third regions, wherein: each third region has a third projection on the substrate, an area of the third projection is larger than the area of the second projection, and the second projection and the first projection are located within the third projection.
Economikos (see FIGs. 1-5 and ¶ [0033], [0050]-[0053], and [0062]) teaches “a replacement metal gate (RMG) structure following the removal of a sacrificial gate … gate dielectric and work function metal layers 410, 420 are deposited in succession”; “a masking layer 450 is formed over the gate dielectric and work function metal layers … is then recessed … may include an organic planarization layer … is adapted to limit the extend of a subsequent recess etch of the gate dielectric and work functional metal layers 410, 420 to form gate openings 460”; “masking layer 450 may include a photo-sensitive organic polymer … configured to be removed using a developing solvent”; “the recess etching processes described herein typically include an anisotrpic etch … a dry etching process … a wet chemical etchant … a combination of dry etching and wet etching can be used”; “a gate conductor layer 470 is formed over the recessed work function metal and gate dielectric layers 410, 420”; and “the sacrificial layer 340 can be removed by ashing, a reactive ion etch or isotropic etch such as a wet etch or an isotropic plasma etch”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Bih to further include the teaching of Economikos to form the gate dielectric layer and the work function layer after the dummy gate electrode being removed which is another commonly alternative process; to at least partially etch back the gate spacer through any of the known etching methods, such as isotropic dry etching or a web etching and using the masking layer as a sacrificial layer in order to implement the desired multi-step-profile for the dummy gate electrodes to prevent the voids formations in subsequent process of forming a metal gate electrode.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Bih et al. (Bih hereinafter) (US 2018/0102418) in view of Economikos et al. (Economikos hereinafter) (US 2019/0378722) as applied to claim 12 above, and further in view of Jin et al. (Jin hereinafter) (US 2008/0079094).
Regarding Claim 16:
Bih in the method of Economikos does not explicitly teach the sacrificial layer is made of an organic material and the organic material includes amorphous silicon or photoresist.
Jin (see ¶ [0031]) teaches “sacrificial layer such as a photoimageable species (including photoresist) can be deposited and selectively etch … in preparation for forming trenches 165”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Bih in the method of Economikos to further include the teaching of Jin to select other known material, such as photoresist for the sacrificial layer in order to be etched away to configure desired shape of the gate opening.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Bih et al. (Bih hereinafter) (US 2018/0102418) in view of Economikos et al. (Economikos hereinafter) (US 2019/0378722) as applied to claim 12 above, and further in view of Smith et al. (Smith hereinafter) (US 9,847,347).
Regarding Claim 21:
Bih in the method of Economikos does not explicitly teach a depth-to-width aspect ratio of each initial gate opening is about 3~6.
Smith (see FIG. 3 and col.6/l.66 – col.7/l.5) teaches “an aspect ratio between the height 307 and the extension 308 in the channel length direction of the dummy gate structure 301 … may be about 2.5 or more … may be in a range from about 3-7”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Bih in the method of Economikos to further include the teaching of Smith to form multi-step-profile of the dummy gate electrode with an aspect ratio of the instant invention to prevent voids formed when the openings are filled with metal.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814