DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office Action is in response to the amendment filed 12/22/2025. Claims 11-20 are pending.
Response to Arguments
Objection to the Specification
Applicant's arguments regarding the objection to the specification have been fully considered and are persuasive. Therefore, the objection has been withdrawn.
Rejections under 35 U.S.C. 112
Applicant's arguments regarding the rejection of claims 11-20 under 35 U.S.C. 112 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Rejections under 35 U.S.C. 101
Applicant's arguments regarding the rejection of claims 11-20 under 35 U.S.C. 101 have been fully considered and are not persuasive. Regarding claim 11 Applicant argues: “In response to this rejection, Applicant submits that the claims, as amended, are directed to significantly more than just the abstract idea. Specifically, amended claim 11 recites a particular hardware configuration that includes "a common logic module including a microcontroller, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), ... wherein the common logic module includes a summation logic, a division logic, and an evaluation logic." Amended claim 11 is limited to execution of the method by this specific hardware configuration. Accordingly, the amended limitations provide a meaningful limitation on the abstract idea that prevents monopolization of the abstract idea.
Therefore, amended claim 11 is directed to eligible subject matter.
Additionally, the method according to amended claim 11 provides a technological improvement over conventional methods by reducing the system complexity as compared to conventional systems and methods, which require the reference voltage sensor which is typically arranged in a separate reference module. See [0002]. This also reduces the cost of the system that performs the method, which is another advantage over conventional systems.
Thus, amended claim 11 provides significantly more than the abstract idea and is directed to eligible subject matter for this additional reason.
Dependent claims 12-20 are directed to eligible subject matter for reasons analogous to those for claim 11.” The Examiner respectfully disagrees the limitations “a common logic module including a microcontroller, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), ... wherein the common logic module includes a summation logic, a division logic, and an evaluation logic.t” are merely data processing devices such as a processor, controller, etc to perform a set of computations. The specification recites, in Paragraph [0055], “Likewise, the summing logic ADD, the division logic DIV and the evaluation logic AW can be integrated in a common logic module, such as a microcontroller, ASIC, FPGA, etc." showing that said limitations are routine data processing methods. The other limitations of “wherein at least steps (b) and (c) are executed for the voltage sensors in a commutated manner“ to be merely mathematical flow charts, see fig. 1 and Paragraph [0042], and a data processing device such as a processor, controller, etc to perform a set of computations. Accordingly, the claim recites an abstract idea. The rejection stands.
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of
matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the
conditions and requirements of this title.
Claims 11-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract
idea without significantly more.
Regarding claim 11:
STEP 1: the claim is directed to a method which falls within the statutory category of a process.
STEP 2A Prong 1: the claim recites the steps of “(a) receiving, by a common logic module including a microcontroller, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), voltage measurement values from the n voltage sensors of only the controllers in the onboard electrical system of the vehicle, wherein the common logic module includes a summation logic, a division logic, and an evaluation logic; (b) averaging, by the summation logic followed by the division logic, voltage measurement values from n−1 voltage sensors; (c) determining, by the evaluation logic, a deviation of a voltage measurement value of a remaining voltage sensor from an averaged voltage measurement value; and (d) outputting an error message relating to a fault state of the remaining voltage sensor when the deviation satisfies a specified criterion; wherein at least steps (b) and (c) are executed for the voltage sensors in a commutated manner.”.
The step of calculating… “averaging, by the summation logic followed by the division logic, voltage measurement values from n−1 voltage sensors …”, “determining, by the evaluation logic, a deviation of a voltage measurement value of a remaining voltage sensor from an averaged voltage measurement value …”, fall within the enumerated grouping of abstract ideas of “Mathematical Concepts” of calculation, which can be illustrated from the relevant portion of the original spec, such as Paragraphs [0002]-[0009] and [0055], disclosing a data processing device such as a processor, controller, etc to perform a set of computations, such as Paragraphs [0049]-[0052]. Accordingly, the claim recites an abstract idea.
STEP 2A Prong 2, the claim recites the steps of “(a) receiving, by a common logic module including a microcontroller, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA), voltage measurement values from the n voltage sensors of only the controllers in the onboard electrical system of the vehicle, wherein the common logic module includes a summation logic, a division logic, and an evaluation logic” and “wherein at least steps (b) and (c) are executed for the voltage sensors in a commutated manner”. The claim recites no more than routine data gathering and mere instructions to implement an abstract idea or other exception on a computer. Thus, claims that amount to nothing more than an instruction to apply the abstract idea using a generic computer do not render an abstract idea eligible.
Therefore, the claim is directed to an abstract idea.
Step 2B, the additional elements considered individually and in combination do not qualify significant more because the they are routine data gathering and mere instructions to implement an abstract idea on a computer.
As such, claim 11 is ineligible under 35 USC 101.
Claims 12-20 are rejected for depending from rejected claim 11 and only amounting to further limit the abstract idea of claim 11.
Comments
The prior art of record found as a result of the search, does not teach alone or in combination all of the elements recited in claims 11-20. Therefore, no prior art rejection for claim 11 is presented in this action. However, Claims 11-20 are rejected under 35 U.S.C. 101. It is suggested to contact the Examiner for any clarification with respect the rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
-Pani teaches checking voltage measurements.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S CLARKE whose telephone number is (571)270-3792. The examiner can normally be reached M-F 8am-4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADAM S CLARKE/Examiner, Art Unit 2858
/JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858
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