DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 4, 7-10, 17 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ma et al. (US 2022/0045155).
Regarding claim 1, Ma discloses a display panel, wherein the display panel has a display region comprising a first display region (101, figs. 1, 4 and paragraph 0042) and a second display region (102, figs. 1, 4 and paragraph 0042), and a density of pixel circuits in the first display region is less than a density of pixel circuits in the second display region (figs. 1, 4 and paragraph 0042); the display panel comprises:
a base substrate (710, figs. 11-12 and paragraph 0072);
a plurality of first pixel circuits disposed on the base substrate and located in the second display region (720, figs. 11-12 and paragraphs 0072-0080);
a plurality of first traces disposed on a side of the first pixel circuits away from the base substrate (300, figs. 11-12 and paragraphs 0078-0080);
a pixel defining layer disposed on a side of the first traces away from the base substrate and defining a plurality of openings in the pixel defining layer (760, figs. 11-12 and paragraphs 0078-0080):
a plurality of first light emitters disposed on the side of the first traces away from the base substrate and located in the first display region (101, figs. 11-12), wherein the first light emitters have effective light emitting regions respectively located in the openings, the first light emitters have first anodes (771, figs. 11-12 and paragraphs 0078-0080) each comprising an effective light emitting anode region and a non-light emitting anode region disposed surrounding the effective light emitting anode region, and the pixel defining layer covers the non-light emitting anode region and the effective light emitting regions each comprise the effective light emitting anode region (figs. 11-12 and paragraphs 0078-0080):
wherein the first traces are respectively electrically connected with the first pixel circuits through first vias (via close to transistor, figs. 11-12) and respectively electrically connected with the first anodes through second vias (via under anode 771, figs. 11-12 and paragraphs 0078-0080), and orthographic projections of the second vias on the base substrate are respectively located in orthographic projections of the first anodes on the base substrate (figs. 11-12 and paragraphs 0078-0080).
Regarding claim 2, Ma further discloses wherein orthographic projections of the openings on the base substrate are shaped as circles, parts of circles, ovals or parts of ovals (7731, fig. 13 and paragraphs 0082-0083), and/or the orthographic projections of the first anodes on the base substrate are shaped as circles or ovals (7731,fig. 13 and paragraphs 0082-0083).
Regarding claim 4, Ma further discloses a first insulating layer disposed on the side of the first pixel circuits away from the base substrate (730, figs. 11-12 and paragraphs 0075-0080), wherein the plurality of first traces are disposed on a surface of the first insulating layer away from the base substrate and respectively electrically connected with the first pixel circuits through the first vias penetrating the first insulating layer (via close to transistor, figs. 11-12 and paragraphs 0075-0080);
a second insulating layer disposed on the surface of the first insulating layer away from the base substrate and covering the first traces (750, figs. 11-12 and paragraphs 0077-0080), wherein the pixel defining layer is disposed on a side of the second insulating layer away from the base substrate, and the first anodes are respectively electrically connected with the first traces through the second vias penetrating the second insulating layer (via under anode, figs. 11-12 and paragraphs 0076-0080).
Regarding claims 7, 17 and 19, Ma further discloses wherein the orthographic projections of the second vias on the base substrate are respectively in orthographic projections of effective light emitting anode regions on the base substrate (via under anode, figs. 11-12).
Regarding claim 8, Ma further discloses wherein the first traces comprises indium tin oxide (ITO), aluminum-doped zinc oxide (AZO) or both (paragraph 0089).
Regarding claim 9, Ma further discloses a plurality of second pixel circuits and a plurality of second light emitters that are both located in the second display region (220, 210, figs. 1, 4 and paragraph 0051), wherein the second pixel circuits are directly electrically connected with the second anodes in the second light emitting device emitters through third vias, to drive the second light emitting device emitters to emit light or the display panel further comprises a conductive layer disposed in a same layer as the first traces, the second anodes are electrically connected with the conductive layer through fourth vias penetrating the second insulating layer, and the conductive layer is electrically connected with the second pixel circuits through fifth vias penetrating the first insulating layer, to drive the second light emitting device emitters to emit light (paragraphs 0050-0056).
Regarding claim 10, Ma further discloses a display apparatus, comprising:
the display panel according to any one of claim 1;
an under-screen functional layer, wherein an orthographic projection of the under- screen functional layer on the display panel overlaps the first display region of the display panel (figs. 1, 4 and paragraph 0050).
Regarding claim 20, Ma further discloses wherein a the first traces comprises indium tin oxide (ITO), and aluminum-doped zinc oxide (AZO) or both (paragraph 0089).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5-6, 11-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 2022/0045155) in view of Yang et al. (US 2020/0312209).
Regarding claim 3, Ma discloses the panel according to claim 2, as mentioned above. Ma further discloses the light emitters shaped as ovals (figs. 13, 15). Ma does not explicitly disclose blue, red and green light emitters. However, it was well known at the time of filing that pixels for displays are divided into blue, red and green pixels and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing.
Regarding claim 18, Ma further discloses wherein the orthographic projections of the second vias on the base substrate are respectively in orthographic projections of effective light emitting anode regions on the base substrate (via under anode, figs. 11-12).
Regarding claims 5 and 11-13, Ma discloses the display panel of claims 1-4 as mentioned above. Ma further discloses wherein portions of the orthographic projections of the second vias (via under anode, figs. 11-12) on the base substrate are respectively in orthographic projections of effective light emitting anode regions on the base substrate. Ma does not disclose wherein other portions of the orthographic projections of the second vias on the base substrate are respectively in orthographic projections of non-light emitting anode regions on the base substrate. However, the corresponding position of the via placement being under the effective light emitting anode regions, as taught by Ma, or under the non-light emitting anode regions or at the intersection therebetween and under both the light-emitting anode regions and the non-light emitting anode regions was well known at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate the known teachings in addition to Ma’s disclosure of under the light-emitting anode region, see Yang figure 5 (under both light emitting anode region and non-light emitting anode region) and Yang figure 6 (under non-light emitting region only).
Regarding claims 6 and 14-16, Ma discloses the display panel of claims 1-4 as mentioned above. Ma further discloses wherein portions of the orthographic projections of the second vias (via under anode, figs. 11-12) on the base substrate are respectively in orthographic projections of effective light emitting anode regions on the base substrate. Ma does not disclose wherein the orthographic projections of the second vias on the base substrate are respectively in orthographic projections of non-light emitting anode regions on the base substrate. However, the corresponding position of the via placement being under the effective light emitting anode regions, as taught by Ma, or under the non-light emitting anode regions or at the intersection therebetween and under both the light-emitting anode regions and the non-light emitting anode regions was well known at the time of filing and would therefore be deemed obvious to one of ordinary skill in the art at the time of filing. To illustrate the known teachings in addition to Ma’s disclosure of under the light-emitting anode region, see Yang figure 5 (under both light emitting anode region and non-light emitting anode region) and Yang figure 6 (under non-light emitting region only).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publications 20210343222 and 20210057494 both disclose display panels with a lower pixel density transmission display region and a regular display region wherein the pixel circuits are disposed in the regular display region that correspond to the light emitting elements in the lower density transmission display region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 9/29/25