DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-9, 13, 15 and 26-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kimura et al. (PG Pub. No. US 2020/0105330 A1).
Regarding claim 1, Kimura teaches a NOR-type memory device (¶ 0307), comprising:
a first gate stack (¶¶ 0165, 0168: 134/103/152/104) extending vertically on a substrate (figs. 18A, 29A: 1700), wherein the first gate stack comprises a gate conductor layer (¶ 0168: 134) and a memory functional layer (¶ 0168 & fig. 27: composite structure 103/152/104 includes at least one layer comprised by memory cell MC which provides a read and/or write function); and
a first semiconductor layer (¶ 0156: 151) surrounding a periphery of the first gate stack and extending along a sidewall of the first gate stack (fig. 18A among others: 151 surrounds periphery of and extends along a sidewall of 134/103/152/104),
wherein the memory functional layer is located between the first semiconductor layer and the gate conductor layer (fig. 18A: 103/152/104 arranged between 151 and 134),
wherein the first semiconductor layer comprises a first source/drain region (¶ 0163 & fig. 17A: first 151b/151c), a first channel region (¶ 0163: 151a) and a second source/drain region (¶ 0163: second 151b/151c) arranged in sequence in a vertical direction (figs. 17A, 18A: 151/b/c, 151a, 151b/c vertically arranged in sequence), and
wherein a memory cell is defined at an intersection of the first gate stack and the first semiconductor layer (¶ 0163 & fig. 27 among others: memory cell MC provided in part by intersection of 134/103/152/104 and 151),
the NOR-type memory device further comprises a conductive shielding layer (¶ 0131, 0138: 131A or 131B, comprising a function of shielding against material such as hydrogen) surrounding a periphery of the first channel region of the first semiconductor layer (fig. 18A: 131A/131B surrounds periphery of 151a), and a dielectric layer (¶¶ 0131, 0149: 102 and/or 101C/101D) between the first channel region of the first semiconductor layer and the conductive shielding layer (fig. 18A: portion of 102 and/or 101C arranged between 151a and 131A/131B),
the NOR-type memory device further comprises a first interconnection layer (¶ 0131: 132A) extending laterally at a periphery of the first source/drain region of the first semiconductor layer (fig. 18A: 132A extending laterally at periphery of first 151b/151c) and a second interconnection layer (¶ 0131: 132B) extending laterally at a periphery of the second source/drain region of the first semiconductor layer (fig. 18A: 132B extending laterally at periphery of second 151b/151c),
wherein the conductive shielding layer extends laterally between the first interconnection layer and the second interconnection layer to surround a periphery of the first semiconductor layer (fig. 18A: 131A extends laterally between the 132A and 132B to surround a periphery of 151).
Regarding claim 2, Kimura teaches the NOR-type memory device according to claim 1, wherein:
the first interconnection layer surrounds the periphery of the first source/drain region of the first semiconductor layer (fig. 18A: 132A surrounds periphery of first 151c/151c); and
the second interconnection layer surrounds the periphery of the second source/drain region of the first semiconductor layer (fig. 18A: 132B surrounds periphery of second 151c/151c),
wherein the dielectric layer is further located between the conductive shielding layer and the first interconnection layer and between the conductive shielding layer and the second interconnection layer (fig. 18A: 102 and/or 101C located between 131B and 1232B).
Regarding claim 3, Kimura teaches the NOR-type memory device according to claim 2, further comprising:
a plurality of the first gate stacks (¶ 0207 & figs. 18A, 27: plurality of BGL, comprising 134/103/152/104 of fig. 18A), wherein each of the plurality of first gate stacks extends vertically through the first interconnection layer and the second interconnection layer (fig. 27: each BGL extends through RWL, comprising interconnection layers 132A and 132B of fig. 18A);
a plurality of the first semiconductor layers (fig. 27: plurality of WBL, comprising layer 152 of fig. 18A) extending along sidewalls of corresponding first gate stacks to surround the periphery of each first gate stack respectively (fig. 27: plurality of WBL surrounds periphery of BGL), wherein each of the plurality of first semiconductor layers is located at substantially a same height with respect to the substrate (fig. 27: each WBL/152 located at same height) and extends vertically through the first interconnection layer and the second interconnection layer (fig. 27: each WBL/152 extends vertically through each RWL/132A and RWL/132B),
wherein the conductive shielding layer extends laterally between the first interconnection layer and the second interconnection layer to surround a periphery of each first semiconductor layer (fig. 27: WWL, comprising 131A or 131B of fig. 18A, extends laterally between RWL/132A and RWL/132B to surround a periphery of each WBL/152), and the dielectric layer extends to be located between the conductive shielding layer and the first semiconductor layer, between the conductive shielding layer and the first interconnection layer, and between the conductive shielding layer and the second interconnection layer (figs. 18A, 26-27: 102 and/or 101C/101D extends to be located between WWL/131B and 152, between WWL/131B and RWL/132A, and between WWL/131B and RWL/132B).
Regarding claim 4, Kimura teaches the NOR-type memory device according to claim 3,
wherein each first semiconductor layer further comprises a second channel region and a third source/drain region arranged in sequence in the vertical direction (figs. 17A, 18A: second 151a and third 151b/151c), and the second channel region is located between the second source/drain region and the third source/drain region in the vertical direction (figs. 17A, 18A: second 151a arrandes between second 151b/151c and third 151b/151c), so that two memory cells stacked with each other are defined at the intersection of the first gate stack and each first semiconductor layer (fig. 27 among others: two memory cells vertically stacked at intersections of 134/103/152/104 and 151),
the NOR-type memory device further comprises:
a third interconnection layer (fig. 27: third RWL/132) extending laterally to surround a periphery of the third source/drain region of each first semiconductor layer (fig. 27: third RWL/132 extends laterally to surround a periphery of the third 1151b/151c);
a further conductive shielding layer (second WWL/131) extending laterally between the second interconnection layer and the third interconnection layer to surround the periphery of each first semiconductor layer (figs. 17A, 18A, 27: second WWL/131 extends laterally between second RWL/132 and third RWL/132 to surround the periphery of each 151); and
a further dielectric layer located between the further conductive shielding layer and the first semiconductor layer, between the further conductive shielding layer and the second interconnection layer, and between the further conductive shielding layer and the third interconnection layer (fig. 27: additional portion of 102 and/or 101E located between second WWL/131 and 151, between second WWL/131 and second RWL/132, and between second WWL/131 and third RWL/132).
Regarding claim 5, Kimura teaches the NOR-type memory device according to claim 4, wherein the substrate comprises a device region (¶ 0212 & fig. 28A: bottom portion including Si transistor) and a contact region (¶ 0209: intermediate region including conductor 1730) adjacent to the device region (fig. 28A: layer including 1730 vertically adjacent to layer comprising Si transistor), and the memory cell is formed on the device region (fig. 28A: MC formed on region including Si transistor),
wherein the first interconnection layer, the second interconnection layer and the third interconnection layer respectively extend from the device region to the contact region in a first direction (figs. 13A, 13B 28A: 132A/132B/143 laterally extend from a region comprising at least one Si transistor to a region comprising at least one 1730).
Regarding claim 8, Kimura teaches the NOR-type memory device according to claim 3, further comprising:
a plurality of second semiconductor layers (151 of adjacent cell) extending along sidewalls of corresponding first gate stacks to surround the periphery of each first gate stack respectively (fig. 28A: 151 surrounds gate stack of adjacent cell), wherein each second semiconductor layer is located at substantially a same height with respect to the substrate but different from the height of the first semiconductor layer (fig. 28A: 2nd 151 located at a same height, including portions with different height than 1st 151), and comprises a first source/drain region, a first channel region and a second source/drain region arranged in sequence in the vertical direction (figs. 17A, 18A, 28A: 2nd 151 include sequentially stacks 1st S/D, channel, and 2ns S/D regions);
a third interconnection layer extending laterally to surround a periphery of the first source/drain region of each second semiconductor layer (see annotated fig. 28A below);
a fourth interconnection layer extending laterally to surround a periphery of the second source/drain region of each second semiconductor layer (see annotated fig. 28A below);
a further conductive shielding layer extending laterally between the third interconnection layer and the fourth interconnection layer to surround a periphery of each second semiconductor layer (see annotated fig. 28A below); and
a further dielectric layer located between the further conductive shielding layer and the second semiconductor layer, between the further conductive shielding layer and the third interconnection layer, and between the further conductive shielding layer and the fourth interconnection layer (see annotated fig. 28A below).
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Regarding claim 9, Kimura teaches the NOR-type memory device according to claim 4, further comprising:
a contact portion to the conductive shielding layer (figs. 1-6: 131 connected to WWL1-n and/or RWL1-n, and therefore implicitly includes a contact portion).
Regarding claim 13, Kimura teaches the NOR-type memory device according to claim 8, wherein an isolation layer (¶ 0131: 101B and/or 101C) is provided between the first semiconductor layer and the second semiconductor layer (fig. 28A: 101B/101C provided between 151 in adjacent cell regions).
Regarding claim 15, Kimura teaches the NOR-type memory device according to claim 1, wherein the conductive shielding layer and the dielectric layer form a second gate stack (¶ 0136, fig. 1C among others: 131 provide a gate structure of WWL1-n for transistors WTr/DTr).
Regarding claim 26, Kimura teaches an electronic apparatus, comprising the NOR-type memory device according to claim 1 (implicit: NOR-type memory is a type of electronic apparatus).
Regarding claim 27, Kimura teaches the electronic apparatus according to claim 26, wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply (¶ 0261).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claims 5 and 8 above, and further in view of Zhang et al. (PG Pub. No. US 2021/0217775 A1).
Regarding claim 6, Kimura teaches the NOR-type memory device according to claim 5, further comprising:
a first bit line and a second bit line different from the first bit line (¶ 0057 & figs. 1-6: WBL1/2/n and/or RBL1/2/n); and
a source line (¶ 0057 & figs. 1-6: WWL1/2/n and/or RWL1/2/n),
Kimura does not teach wherein the first interconnection layer and the third interconnection layer are electrically connected to the first bit line and the second bit line respectively, and the second interconnection layer is electrically connected to the source line.
Zhang teaches a NOR-type memory device (¶ 0090 & fig. 20 among others) including
a first bit line (BL1) and a second bit line (BL2) different from the first bit line (BL2 implicitly different from BL1); and
a source line (SL1 or SL2),
wherein a first interconnection layer and a third interconnection layer are electrically connected to the first bit line and the second bit line respectively (figs. 19E, 20: elements 46 and/or 48 electrically connected to respective BL1 and BL2), and a second interconnection layer is electrically connected to the source line (element 42 and/or 44 electrically connected to CS1/CS2).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the memory device of Kimura with bit lines and source line(s), as a means to provide signals in a memory array circuit (Zhang, ¶¶ 0032, 0090).
Regarding claim 12, Kimura teaches the NOR-type memory device according to claim 8, comprising first and second semiconductor layers (1st and 2nd 151) extending around respective first gate stacks (fig. 28A: each 151 extends around a 1st gate stack).
Kimura does not teach wherein the first semiconductor layer and the second semiconductor layer extending around a same first gate stack are substantially coplanar in the vertical direction.
Zhang teaches a memory device (fig. 18E) including a plurality of semiconductor layers (active
region including channels 60 and source/drains 44/46, similar to 151 of Kimura) extending around a
same first gate stack are substantially coplanar in the vertical direction (fig. 18E: top and bottom
44/60/46 extend around same gate stack 70/50, similar to 1037/1035 of Zhu, and substantially coplanar in vertical direction).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed
to configure the plurality of semiconductor layers of Zhu around a same first gate stack, as a means to
provide a plurality of memory units in a stacked configuration, increasing memory capacity and/or density, improving manufacturing efficiency.
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Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claim 4 above, and further in view of Kwon et al. (PG Pub. no. US 2007/0176214 A1).
Regarding claim 7, Kimura teaches the NOR-type memory device according to claim 4, wherein the first interconnection layer, the second interconnection layer and the third interconnection layer contain a doped semiconductor material (¶ 0137: in at least one embodiment, 131A/B and 132A/B comprise doped semiconductor material).
Kimura fails to teach the first, second and third interconnection layers comprise single crystalline material.
Kwon teaches a Nor-type memory device (¶ 0013) including a plurality of interconnection layers (¶ 0016: semiconductor layers associated to source and/or bit lines) comprising single crystalline material (¶ 0017: semiconductor layers formed with single crystal silicon).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the doped semiconductor material of Kimura with single crystalline material, as a means to optimize properties of the interconnection layers, minimizing parameters such parasitic resistance.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, doped single crystal semiconductor material is suitable to form the interconnection layers of Kimura.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claim 1 above, and further in view of Salahuddin et al. (PG Pub. No. US 2020/0227123 A1).
Regarding claim 10, Kimura teaches the NOR-type memory device according to claim 1, comprising a memory functional layer (¶ 0168: composite structure includes a memory read and/or write function).
Kimura does not teach wherein the memory functional layer contains at least one of a charge trapping material or a ferroelectric material.
Salahuddin teaches a NOR-type memory device (¶ 0017 & fig. 5g among others) including a memory functional layer containing a charge trapping material (¶ 0067: charge-trapping layers 531), the memory functional layer located between a first semiconductor layer (¶ 0154: 522) and a gate conductor layer (fig. 5g: 531 located between 522 and gate conductor 208W).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the NOR-type memory functional layer of Kimura with the charge-trapping material of Salahuddin, as a means to enable parallel read, write or erase operations on a large number of addressed TFTs (Salahuddin, ¶ 0019).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claim 1 above, and further in view of Lee et al. (PG Pub. No. US 2021/0159231 A1).
Regarding claim 11, Kimura teaches the NOR-type memory device according to claim 1, wherein the semiconductor layer contains a semiconductor material (¶ 0138).
Kimura does not teach the semiconductor material is single crystalline.
Lee teaches a memory device (¶ 0037: 10) including a single crystalline semiconductor material channel layer (¶ 0052).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the semiconductor layer of Kimura with single crystalline material, as a means to provide the channel region of the semiconductor layer (Lee, ¶ 0052).
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, single crystalline material is suitable to provide the semiconductor layer of Kimura, as evidenced by Lee.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claim 8 above, and further in view of Rajashekhar et al. (PG Pub. No. US 20210202703 A1).
Regarding claim 14, Kimura teaches the NOR-type memory device according to claim 8, wherein the first semiconductor layer is a vertically extending element with an annular cross-section, and the second semiconductor layer is a vertically extending element with an annular cross-section (¶ 0127 & figs. 13A, 18A among others: conductors/semiconductors, including 151, formed in annular shaped regions HL).
Kimura does not teach the vertically extending elements are nanosheets.
Rajashekhar teaches a NOR-type memory device (¶ 0145) including an annular semiconductor layer (¶ 0084: 60L, similar to 151 of Kimura) comprising nanosheets (¶ 0084: 60L includes a sheet-like structure with 4nm thickness, meeting the broadest reasonable interpretation of “nanosheets”).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first and second semiconductor layers of Kimura as nanosheets, as a means to provide a memory channel with optimized size, shape and/or density.
Furthermore, such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claim 1 above, and further in view of Xu et al. (PG Pub. No. US 2020/0013896 A1).
Regarding claim 16, Kimura teaches the NOR-type memory device according to claim 15, comprising a second gate stack (¶ 0136: 131/WWL).
Kimura does not teach wherein the second gate stack is configured for at least one selected from:
shielding a crosstalk between memory cells,
adjusting a threshold voltage of the memory cell,
increasing an on-state current, or
reducing a leakage current.
Xu teaches a memory device (¶ 0029) including a conductive shielding layer (¶ 0029: control gates, similar to 131/WWL of Kimura), configured for shielding a crosstalk between memory cells (¶ 0029: control gates provide shielding function to reduce cross-talk), minimizing data leakage and enhancing data retention.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the second gate stack of Zimura with a cross-talk shielding function, as a means to reduce ross-talk between memory cells (Xu, ¶ 0029).
Response to Arguments
Applicant’s arguments, see page 11, filed 3/12/2026, with respect to the drawing objections have been fully considered and are persuasive. Accordingly, the drawing objections have been withdrawn.
Applicant’s arguments with respect to the 35 USC § 112(b) rejections have been fully considered and are persuasive. Accordingly, the 35 USC § 112(b) rejections have been withdrawn.
Applicant’s arguments with respect to the 35 USC § 102 and 35 USC § 103 rejections of claims 1-16 and 26-27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/ Examiner, Art Unit 2818