DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement(s)
The Information Disclosure Statement (IDS) filed on August 26, 2025 was considered by the Examiner. However, the IDS filed March 26, 2026 was not considered as it did not include the statement specified in paragraph (e) of 37 C.F.R. 1.97; or the fee set forth in § 1.17(p).
Election/Restrictions
Applicant's election of Group II in the reply filed on March 11, 2026 is acknowledged.
Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
As the election was made without traverse, the requirement is deemed proper and is therefore made FINAL.
Response to Arguments
RE: the rejection of claim 10 under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are not persuasive. Applicant states that for at least the reasons presented in the interview, the applied references do not teach the highlighted subject matter of claim 10. However, the present amendment to claim 10 was not discussed during the interview (see the proposed claim amendments attached to the Examiner’s Summary Record dated October 1, 2025).
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 23 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 23 includes “wherein the at least two dummy silicon components have a greater thermal conductivity than a mold compound in which the package-on-package assembly is encapsulated” which is not supported by the instant application and is therefore considered new matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-14, 17, 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20200243497A1 to Hsu et al. (hereinafter “Hsu”).
RE: Claim 10, Hsu discloses A package-on-package assembly (PS1 in FIGs. 12, 13A, [0014]) comprising:
a first integrated circuit package (10, [0014]) comprising a first integrated circuit die (130, [0026]);
a second integrated circuit package (20, [0014]) comprising a second integrated circuit die (220a, 220b, [0066]), the second integrated circuit package coupled to the first integrated circuit package (FIG. 12 shows 20 is coupled to 10); and
thermal management components (120 / 120’ and 330; 120’ is 120 after planarization, see FIGs. 5-6, [0022], [0033], [0045]) encapsulated in the first integrated circuit package (the through vias 120, the semiconductor die 130, and the dummy dies 330 are encapsulated in an insulating encapsulation 140, [0043]), the thermal management components including at least two dummy silicon components (two 330 or two 330s in FIG. 12; each dummy 330 includes 330s, [0033]; material of 330s includes silicon substrate, [0035]) disposed adjacent to respective sides of the first integrated circuit die and configured to spread heat from the first integrated circuit die throughout the first integrated circuit package to enable transfer of the heat to the second integrated circuit package (the dummy dies 330 further serve as heat dissipating elements for the package structure PS1, [0039]; therefore, 330, 330s would spread heat from 130 throughout 10 to enable transfer of heat to 20), the at least two dummy silicon components positioned on opposing sides of the first or second integrated circuit packages (the two 330, 330s are positioned on left and right opposing sides of 10), the opposing in an XY plane (FIG. 12 shows the opposing left and right sides of 10 are in an XY plane passing below or through bottom surfaces of 330, 330s), the XY plane representing a largest dimension of the first or second integrated circuit package (FIG. 12 shows the XY plane would represent a largest dimension of 10).
RE: Claim 11, Hsu discloses wherein:
the first integrated circuit die comprises a system-on-chip integrated circuit die (the semiconductor die 130 described herein may be referred to as a chip or an integrated circuit (IC), [0031]; the semiconductor die 130 includes at least one wireless and radio frequency (RF) chip, [0031]; therefore, 130 includes a system of a wireless and RF chip and is considered a system-on-a-chip integrated circuit die); and
the second integrated circuit die includes a memory integrated circuit die (the semiconductor dies 220 a, 220 b may be logic chips (e.g., central processing units, microcontrollers, etc.), memory chips, [0067]; accordingly, it would have been obvious to try making 220a and/or 220b memory chips as this is one solution for the type of chips in 220a, 220b identified by Hsu and this would have had a reasonable expectation of success).
RE: Claim 12, Hsu discloses wherein the first integrated circuit package further comprises:
a redistribution layer (118, [0018]) to electrically couple the first integrated circuit package to the second integrated circuit package (the conductive pads 250 of the second package 20 are electrically connected to the redistribution circuit structure 118, [0041]; through the redistribution circuit structure 150 and the through vias 120, the semiconductor die 130 is electrically connected to the redistribution circuit structure 118, [0048]; through insulator vias (not shown) or interconnects (not shown) may be used to provide electrical connection between the conductive pads 240 and the conductive pads 250, [0070]); and
a die attach film (CM, [0025]) disposed between the first integrated circuit die and the redistribution layer, the die attach film in thermal contact with the redistribution layer and the first integrated circuit die (FIG. 12 shows CM is in thermal contact with 118 and 130).
RE: Claim 13, Hsu discloses wherein the redistribution layer is a first redistribution layer (118) and the first integrated circuit package further comprises a second redistribution layer (150, [0048]) to which the first integrated circuit die is coupled to via an array of solder interconnects (130 is mechanically coupled to 150 via 310; 310 are solder joints, [0071]), and
wherein the at least two dummy silicon components are disposed between the first redistribution layer and the second redistribution layer (FIG. 12 shows 330 are disposed between 118 and 150).
RE: Claim 14, Hsu discloses wherein the second redistribution layer comprises a heat transfer component (154; 150 includes metallization layers 154, [0050]) configured to transfer heat from the array of solder interconnects coupled to the first integrated circuit die to another array of interconnects (170, [0053]) exposed on an exterior surface of the package-on-package assembly (metallization layers 154 would inherently transfer heat from 310 to 170).
RE: Claim 17, Hsu discloses the assembly further comprising:
an additional thermal management component (a third 330 is shown in FIG. 13A, FIG. 1 to FIG. 12 are the schematic cross-sectional views taken along a cross-sectional line A-A depicted in FIG. 13A, [0014]) encapsulated in the first integrated circuit package (the dummy dies 330 are encapsulated in an insulating encapsulation 140) and in thermal contact with the first integrated circuit die (the third 330 is in thermal contact with 130 through 140), the additional thermal management component comprising a heat spreader configured to spread heat from the first integrated circuit die throughout the first integrated circuit package to enable transfer of the heat to the second integrated circuit package (the dummy dies 330 further serve as heat dissipating elements for the package structure PS1, [0039]; therefore, 330 would spread heat from 130 throughout 10 to enable transfer of heat to 20).
RE: Claim 20, Hsu discloses wherein the first integrated circuit package further comprises a die attach film (CM, [0025]) disposed between the heat spreader and the first integrated circuit die (FIG. 12 shows CM is on sidewalls of each 330, 130; due to the connecting material CM provided between the dummy dies 330 and the redistribution circuit structure 118, the dummy dies 330 and the redistribution circuit structure 118 are stably adhered to each other. In some embodiments, the connecting material CM further physically contacts at least a portion of a sidewall of each dummy die 330, [0032]; accordingly, it would have been obvious to provide enough CM that CM is on sidewalls of the third 330 as shown for the two 330 in FIG. 12 in order to ensure the third 330 is stably adhered; as a result, CM would be between the third 330 and 130).
RE: Claim 21, Hsu discloses wherein two of the at least two dummy silicon components are disposed adjacent to respective sides of the first or second integrated circuit packages (FIG. 12 Hsu shows the at least two 330s are disposed adjacent to respective sides of 10).
Claim(s) 15 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu as applied to claim 10, and further in view of US20180269188A1 to Yu et al. (hereinafter “Yu”).
RE: Claim 15, Hsu discloses the assembly further comprising a plurality of solder interconnects (310 and as discussed below, thermal connectors, [0071]) disposed between the first integrated circuit package and the second integrated circuit package (the conductive pads 250 of the second package 20 are electrically connected to the redistribution circuit structure 118 of the first package 10 through a plurality of joints 310 that are sandwiched therebetween, [0071]; the joints 310 may be referred to as solder joints, [0071]),
Hsu does not explicitly disclose the plurality of solder interconnects including a subset of solder interconnects configured to transfer heat from the first integrated circuit package to the second integrated circuit package;
wherein the subset of solder interconnects configured to transfer heat from the first integrated circuit package to the second integrated circuit package do not electrically couple the first integrated circuit package to the second integrated circuit package.
In a similar field of endeavor, Yu discloses the conductive connectors 316 are not utilized to electrically connect devices or metallization patterns in integrated circuit dies 114 or package structures but are utilized to dissipate heat from the integrated circuit dies 114 and/or package structures, [0044]. Yu further discloses The conductive connectors 314 are utilized to electrically connect the package structure of FIG. 9 to other package structures, [0044].
Yu labels an integrated circuit die 114 including a substrate 118 in FIG. 2, [0019]-[0020] and shows 316 are positioned between the die 114 and other dies 308 in FIG. 10, [0046].
Yu discloses The conductive connectors 314 and thermal connectors 316 may be BGA connectors, solder balls, metal pillars, C4 bumps, micro bumps, ENEPIG formed bumps, or the like, [0045].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add thermal connectors 316 between the die 130 and 220a, 220b which are not electrically connected to devices or metallization patterns or package structures as taught by Yu to help dissipate heat. It would have been further obvious to make the thermal connectors 316 solder balls as this is would have been obvious to try since this is one solution for the thermal connectors 316 provided by Yu and this would have had a reasonable expectation of success. As a result, the thermal connectors would be solder balls that would dissipate heat from 10 to 20. As the thermal connectors are not electrically connected to devices or metallization patterns or package structures, they would not electrically couple the first integrated circuit package 10 to the second integrated circuit package 20.
Claim 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu as applied to claim 10, further in view of US 20210202354 A1 (“Chuang”).
RE: Claim 22, Hsu does not explicitly disclose wherein the at least two dummy silicon components have a greater thermal conductivity than a mold compound in which the package-on-package assembly is encapsulated.
However, Hsu discloses the insulating encapsulation 140 is a molding compound formed, [0044]; the materials of the insulating encapsulation 260 is the same as the insulating encapsulation 140, [0069].
In the same field of endeavor, Chuang discloses the dummy die DM has a thermal conductivity larger than that of the encapsulant P, [0050].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the dummy dies 330 have a greater thermal conductivity than the encapsulant 140 as taught by Chuang in order to improve the thermal conductivity of the dummy dies 330. As a result the dummy dies 330 would have a greater thermal conductivity than that of encapsulants 260. Encapsulants 140, 260 at least partially encapsulate 10, 20.
Claim 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu as applied to claim 10, further in view of US20080160674A1 (“Takiar”).
RE: Claim 23, Hsu does not explicitly disclose wherein the at least two dummy silicon components include no integrated circuitry.
However, Hsu discloses the dummy dies 330 further serve as heat dissipating elements for the package structure PS1, [0039].
In the same field of endeavor, Takiar discloses it is therefore further known to provide a dummy “jumper” die 50 along side a first die, such as die 24. Die 50 may simply be a block of silicon or other material without internal circuitry but having bond pads 52 on its surface, [0010].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make each of the dummy substrates 330s be a block of silicon without internal circuitry as taught by Takiar in order to simplify manufacturing while still using the substates 330s as heat dissipating elements.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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