CTNF 18/042,304 CTNF 71281 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Continued Examination Under 37 CFR 1.114 07-42-04 AIA A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/11/26 has been entered. Election/Restrictions 08-06 AIA Claim s 3, 6-14 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention / species , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/28/25 . Response to Arguments Applicant’s arguments, see Remarks, filed 5/11/26, with respect to the rejection(s) of claim(s) 1, 2, 4, 5 have been fully considered and are persuasive in light of the amendments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made below. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 1, 2, 4, 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2005/0056903 (Yamamoto) in view of U.S. Patent Application Publication No. 2018/0331147 (Takahashi) . Yamamoto discloses 1. (Currently Amended) A semiconductor apparatus comprising: a light-receiving chip 303 configured to receive incident light; a rewiring-side semiconductor chip that includes a semiconductor substrate 401 and wiring layer 409, wherein the wiring layer 409 is on a wiring surface (bottom) of the rewiring-side semiconductor chip; an intermediate semiconductor chip that includes a semiconductor substrate 301 and a wiring layer 309 / 310 / 311 wherein a top side of the semiconductor substrate 401 of the rewiring-side semiconductor chip is bonded to an underside of the semiconductor substrate 301 of the intermediate semiconductor chip; a first pair of bonding surfaces (top and bottom) bonded to the light-receiving chip 303; a second pair of bonding surfaces (top and bottom) bonded to the rewiring-side semiconductor chip; a through-electrode 308 / 408 configured to penetrate the semiconductor substrate 301 of the intermediate semiconductor chip; and a rewiring 406 configured to connect the through-electrode 308 / 408 with the wiring layer 409 of the rewiring-side semiconductor chip , wherein the rewiring 406 is on the wiring surface (top) of the rewiring-side semiconductor chip. Yamamoto fails to disclose a through-electrode configured to penetrate each of the semiconductor substrate of the intermediate semiconductor chip and the semiconductor substrate of the rewiring-side semiconductor chip . Takahashi teaches (at least Figs. 1, 4, 5) A semiconductor apparatus comprising: a through-electrode 64 (81 / 121 / 351) configured to penetrate each of the semiconductor substrate 212 of the intermediate semiconductor chip and the semiconductor substrate 213 of the rewiring-side semiconductor chip. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a through-electrode that penetrates two semiconductor substrates in Yamamoto. The motivation would be to increase utilization efficiency of a substrate as taught by Takahashi. ([0024], [0099]) Yamamoto discloses (Takahashi teaches also) 2. (Currently Amended) The semiconductor apparatus according to claim 1, wherein an end of the through-electrode 308 / 408 reaches the wiring surface (bottom) of the rewiring-side semiconductor chip. Yamamoto discloses 4. (Previously Presented) The semiconductor apparatus according to claim 2, wherein the rewiring-side semiconductor chip has a rectangular shape, and the through-electrode 308 / 408 is along a side of the rewiring-side semiconductor chip. Yamamoto discloses 5. (Previously Presented) The semiconductor apparatus according to claim 2, further comprising an insulating film 307 / 407 configured to insulate the through-electrode 308 / 408 from each of the semiconductor substrate 301 and 401 of the intermediate semiconductor chip and the rewiring-side semiconductor chip . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication No. 2014/0211056 (Fan), 2018/0138225 (Kim), 2019/0237461(Or-Bach), 2019/0386051 (Hong), 2020/0211912 (Chandolu) teach a semiconductor apparatus including stacked chips and a through-electrode . Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/ Primary Examiner, Art Unit 2893 Application/Control Number: 18/042,304 Page 2 Art Unit: 2893 Application/Control Number: 18/042,304 Page 3 Art Unit: 2893 Application/Control Number: 18/042,304 Page 4 Art Unit: 2893 Application/Control Number: 18/042,304 Page 5 Art Unit: 2893 Application/Control Number: 18/042,304 Page 6 Art Unit: 2893 Application/Control Number: 18/042,304 Page 7 Art Unit: 2893
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