Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-24 and 36-37 in the reply filed on 6/27/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 13-14, 18-19, 22-24 and 36-37 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. US 2019/0019875.
Re claim 1, Tsai teaches a semiconductor device (fig11), comprising:
a substrate (12, fig11, [14]);
a gate spacer (22, fig11, [15]) on the substrate;
an interface layer (36, fig11, [22]), a gate dielectric layer (58, fig11, [29]) on the interface layer (36, fig11, [22]), and gate electrode (44, 46, fig11, [23]) on the gate dielectric layer (58, fig11, [29]), wherein the interface layer (36, fig11, [22]), the gate dielectric layer (58, fig11, [29]) and the gate electrode (44, 46, fig11, [23]) are on an inner side of the gate spacer (22, fig11, [15]);
a ferroelectric or negative capacitance material layer (38, fig11, [20]) formed on a sidewall of the gate electrode (44, 46, fig11, [23]) on the inner side of the gate spacer (22, fig11, [15]); and
a source region (24 left, fig2, [15]) and a drain region (24 right, fig2, [15]) that are located on opposite sides of the gate spacer (22, fig11, [15]) on the substrate,
wherein the ferroelectric or negative capacitance material layer (38, fig11, [20]) is located between the gate dielectric layer (58, fig11, [29]) and the gate electrode (44, 46, fig11, [23]), and the ferroelectric or negative capacitance material layer (38, fig11, [20]) is formed in form of spacer (38 used to create or maintain desired space between 58 and 44/46, fig11) on a sidewall of the gate dielectric layer (58, fig11, [29]).
Re claim 3, Tsai teaches the semiconductor device according to claim 1,wherein the ferroelectric or negative capacitance material layer (38, fig11, [20]) extends along a substantially entire height of the sidewall of the gate electrode (44, 46, fig11, [23]).
Re claim 13, Tsai teaches the semiconductor device according to claim 1, wherein the gate dielectric layer (U shaped 58 extend around 38, fig11, [29]) extends on a sidewall of the ferroelectric or negative capacitance material layer (surface of 38 facing 22, fig11, [20]) and a bottom surface of the ferroelectric or negative capacitance material layer (surface of 38 facing 14, fig11, [20]).
Re claim 14, Tsai teaches the semiconductor device according to claim 1,further comprising: a potential equalization layer (60, fig11, [21, 29]) formed on a bottom surface of the ferroelectric or negative capacitance material layer and a sidewall of the ferroelectric or negative capacitance material layer (U shaped 60 formed around 38, fig11, [20]), wherein the potential equalization layer (60, fig11, [21, 29]) is located between the ferroelectric or negative capacitance material layer (38, fig11, [20]) and the gate dielectric layer (58, fig11, [29]).
Re claim 18, Tsai teaches the semiconductor device according to claim 14,wherein the potential equalization layer is a conductive layer comprising at least one of Ti, Ru, Co and Ta (60 as TiN or TaN, fig11, [21, 29]).
Re claim 19, Tsai teaches the semiconductor device according to claim 1, wherein the ferroelectric or negative capacitance material (38 as HfZrO2, fig11, [20]) comprises an oxide containing Hf, Zr, Si and/or Al.
Re claim 22, Tsai teaches the semiconductor device according to claim 1, wherein the semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET) (fig11).
Re claim 23, Tsai teaches the semiconductor device according to claim 1, wherein a capacitance value between the gate electrode and the source region or the drain region is less than zero (C reduced as a result of added negative capacitance material layer 38, fig11).
Re claim 24, Tsai teaches the semiconductor device according to claim 1, wherein the semiconductor device has different threshold voltages according to a state of the ferroelectric or negative capacitance material layer ([4]).
Re claim 36, Tsai teaches an electronic apparatus, comprising the semiconductor device according to claim 1 (fig11, [2]).
Re claim 37, Tsai teaches the electronic apparatus according to claim 36, wherein the electronic apparatus comprises a smart phone (fig11, [2]), a computer (fig11, [2]), a tablet computer, a wearable intelligent device, an artificial intelligence device, or a mobile power supply.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 5-7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. US 2019/0019875 and Sung et al. US 2020/0411695.
Re claim 2, Tsai does not explicitly show the semiconductor device according to claim 1, wherein the gate spacer comprises a further ferroelectric or negative capacitance material layer.
Sung teaches replacing conventional dielectric spacer with a spacer including a ferroelectric material (114, fig1A, [37, 43]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai and Sung to replace 22 of Tsai with a ferroelectric material. The motivation to do so is to optimize drive current while operate the transistor at low voltage (Sung, [36, 37]).
Re claim 5,Tsai modified above teaches the semiconductor device according to claim 2, wherein the gate spacer comprises a plurality layers of spacers (Tsai, 22, fig11, [15]) and the further ferroelectric or negative capacitance material layer is one of the plurality layers of spacers (Tsai, both 26 and 28 replaced by ferroelectric material as in Sung, fig11).
Re claim 6, Tsai modified above teaches the semiconductor device according to claim 5, wherein the plurality layers of spacers comprise: a L-shaped first dielectric spacer (Tsai, 26, fig11, [15]) formed on the sidewall of the gate electrode (Tsai, 46, 44, fig11, [23]); the further ferroelectric or negative capacitance material layer (Tsai, 28 replaced by ferroelectric material as in Sung, fig11) formed on the L- shaped first dielectric spacer (Tsai, 26, fig11, [15]); and a second dielectric spacer (Tsai, 30, fig11, [16]) formed on a sidewall of the further ferroelectric or negative capacitance material layer (Tsai, 28 replaced by ferroelectric material as in Sung, fig11).
Re claim 7, Tsai modified above teaches the semiconductor device according to claim 6, wherein the further ferroelectric or negative capacitance material layer (Tsai, 28 replaced by ferroelectric material as in Sung, fig11) extends along a substantially entire height of a sidewall of the L-shaped first dielectric spacer (Tsai, 26, fig11, [15]).
Re claim 20, Tsai does not explicitly show the semiconductor device according to claim 1, further comprising: a contact portion to the source region and the drain region respectively, wherein the ferroelectric or negative capacitance material layer is located between the contact portion and the gate electrode.
Sung teaches a contact portion (112 and 114, fig1B) to the source region and the drain region respectively.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Tsai and Sung to add metallization structure above the source/drain region with the ferroelectric or negative capacitance material layer located between the contact portion and the gate electrode. The motivation to do so is to access the source/drain region and provide bias voltage (Sung, [37]).
Response to Arguments
Regarding arguments about all the claims applicant's arguments have been fully considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOMING LIU/Examiner, Art Unit 2812