DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, per page 14, filed April 2, 2026, with respect to the title have been fully considered and are persuasive. The objection of January 12, 2026 has been withdrawn.
Applicant’s arguments, per page 17, filed April 2, 2026, with respect to claim 2 have been fully considered and are persuasive. The rejection of January 12, 2026 has been withdrawn.
Applicant's arguments filed April 2, 2026 have been fully considered but they are not persuasive.
Regarding Claim 1, applicant asserts that Kai does not disclose the limitation “a doping concentration in the first source/drain region decreases towards the channel region in the vertical direction, and a doping concentration in the second source/drain region decreases towards the channel region in the vertical direction” since Kai does not disclose the doping concentration distribution decreasing. However, Claim 1 does not recite the distribution limitation so examiner asserts that Kai does still disclose the doping concentration as previously stated in the rejection below.
Status of the Claims
Claims 5-6 are canceled. Claims 2 and 7 are amended. Claims 1-4, and 7-46 are present for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-9, 12, 14, and 26 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kai (US 2021/0050360). Claim 1, Kai discloses (Fig. 47) a NOR-type memory device, comprising: a plurality of device layers (276/460, channel-level insulating layers/channel material layers, Para [0185], hereinafter “device”) stacked on (device is stacked on 9) a substrate (9, substrate, Para [0068]), wherein each of the plurality of device layers comprises a first source/drain region (24, doped semiconductor source layer, Para [0068]) and a second source/drain region (26, doped semiconductor drain layer, Para [0068]) at opposite ends of the device layer in a vertical direction (24 and 26 are at opposite ends of device in a vertical direction), and a channel region (60, semiconductor channel, Para [0126]) between the first source/drain region and the second source/drain region in the vertical direction (60 is between 24 and 26 in the vertical direction); and a gate stack (54/66, memory films/gate electrodes, Para [0185], hereinafter “stack”) that extends vertically with respect to the substrate to pass through each of the plurality of device layers (stack extends vertically with respect to 9 to pass through device), wherein the gate stack comprises a gate conductor layer (66) and a memory functional layer (54) disposed between the gate conductor layer and the device layer (54 is between 66 and device), and a memory cell is defined at an intersection of the gate stack and the device layer (memory cell would be defined at intersection of stack and device), wherein a doping concentration in the first source/drain region (24) decreases towards the channel region in the vertical direction (since 24 has larger doping concentration (5E19 to 2E21) than 60 (1E14 to 3E17) there would be a decrease going from 24 towards 60 in the vertical direction, Para [0123]), and a doping concentration in the second source/drain region decreases towards the channel region in the vertical direction (since 26 has larger doping concentration (5E19 to 2E21) than 60 (1E14 to 3E17) there would be a decrease going from 26 towards 60 in the vertical direction, Para [0123]).
Claim 3, Kai discloses (Fig. 47) the NOR-type memory device according to claim 1, further comprising: an interface layer (interface between 24 and 460, under broadest reasonable interpretation (BRI) considered interface layer, hereinafter “int1”) on a side of the first source/drain region away from the channel region (int1 is away from 60) and an interface layer (interface between 26 and 460, under broadest reasonable interpretation (BRI) considered interface layer, hereinafter “int2”) on a side of the second source/drain region away from the channel region (int2 is away from 60). Claim 4, Kai discloses (Fig. 47) the NOR-type memory device according to claim 1, wherein the highest doping concentration in the first source/drain region (24) is higher than 1E20 cm-3 (highest doping concentration of 24 is 2E21, Para [0123]), and the highest doping concentration in the second source/drain region is higher than 1E20 cm-3 (highest doping concentration of 26 is 2E21, Para [0123]). Claim 8, Kai discloses (Fig. 47) the NOR-type memory device according to claim 1, wherein the device layer (device) comprises: a base layer (276); and a semiconductor layer (460) on a sidewall of the base layer facing the gate stack (460 is on formed on sidewall of 276 facing stack), wherein the channel region (60) is substantially formed in the semiconductor layer (60 is formed in 460). Claim 9, Kai discloses (Fig. 47) the NOR-type memory device according to claim 1, wherein the memory functional layer (54) comprises at least one of a charge trapping material or a ferroelectric material (54 has material for trapping charges, Para [0089]). Claim 12, Kai discloses (Fig. 47) the NOR-type memory device according to claim 8, wherein the semiconductor layer (460) comprises a semiconductor material different from the base layer (276 may be doped silicate glass, and 460 can be silicon silicon-germanium, Para [0184]- [0187]). Claim 14, Kai discloses (Fig. 47) the NOR-type memory device according to claim 1, wherein the channel region (60) comprises a dopant (60 is semiconductor material with second doping, Para [0088]), wherein a conductive type of the dopant in the channel region is opposite (dopant of 60 is second conductivity type which is opposite of first conductivity typer, Para [0088]) to a conductive type of a dopant in each of the first source/drain region and the second source/drain region (24/26 has a first conductivity typer, Para [0123]). Claim 26, Kai discloses (Fig. 47) the NOR-type memory device according to claim 1, further comprising: a word line (98, word lines, Para [0188]); and a sixth contact portion (68, contact pad, Para [0188]) to the gate conductor layer (66), wherein the sixth contact portion is electrically connected to the word line (68 is electrically connected to 98 through 88, Para [0188]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kai (US 2021/0050360) as applied to claims 1 and 8 above, and further in view of Yada (US 2015/0179660).
Claim 10, Kai discloses the NOR-type memory device according to claim 1. Kai does not explicitly disclose wherein the device layer comprises a single crystal semiconductor material. However, Yada discloses where a channel layer of a memory device comprises singly crystalline silicon (Para [0013]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the single crystalline silicon material of Yada to device of Kai as it leads to higher bottom select gate performance (Yada, Para [0013]). Claim 11, Kai discloses the NOR-type memory device according to claim 8. Kai does not explicitly disclose wherein the semiconductor layer comprises a single crystal semiconductor material. However, Yada discloses where a channel layer of a memory device comprises singly crystalline silicon (Para [0013]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the single crystalline silicon material of Yada to device of Kai as it leads to higher bottom select gate performance (Yada, Para [0013]).
Claim(s) 45-46 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kai (US 2021/0050360) as applied to claim 1 , and further in view of Forbes (US 2005/0082599). Claim 45, Kai discloses the NOR-type memory device according to claim 1. Kai does not explicitly disclose an electronic apparatus comprising the NOR-type memory device according to claim 1. However, Forbes discloses utilizing memories such as NOR for forming electronic apparatuses (Para [0082] – [0083]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the memory device of Kai to a larger apparatus as it forms an integral element in a electronic system. Claim 46, Kai in view of Forbes disclose the electronic apparatus according to claim 45, wherein the electronic apparatus comprises a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply (Forbes, Para[ 0082] applications for the memory cells can be a cell phone, computer).
Allowable Subject Matter
Claims 13 and 15-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Kai (US 2021/0050360), Yada (US 2015/0179660), Forbes (US 2005/0082599), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 13, wherein the first doped region of the semiconductor layer is substantially coplanar to the first doped region of the base layer in a transverse direction, and the second doped region of the semiconductor layer is substantially coplanar to the second doped region of the base layer in the transverse direction, wherein the first doped regions define the first source/drain region, and the second doped regions define the second source/drain region.
Regarding Claim 15, a doping concentration of the channel region on a side of the channel region close to the gate stack is lower than a doping concentration of the channel region on a side of the channel region away from the gate stack.
Regarding Claim 16 (from which claims 17-25 depend), wherein the first contact portion is electrically connected to the first bit line, and the second contact portion is electrically connected to the source line.
Claims 2, 7, and 27-44 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Kai (US 2021/0050360), Yada (US 2015/0179660), Forbes (US 2005/0082599), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 2 (from which claim 7 depends), wherein the isolation layer contains a dopant identical to a dopant in each of the first source/drain region and the second source/drain region.
Regarding Claim 27 (from which claims 28-44 depend), driving the dopant from the solid phase dopant source layer into opposite ends of the device layer by annealing…
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.G.R/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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