DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species – I and Claims 1-14, 16-34 and 36-39 in the reply filed on 8/25/2025 is acknowledged.
Claims 15 and 35 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species – II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/25/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 38-39 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 38 recites “an electronic apparatus comprising the NOR-type memory device according to claim 1”, which does not further limit claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim 39 depends from claim 38 and is rejected for at least the reasons above.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Purayath et al. (US 2022/0028876 A1).
Re Claim 1, Purayath teaches a NOR-type memory device, comprising:
a gate stack (251+252, Fig. 2i, para [0050]) extending vertically (see Fig. 2i) on a substrate (202, Fig. 2i, para [0039]), wherein the gate stack (251+252) comprises a gate conductor layer (252) and a memory functional layer (251); and
a first semiconductor layer (204b+204d+250 of 1st layer, marked in annotated Fig. 2i below, paras [0047] - [0048]) and a second semiconductor layer (204b+204d+250 of 2nd layer, marked in annotated Fig. 2i below) that surround a periphery of the gate stack (251+252, see Fig. 2i) and extend along a sidewall of the gate stack (see Fig. 2i),
wherein the first semiconductor layer (204b+204d+250 of 1st layer, Fig. 2i) and the second semiconductor layer (204b+204d+250 of 2nd layer) are respectively located at different heights (see Fig. 2i) with respect to the substrate (202), wherein the memory functional layer (251) is located between the first semiconductor layer (204b+204d+250 of 1st layer) and the gate conductor layer (252), and between the second semiconductor layer (204b+204d+250 of 2nd layer) and the gate conductor layer (252),
wherein each of the first semiconductor layer (204b+204d+250 of 1st layer) and the second semiconductor layer (204b+204d+250 of 2nd layer) comprises a first source/drain region (204b, Fig. 2i, para [0047]), a channel region (250, Fig. 2i, para [0048]), and a second source/drain region (204d, Fig. 2i, para [0047]) that are disposed in sequence in a vertical direction (see Fig. 2i), and
wherein a memory cell (paras [0047] – [0049]) is defined at each of an intersection of the gate stack (251+252) and the first semiconductor layer (204b+204d+250 of 1st layer) and an intersection of the gate stack (251+252) and the second semiconductor layer (204b+204d+250 of 2nd layer).
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Re Claim 3, Purayath teaches the NOR-type memory device according to claim 1, wherein the memory functional layer (251) comprises at least one of a charge trapping material (251 is a charge trapping layer, para [0049]) or a ferroelectric material.
Re Claim 5, Purayath teaches the NOR-type memory device according to claim 1, wherein the memory functional layer (251) is formed on a bottom surface of the gate conductor layer (252, see Fig. 2i) and a sidewall of the gate conductor layer (252, see Fig. 2i).
Re Claim 6, Purayath teaches the NOR-type memory device according to claim 1, wherein the first semiconductor layer (204b+204d+250 of 1st layer) is substantially coplanar (see Fig. 2i) to the second semiconductor layer in the vertical direction (204b+204d+250 of 2nd layer).
Re Claim 38, Purayath teaches an electronic apparatus comprising the NOR-type memory device according to claim 1 (paras [0007] – [0008]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Purayath et al. (US 2022/0028876 A1), and further in view of Ahn et al. (US 2021/0375872 A1).
Re Claim 4, Purayath teaches the NOR-type memory device according to claim 1, wherein the semiconductor layer (204b+204d+250) comprises a semiconductor material (204b+204d can be amorphous silicon, para [0047], while 250 can be polycrystalline silicon, para [0048]).
Purayath does not teach that the semiconductor layer can be made of single crystal semiconductor material.
However, in a related semiconductor art Ahn teaches that the semiconductor layer can be made of either polycrystalline silicon or single crystal silicon (para [0116]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Purayath, such that the semiconductor layer is made of single crystal silicon rather than polycrystalline silicon, as taught by Ahn, which will yield predictable result. The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Additionally, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Purayath et al. (US 2022/0028876 A1), and further in view of Okajima et al. (US 2021/0313340 A1).
Re Claim 18, Purayath teaches the NOR-type memory device according to claim 1, and teaches that the gate conductor 252 is connected to a word line (para [0049]) but does not explicitly show the word line and does not show a fourth contact portion to the gate conductor layer, wherein the fourth contact portion is electrically connected to the word line.
In a related semiconductor art, Okajima discloses a similar NOR-type device (Fig. 4) where the gate conductor 30 (Fig. 4, para [0140]) is connected to the word line 24 (Fig. 4) via the contact portion 23 (Fig. 4, para [0143]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the device of Purayath to connect the gate conductor to the word line according to the teachings of Okajima, in order to have a functional NOR device where the voltage in the gate conductor is controlled via the word line.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Purayath et al. (US 2022/0028876 A1).
Re Claim 19, Purayath teaches the NOR-type memory device according to claim 1, wherein each of the first semiconductor layer (204b+204d+250 of 1st layer) and the second semiconductor layer (204b+204d+250 of 2nd layer) is extending vertically (see Fig. 2i) and having annular cross-section (see Figs. 2h and 2i).
Purayath does not explicitly state that the semiconductor layer is a nanosheet. However, it does disclose that the width of the openings where the gate stacks are formed are about 100 nm in diameter (para [0042]). Considering that the annular channel layer 250 of the semiconductor layer is formed within this opening, it will have a thickness within a range 10-40 nm (compare Fig. 2i), which can be considered a nanosheet. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the semiconductor layer has a channel layer which is a nanosheet as it will have a thickness within a range 10-40 nm.
Claims 20-22, 25-26, 31-32, 34 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Purayath et al. (US 2022/0028876 A1), and further in view of Yamazaki et al. (US 2021/0135010 A1).
Re Claim 20, Purayath teaches a method of manufacturing a NOR-type memory device, comprising:
disposing a plurality of device layers (marked “device layers” in annotated Fig. 2i below) on a substrate (202, Fig. 2i, para [0039]), wherein each of the plurality of device layers (“device layers” in annotated Fig. 2i below) comprises a stack of a first source/drain defining layer (204b, Fig. 2i, para [0047]), a first channel defining layer (204c, Fig. 2i, para [0047]), and a second source/drain defining layer (204d, Fig. 2i, para [0047]);
forming a processing channel (218, Fig. 2h(ii), para [0042]) that extends vertically with respect to the substrate (202) to pass through the stack in each device layer (see Fig. 2h(ii));
growing a semiconductor layer (250, Figs. 2h(ii) and 2i, para [0048]) on a sidewall of each device layer (see Figs. 2h(ii) and 2i) exposed in the processing channel (218) through the processing channel (see Figs. 2h(ii), para [0048]); and
forming a gate stack (251+252, Fig. 2i, para [0049]) in the processing channel (218), wherein the gate stack comprises a gate conductor layer (252) and a memory functional layer (251) disposed between the gate conductor layer (252) and the semiconductor layer (250), and a memory cell is defined (paras [0047] – [0049]) at an intersection of the gate stack (251+252) and the semiconductor layer (250).
Purayath does not disclose how the semiconductor layer is grown and hence doesn’t teach that the semiconductor layer is epitaxially grown.
However, in a related semiconductor art, Yamazaki teaches a memory device where the conductors, insulators and the semiconductor layers can be formed by a variety of method including a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like (para [0255]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the semiconductor layer of Purayath can be made epitaxially as taught by Yamazaki. The selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
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Re Claim 21, Purayath modified by Yamazaki teaches the method according to claim 20, wherein the stack of at least one of the plurality of device layers (“device layer”, Purayath) further comprises a second channel defining layer (2nd 204c layer within “device layer”, also annotated in Fig. 2i above, para [0047], Purayath) and a third source/drain defining layer (2nd 204b layer within “device layer”, also annotated in Fig. 2i above Fig. 2i, para [0047], Purayath).
Re Claim 22, Purayath modified by Yamazaki teaches the method according to claim 20, wherein the stack is formed by epitaxial growth (para [0255], Yamazaki).
Re Claim 25, Purayath modified by Yamazaki teaches the method according to claim 20, further comprising: recessing the sidewall of the device layer (“device layer”, Purayath) exposed in the processing channel (218) to a certain depth in a transverse direction (x-direction in Fig. 2h(ii), Purayath) by etching via the processing channel (see para [0048], Purayath).
Re Claim 26, Purayath modified by Yamazaki teaches the method according to claim 25, wherein respective sidewalls of the plurality of device layers (“device layer”) are substantially coplanar to each other in the vertical direction after being recessed (see Fig. 2h(ii), Purayath).
Re Claim 31, Purayath modified by Yamazaki teaches the method according to claim 20, wherein forming the gate stack (251+252, Purayath) comprises:
forming the memory functional layer (251) on a bottom surface of the processing channel (218, see Fig. 2i, Purayath) and a sidewall of the processing channel (218) in a substantially conformal manner (see Fig. 2i, para [0049], Purayath); and
filling the processing channel (218), on which the memory functional layer is formed (251), with the gate conductor layer (252, see Fig. 2i, para [0049], Purayath).
Re Claim 32, Purayath modified by Yamazaki teaches the method according to claim 20, wherein a plurality of processing channels (218) arranged in an array are formed (see Fig. 2h(i), Purayath).
Re Claim 34, Purayath modified by Yamazaki teaches the method according to claim 21, wherein the substrate comprises a device region (101, Fig. 1, paras [0036] – [0038], Purayath) and a contact region (102a+102b, Fig. 1, para [0038], Purayath) adjacent to the device region (101), the memory cell is formed on the device region (para [0036] – [0037], Purayath), and the method further comprises:
forming, on the contact region (102a+102b), a first contact portion to the first source/drain defining layer, a second contact portion to the second source/drain defining layer, and a third contact portion to the third source/drain defining layer (102a and 102b allow connections through conductive vias to the bit lines and the source lines of the NOR memory strings, para [0038], where source/drain defining layer 204b and 204 are the bit lines and the source lines respectively, para [0047], Purayath).
Re Claim 36, Purayath modified by Yamazaki teaches the method according to claim 34, further comprising:
patterning the first source/drain defining layer, the second source/drain defining layer, and the third source/drain defining layer in each device layer into a step structure in the contact region (Fig. 2a(ii), para [0040], Purayath).
Claims 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Purayath et al. (US 2022/0028876 A1) and Yamazaki et al. (US 2021/0135010 A1), and further in view of Zhu et al. (US 2020/0035696 A1).
Re Claim 23, Purayath modified by Yamazaki teaches the method according to claim 22, wherein at least each source/drain defining layer in the stack is doped (204b/204d are doped, para [0047], Purayath).
Purayath modified by Yamazaki does not disclose when the doping process is performed and hence does not teach that the doping is done in situ during epitaxial growth.
However, in a related semiconductor art, Zhu teaches that the doping of the source/drain layers can be performed epitaxially in-situ (para [0034]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the source/drain layers of Purayath modified by Yamazaki can be doped in-situ during the epitaxial growth as taught by Zhu. The selection of a known process based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Re Claim 24, Purayath modified by Yamazaki and Zhu teaches the method according to claim 23, but does not disclose performing an annealing treatment, so that a dopant in the stack diffuses transversely into the semiconductor layer.
Zhu, however discloses an annealing treatment of the source/drain defining layers, such that the dopants can diffuse into the channel defining semiconductor layer (paras [0055] – [0056]), thus improving the mobility of the charge carriers within the channel.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to anneal the source/drain defining layers of Purayath modified by Yamazaki and Zhu, such that the dopants can diffuse into the channel defining semiconductor layer (paras [0055] – [0056], Zhu), thus improving the mobility of the charge carriers within the channel.
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over Purayath et al. (US 2022/0028876 A1), and further in view of Lee et al. (US 2018/0277558 A1).
Re Claim 39, Purayath teaches the electronic apparatus according to claim 38, but does not disclose that the electronic apparatus comprises a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.
In a related semiconductor art, Lee discloses a memory device with a NOR or NAND memory interface (para [0087]) and can be used in a computer or phone (para [0100]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, that the device of Purayath can be used in a computer or a phone as disclosed by Lee, as the device can be used as a memory component for the computer or phone.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3-5 and 38-39 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 16-20 of U.S. Patent No. 12,477,804. Although the claims at issue are not identical, they are not patentably distinct from each other as shown below.
US Patent No. 12,477,804
Instant application
1. A NOR-type storage device, comprising:
a gate stack extending vertically on a substrate, the gate stack comprising a gate conductor layer and a storage function layer;
an active region surrounding a periphery of the gate stack, wherein the active region comprises a first source/drain region and a second source/drain region respectively located at different heights with respect to the substrate, and a first channel region located between the first source/drain region and the second source/drain region in a vertical direction, the active region further comprises a third source/drain region and a fourth source/drain region respectively located at different heights with respect to the substrate, and a second channel region located between the third source/drain region and the fourth source/drain region in the vertical direction,
the storage function layer is arranged between the gate conductor layer and the active region,
a first storage cell is defined at an intersection of the gate stack with the first source/drain region, the first channel region and the second source/drain region, and a second storage cell is defined at an intersection of the gate stack with the third source/drain region, the second channel region and the fourth source/drain region;
a first interconnection layer, a second interconnection layer, a third interconnection layer, and a fourth interconnection layer extending laterally from the first source/drain region, the second source/drain region, the third source/drain region, and the fourth source/drain region, respectively; and
a source line contact part extending vertically with respect to the substrate to pass through the first interconnection layer, the second interconnection layer, the third interconnection layer, and the fourth interconnection layer, wherein the source line contact part is electrically connected to one of the first interconnection layer and the second interconnection layer, and electrically connected to one of the third interconnection layer and the fourth interconnection layer.
16. The NOR-type storage device according to claim 1, wherein the storage function layer comprises at least one of a charge trapping material or a ferroelectric material.
17. The NOR-type storage device according to claim 1, wherein the active region comprises a single crystal semiconductor material.
18. The NOR-type storage device according to claim 1, wherein the storage function layer is formed on a bottom surface of the gate conductor layer and a sidewall of the gate conductor layer.
19. An electronic apparatus, comprising the NOR-type storage device according to claim 1.
20. The electronic apparatus according to claim 19, wherein the electronic apparatus comprises a smart phone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply.
1. A NOR-type memory device, comprising:
a gate stack extending vertically on a substrate, wherein the gate stack comprises a gate conductor layer and a memory functional layer; and
a first semiconductor layer and a second semiconductor layer that surround a periphery of the gate stack and extend along a sidewall of the gate stack, wherein the first semiconductor layer and the second semiconductor layer are respectively located at different heights with respect to the substrate, wherein each of the first semiconductor layer and the second semiconductor layer comprises a first source/drain region, a channel region, and a second source/drain region that are disposed in sequence in a vertical direction, and
wherein the memory functional layer is located between the first semiconductor layer and the gate conductor layer, and between the second semiconductor layer and the gate conductor layer,
wherein a memory cell is defined at each of an intersection of the gate stack and the first semiconductor layer and an intersection of the gate stack and the second semiconductor layer.
3. The NOR-type memory device according to claim 1, wherein the memory functional layer comprises at least one of a charge trapping material or a ferroelectric material.
4. The NOR-type memory device according to claim 1, wherein the semiconductor layer comprises a single crystal semiconductor material.
5. The NOR-type memory device according to claim 1, wherein the memory functional layer is formed on a bottom surface of the gate conductor layer and a sidewall of the gate conductor layer.
38. An electronic apparatus comprising the NOR-type memory device according to claim 1.
39. The electronic apparatus according to claim 38, wherein the electronic apparatus comprises a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply.
Claim 20 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of co-pending Application No. 18/041085 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other as shown below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Co-pending Application No. 18/041085
Instant application
17. A method of manufacturing a NOR-type memory device, comprising: providing a plurality of device layers on a substrate, wherein each of the plurality of device layers comprises a stack of a first source/drain defining layer, a first channel defining layer and a second source/drain defining layer;
forming a processing channel that extends vertically with respect to the substrate to pass through the stack in each device layer;
epitaxially growing, through the processing channel, a semiconductor layer on a sidewall of each device layer exposed in the processing channel; forming a gate stack in the processing channel, wherein the gate stack comprises a gate conductor layer and a memory functional layer arranged between the gate conductor layer and the semiconductor layer, and
a memory cell is defined at an intersection of the gate stack and the semiconductor layer;
removing the first channel defining layer in each device layer by a selective etching; and forming a dielectric layer and a conductive shielding layer in sequence in a gap formed by a removal of the first channel defining layer.
20. A method of manufacturing a NOR-type memory device, comprising: disposing a plurality of device layers on a substrate, wherein each of the plurality of device layers comprises a stack of a first source/drain defining layer, a first channel defining layer, and a second source/drain defining layer;
forming a processing channel that extends vertically with respect to the substrate to pass through the stack in each device layer;
epitaxially growing a semiconductor layer on a sidewall of each device layer exposed in the processing channel through the processing channel; and forming a gate stack in the processing channel, wherein the gate stack comprises a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the semiconductor layer, and
a memory cell is defined at an intersection of the gate stack and the semiconductor layer.
Allowable Subject Matter
Claims 2, 7-14, 16-17, 27-30, 33 and 37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowable subject matter:
Claim 2 is allowable for at least the reasons of, “wherein each of the first semiconductor layer and the second semiconductor layer further comprises a second channel region and a third source/drain region that are disposed in sequence in the vertical direction, so that the second channel region is located between the second source/drain region and the third source/drain region in the vertical direction”. The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 1, as a whole. For example, Purayath et al. teaches “a second channel region and a third source/drain region that are disposed in sequence in the vertical direction” in Fig. 2i, but they are not within the same semiconductor layer, but are part of a different semiconductor layer.
Claims 7-14 and 16-17 depend from claim 2 and are allowable for at least the reasons above.
Claim 27 is allowable for at least the reasons of, “forming a sacrificial layer between at least one pair of adjacent device layers, wherein after disposing the plurality of device layers, the method further comprises replacing the sacrificial layer by an isolation layer.” The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 20, as a whole.
Claims 28-30 depend from claim 27 and are allowable for at least the reasons above.
Claim 33 is allowable for at least the reasons of, “removing each channel defining layer in the device layer by selective etching; and filling a gap obtained by the removing of the channel defining layer with a dielectric.” The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 20, as a whole.
Claim 37 is allowable for at least the reasons of, “comprises a step with a transverse surface and a vertical surface, and the method further comprises: siliconizing the transverse surface of the step.” The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 20, as a whole. Prior art, Lee et al. (US 2018/0277558 A1) teaches forming a dielectric spacer (14, Fig. 1A, para [0024]) on the vertical surface of the step (Fig. 1A) but does not teach siliconizing or silicide formation on the transverse surface of the step.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lai’899 et al. (US 2020/0258899 A1) teaches a very similar NOR-type memory structure.
Lai’191 et al. (US 2021/0351191 A1) teaches a very similar NOR-type memory structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898